CN209132758U - Multi core chip data/address bus wire structures - Google Patents
Multi core chip data/address bus wire structures Download PDFInfo
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- CN209132758U CN209132758U CN201821774905.4U CN201821774905U CN209132758U CN 209132758 U CN209132758 U CN 209132758U CN 201821774905 U CN201821774905 U CN 201821774905U CN 209132758 U CN209132758 U CN 209132758U
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Abstract
The utility model embodiment provides a kind of multi core chip data/address bus wire structures, and each kernel in N number of kernel arranges the data/address bus of a transmission data；The chip core can only send data to other kernels on its corresponding data/address bus for sending data, and receive data from other kernels from the data/address bus of transmission data described in other remaining N-1 items.Using the technical solution of the utility model, it is possible to reduce chip connects the quantity of kernel data bus, saves chip interior wiring space, reduces the interference between data/address bus, and improve data transfer speed increases the utilization rate of bandwidth.
Description
Technical field
The utility model embodiment is related to integrated circuit fields, more particularly to a kind of multi core chip data/address bus wire bond
Structure.
Background technique
ASIC (Application Specific Integrated Circuits) i.e. specific integrated circuit, refers to Ying Te
Determine the integrated circuit that user requires the needs with particular electronic system and designs, manufactures.The characteristics of ASIC is towards specific user
Demand, ASIC batch production when with universal integrated circuit compared with have volume is smaller, power consumption is lower, reliability raising, property
The advantages that energy improves, confidentiality enhances, cost reduces.
With the development of science and technology, more and more fields, such as artificial intelligence, safe operation etc. are directed to macrooperation amount
Specific calculation.For certain operations, asic chip can play that its operation is fast, and small power consumption etc. is specific.Meanwhile for these big fortune
Calculation amount field, in order to improve the processing speed and processing capacity of data, it usually needs control N number of operation chip while carrying out work
Make.It needs to be arranged multiple kernels (core) in asic chip to come while carrying out operation, these kernels need mutual data transmission
And order, therefore any dinuclear to be supported to interconnect；The data bus lines quantity of chip interior increases and index with nuclear volume
Increase；But since chip area is small, cause kernel interconnection space limited, as shown in Figure 1 often in longer and narrower space
Data/address bus wires design is carried out, since wiring space resource is nervous, actual bus track lengths should be short as far as possible, and avoiding unrolling accounts for
Use interconnection resource.And traditional loop wire topological structure and concentration arbitration structure make data/address bus be routed explicit congestion, and require
Bus needs are utmostly parallel, prevent from influencing each other and reducing bandwidth.
Summary of the invention
The utility model embodiment provides a kind of multi core chip data/address bus wire structures, it is possible to reduce chip connects kernel
The quantity of data/address bus, save chip interior wiring space, reduce data/address bus between interference, improve data transfer speed,
Increase the utilization rate of bandwidth.
In order to achieve the above objectives, the utility model embodiment provides the following technical solutions:
It is described according to the utility model embodiment in a first aspect, provide a kind of multi core chip data/address bus wire structures
Chip core quantity is N, and wherein N is the positive integer more than or equal to 2, and each kernel in N number of kernel arranges a transmission data
Data/address bus, each in data/address bus described in N item is served only for a kernel in N number of kernel and sends number to other kernels
According to.
Preferably, N number of tie point is set on every data/address bus, and each of described N number of kernel kernel is logical
It crosses a tie point and connects the data/address bus.
Preferably, for only one kernel by tie point transmission data, other kernels are logical on every data/address bus
It crosses tie point and receives the data transmitted on the data/address bus.
Preferably, each kernel is by the data/address bus for the transmission data being arranged for the kernel into other
Core sends data, receives data from data/address bus described in remaining N-1 item from other kernels.
Preferably, the tie point includes N number of pipeline node PN, wherein one in N number of pipeline node PN and described
The data/address bus for sending data is connected；Remaining N-1 pipeline node PN sends the data/address bus phase of data with other kernels respectively
Even.
Preferably, the pipeline node PN of the data/address bus for sending data is connected for obtaining the kernel number to be sent
According to being sent to the pipeline of purpose kernel by the data/address bus for sending data according to the data destination address to be sent
Node PN.
Preferably, the data that the remaining N-1 pipeline node PN is used to send data according to other described kernels are total
The data destination address transmitted in line is forwarded to data or obtains operation；N-1 pipeline node PN of the residue is by mesh
Address be this kernel address data obtained and be sent to described kernel.
Preferably, kernel selects the pipeline node PN of data to be sent by selecting unit.
Preferably, every data/address bus wire structures are " bow " font cabling form, and N data bus is not handed over
Crunode.
Preferably, the data/address bus wire structures are " П " font cabling form, and N data bus is not intersected
Point.
According to the second aspect of the utility model embodiment, a kind of multi core chip data/address bus wire structures are provided, it is described
Chip core quantity is N, and wherein N is the positive integer more than or equal to 2, it is characterised in that: each kernel arrangement one in N number of kernel
The data/address bus of item transmission data；The chip core can only give other kernels on its corresponding data/address bus for sending data
Data are sent, and receive data from other kernels from the data/address bus of transmission data described in other remaining N-1 items；It is described its
The data of other kernels transmission are not transmitted on the corresponding data/address bus for sending data.
The utility model embodiment is the data/address bus that each kernel in multiple kernels arranges a transmission data；It is described
Chip core can only give other kernels to send data on its corresponding data/address bus for sending data, and from remaining in other
Data are received from other kernels on the data/address bus of the transmission data of core；In the corresponding data for sending data of the kernel
The data of other kernels transmission are not transmitted in bus.Using the technical solution of the utility model, it is possible to reduce chip connects kernel
The quantity of data/address bus, save chip interior wiring space, reduce data/address bus between interference, improve data transfer speed,
Increase the utilization rate of bandwidth.
Detailed description of the invention
In order to illustrate the embodiment of the utility model or the technical proposal in the existing technology more clearly, below will be to embodiment
Or attached drawing needed to be used in the description of the prior art is briefly described, it should be apparent that, the accompanying drawings in the following description is only
Some embodiments are exemplary, for those of ordinary skill in the art, without creative efforts, also
Other drawings may be obtained according to these drawings without any creative labor.
Fig. 1 illustrates the schematic diagram of the multi core chip data/address bus wire structures of the prior art；
Fig. 2 illustrates the signal of the data/address bus wire structures of the transmission data of the first kernel of multi core chip of first embodiment
Figure；
Fig. 3 illustrates the data/address bus wire structures of the transmission data of the first and second kernel of multi core chip of first embodiment
Schematic diagram；
Fig. 4 a illustrates the data of the transmission data of the first kernel of multi core chip of second embodiment according to the present utility model
The schematic diagram of route bus structure；
Fig. 4 b illustrates the data/address bus wire bond of the transmission data of the first and second kernel of multi core chip of second embodiment
The schematic diagram of structure.
Fig. 5 illustrates the structural schematic diagram of parallel first in, first out unit pfifo and bus pipeline BP according to the present utility model；
Fig. 6 illustrates data structure schematic diagram according to the present utility model；
Fig. 7 illustrates the transmission data of the first kernel according to the present utility model and receives the schematic diagram of data.
Specific embodiment
The illustrative embodiments of the utility model will be illustrated based on attached drawing below, it should be understood that provide these realities
Mode is applied just for the sake of making those skilled in the art can better understand that realizing the utility model in turn, and be not with any
Mode limits the scope of the utility model.On the contrary, these embodiments are provided so that this disclosure will be more thorough and complete, and
And the scope of the present disclosure can be completely communicated to those skilled in the art.
Furthermore, it is necessary to specification, all directions of the upper and lower, left and right in each attached drawing are only with specific embodiment
The illustration of progress, those skilled in the art part or all by each component shown in the drawings can change according to actual needs
It changing direction to apply, integrally realizing its function without will affect each component or system, this technical solution for changing direction is still
Belong to the protection scope of the utility model.
Multi core chip is the multiprocessing system for being embodied in single large-scale integrated semiconductor core on piece.Typically, two
Or more chip core can be embodied on multi core chip, this (can also be formed on identical multi core chip by bus
Bus) it is interconnected.Can have from two chip cores to many chip cores and be embodied on identical multi core chip,
The upper limit in the quantity of chip core is only limited by manufacturing capacity and performance constraints.Multi core chip can have application, this is answered
With included in multimedia and signal processing algorithm (such as, encoding and decoding of video, 2D/3D figure, audio and speech processes, image
Processing, phone, speech recognition and sound rendering, encryption) in execute special arithmetic and/or logical operation.
Although having referred only ASIC specific integrated circuit in the background technology, the specific wiring in embodiment is realized
Mode can be applied to in multi core chip CPU, GPU, FPGA etc..Multiple kernels can be in identical in the present embodiment
Core is also possible to different kernels.
[embodiment 1]
For convenience of explanation, will be illustrated for the chip of 8 kernels present in Fig. 2 below, it is each in verification
A node is answered, each kernel has a data bus.And skilled person will appreciate that, for selecting 8 kernels here,
It is only exemplary explanation, kernel number can be N, and wherein N is the positive integer more than or equal to 2, such as can be 3,6,9 etc.
Deng.Multiple kernels can be same kernel in the present embodiment, be also possible to different kernels.
Fig. 2 illustrates the signal of the data/address bus wire structures of the transmission data of the first kernel of multi core chip of first embodiment
Figure.As shown in Fig. 2, inside the chip 10 include 8 kernel core100, core101, core102, core103, core104,
Core105, core106 and core107；A parallel first in, first out unit is arranged in each kernel core (100 ... 107)
And kernel core 200 ... 207) (parallel FIFO, (bus_pipe, 300 ... 307) by bus pipeline BP by pfifo
(103) the data/address bus BS (data bus, 403) of transmission data.
The data/address bus BS (data bus, 403) of kernel core (103) is simply shown in fig 2, in practice often
The data/address bus BS (data bus) of 1 transmission data is all arranged in one kernel core (100 ... 107), has in fig 2
There are 8 kernels, it is seen that there is the data/address bus BS (data bus) of 8 transmission data.Although data/address bus BS in fig 2
(data bus 403) is divided into 7 sections, but data/address bus BS (403) is also possible to a continuous data line.Each kernel
The data/address bus BS that core individually sends data using oneself carries out data transmission, uses the transmission data of other kernels core
Data/address bus BS receive data.The data/address bus BS of the transmission data of kernel core103 is simply shown in fig 2
(data bus 403), be in order to allow those skilled in the art to can be convenient ground, clearly find out the wire laying mode of data/address bus,
It here is using " bow " font wire laying mode.It is then 1 transmission number of each kernel setup if the quantity of kernel in fruit chip is N
According to data/address bus BS, then altogether with N item send data data/address bus BS, chip core can only be in its corresponding transmission number
According to data/address bus on to other kernels send data, and from the data/address bus of transmission data described in other remaining N-1 items from
Other kernels receive data, and the number of other kernels transmission cannot be transmitted on the corresponding data/address bus for sending data of the chip
According to.
A Transmit-Receive Unit or access point is arranged to connect data bus B S in each kernel core (100 ... 107)
(data bus).Transmit-Receive Unit or access point include parallel first in, first out unit pfifo (parallel FIFO, 200 ...
207) (bus_pipe, 300 ... 307) with bus pipeline BP.With reference to the accompanying drawing 5 couples of parallel first in, first out unit pfifo and
The structure and working principle of bus pipeline BP is described in detail.
Fig. 5 illustrates the structural schematic diagram of parallel first in, first out unit pfifo and bus pipeline BP according to the present utility model.
With reference to the accompanying drawings 5 it is found that the parallel first in, first out unit pfifo (input parallel FIFO, 20) include receptions singly
First (221), multiple output units (222) and control unit (223).The receiving unit (221) is connected with kernel core, uses
In the data for receiving kernel core and sending, the data received are sent under control unit (223) control the multiple defeated
Unit (222) out.Setting multiple groups register is as the output unit inside the parallel first in, first out unit pfifo (20)
(222), for buffering the data of input；Every group of register is internally provided with the waiting time.Waiting time record Current buffer is posted
Data in storage are in the waiting time of the parallel first in, first out unit pfifo, for guaranteeing that the data arrived first are arrived to rear
Data have high priority to be handled.
Control unit (223) is used to control and receive the work of unit (221) and multiple output units (222), such as data
Storage location, storage or reading order, the storage logic either ordered occur mistake and carry out the operation such as correcting.
5 it is found that bus pipeline BP (30) includes a selecting unit (331), convergence unit (332) and 8 with reference to the accompanying drawings
(pipen/nodex, 3330 ... 3337) form a pipeline node PN.Interior nucleus number in the number N and chip of pipeline node PN
It measures identical, that is to say, that there are N kernels in chip, there is N number of pipeline node PN, and N is the integer more than or equal to 2.Pipeline
N in node pipen is pipe number, and the x in nodex is node serial number, and each kernel corresponds to multiple pipe numbers, each
It is also corresponding that kernel, which corresponds to only one node serial number, pipe number and node serial number with destination address and source address,.Example
Such as in Fig. 2 and Fig. 5,0 to 7 is set by the pipe number n of kernel (103), node serial number x is set as 3, that is to say, that interior
The data/address bus BS (403) that core (103) sends data passes through from pipeline node pipe3/node3, connects the pipeline of other kernels
Node pipe3/nodex.Kernel (103) receive other kernels send data data/address bus BS400,401,402,404,
405,406,407 be connected to pipeline node pipe0/node3, pipe1/node3, pipe2/node3, pipe4/node3,
pipe5/node3,pipe6/node3,pipe7/node3；Pipeline node pipe0/node3, pipe1/node3, pipe2/
Node3, pipe4/node3, pipe5/node3, pipe6/node3, pipe7/node3 according to data destination address extract or
Person forwards the data transmitted in data bus B S400,401,402,404,405,406,407.That is, pipeline node
Pipe number n in pipen/nodex is the pipeline that multiple kernel core carry out that data send the data/address bus BS connection used
The corresponding number of node；Wherein n≤N, N are kernel number, and N is the integer more than or equal to 2；One kernel has 1 transmission number
According to data/address bus, with N-1 item receive data data/address bus.Node serial number x in pipeline node pipen/nodex and every
A kernel uniquely corresponds to, that is, corresponding with kernel address.
Multiple output units (222) phase of the selecting unit (331) and the parallel first in, first out unit pfifo (20)
It connects, obtains data from the multiple output unit (222), selection will send the pipeline node PN of the data, data are sent out
The pipeline node PN (pipen/nodex) selected is given, the pipeline node PN that kernel (103) selects in attached drawing 2 is pipe3/
node3。
Pipeline node PN (3330 ... 3337) is used to receive the data of the selecting unit (331) transmission, according to data
Destination address be sent to the pipeline node PN of purpose kernel by sending the data/address bus BS (40) of data.Pipeline node simultaneously
PN also passes through the data that data/address bus BS (40) receive adjacent channel node PN, since bus pipeline BP (30) and kernel are one by one
Corresponding relationship, therefore pipeline node PN judges whether it is the number that the pipeline node PN corresponds to kernel by data destination address
According to；If so, the data are extracted, it is sent to convergence unit (332)；If it is not, then will be led to according to destination address
It crosses data/address bus BS (40) and forwards the data to adjacent pipeline node PN.Unit (332) are converged by pipeline node PN
(3330 ... 3337) data forwarding sent is to kernel.
Data/address bus BS (40) includes 8 data bus B S (400 ... 407) in Fig. 5, and 1 hair is arranged in each kernel
The data/address bus BS of data is sent, for sending data to other kernels；Each kernel is by pipeline node PN connection 7 in other
Core sends the data/address bus BS of data, the data sent for receiving other kernels to the kernel.In order to reduce between bus
Influence each other, data/address bus BS (40) can be arranged to " bend " font cabling form.
By taking Fig. 2 as an example, chip core is arranged in two sides symmetrical above and below, and perhaps bilateral symmetry two sides upside or left side have
Kernel core (100) arrives (103), and downside or right side have kernel core (104) to (107), and the position of kernel is put with chip
Position it is related, the orientation kernel core is not specifically limited here, only does exemplary illustration here.Now with kernel
(103) for, " bow " font cabling form is the data/address bus BS (403) of kernel (103) from the pipeline node PN of kernel (103)
(pipe3/node3) set out, first connects the pipeline node PN (pipe3/node4) of kernel (104), then from kernel (104)
Pipeline node PN (pipe3/node4) is routed to the pipeline node PN (pipe3/node5) of kernel (105), then from kernel (105)
Pipeline node PN (pipe3/node5) be routed to the pipeline node PN (pipe3/node2) of kernel (102), then from kernel
(102) pipeline node PN (pipe3/node2) is routed to the pipeline node PN (pipe3/node1) of kernel (101), then from interior
The pipeline node PN (pipe3/node1) of core (101) is routed to the pipeline node PN (pipe3/node6) of kernel (106), then
The pipeline node PN (pipe3/node7) of kernel (107) is routed to from the pipeline node PN (pipe3/node6) of kernel (106),
The pipeline node PN (pipe3/ of kernel (100) is routed to from the pipeline node PN (pipe3/node7) of kernel (107) again
node0).This spline kernel (103) can send data to other kernels by data/address bus BS (403), other kernels can lead to
It crosses data/address bus BS (403) and receives the data that kernel (103) are sent.
Data/address bus BS (402) wire structures of the transmission data of kernel (102) are illustrated by taking Fig. 3 as an example, are being shown
Data/address bus BS (402) is dotted line in intention, and Fig. 3 illustrates the transmission number of the first and second kernel of multi core chip of first embodiment
According to data/address bus wire structures schematic diagram.Kernel (102) " bow " font cabling form is the data/address bus BS of kernel (102)
(402) from the pipeline node PN of kernel (102), (the pipe2/node2) carries out cabling to two sides respectively.One end first connects
The pipeline node PN (pipe2/node5) of kernel (105), then pipeline node PN (pipe2/node5) cloth from kernel (105)
Line the pipeline node PN (pipe2/node4) to kernel (104), then the pipeline node PN (pipe2/ from kernel (103)
Node4) it is routed to the pipeline node PN (pipe2/node3) of kernel (103).Other end cabling is first to be routed to kernel (101)
Pipeline node PN (pipe2/node1), then be routed to kernel from the pipeline node PN (pipe2/node1) of kernel (101)
(106) pipeline node PN (pipe2/node6), then in being routed to from the pipeline node PN (pipe2/node6) of kernel (106)
The pipeline node PN (pipe2/node7) of core (107), then be routed from the pipeline node PN (pipe2/node7) of kernel (107)
To the pipeline node PN (pipe2/node0) of kernel (100).Data/address bus BS (402) in this way passes through pipeline node PN
(pipe2/nodex) all kernels are electrically connected.Kernel (102) by send data data/address bus BS (402) to its
He sends data by kernel (100,101,103,104,105,106,107), passes through the data/address bus of the transmission data of other kernels
It receives data, such as receives kernel (103) transmission by the data/address bus BS (403) of the transmission data of kernel (103)
Data.
[embodiment 2]
Fig. 4 a illustrates the data of the transmission data of the first kernel of multi core chip of second embodiment according to the present utility model
The schematic diagram of route bus structure.By taking Fig. 4 a as an example, chip core is arranged in two sides symmetrical above and below or bilateral symmetry two sides,
Perhaps left side has kernel core (100) to have kernel core (104) to kernel to kernel (103) downside or right side for upside
(107), the position that the position of kernel is put with chip is related, is not specifically limited to the orientation kernel core here, is here
Do exemplary restriction.And for having chosen 8 kernels in attached drawing 4a, for only exemplary here, certain number of cores
It may be greater than the arbitrary integer equal to 2.Now by taking kernel (104) as an example, " П " font cabling form is the number of kernel (103)
According to bus B S (403), from the pipeline node PN of kernel (103), (the pipe3/node3) first connects the pipe of kernel (102)
Road node PN (pipe3/node2), then kernel (101) are routed to from the pipeline node PN (pipe3/node2) of kernel (102)
Pipeline node PN (pipe3/node1), then be routed to kernel from the pipeline node PN (pipe3/node1) of kernel (101)
(100) pipeline node PN (pipe3/node0), then in being routed to from the pipeline node PN (pipe3/node0) of kernel (100)
The pipeline node PN (pipe3/node7) of core (107), then be routed from the pipeline node PN (pipe3/node7) of kernel (107)
To the pipeline node PN (pipe3/node6) of kernel (106), then from pipeline node PN (pipe3/node6) cloth of kernel (106)
Line the pipeline node PN (pipe3/node5) to kernel (105), then the pipeline node PN (pipe3/node5) from kernel (105)
It is routed to the pipeline node PN (pipe3/node4) of kernel (104).Data/address bus BS (403) in this way passes through pipeline node PN
(pipe3/nodex) all kernels are electrically connected.Kernel (103) by send data data/address bus BS (403) to its
He sends data by kernel (100,101,102,104,105,106,107), passes through the data/address bus of the transmission data of other kernels
To receive data.
Fig. 4 b be by taking kernel (102) as an example to send data data/address bus BS (402) " П " font Wiring structure into
Row explanation, data/address bus BS (402) is dotted line in the diagram.Data/address bus BS (402) wire laying mode and kernel of kernel 2
(103) wire laying mode of the data/address bus BS (403) under " П " font cabling form is similar, herein with regard to not said in detail
It is bright." bow " font cabling form and " П " font cabling form not generating intersection between data/address bus BS (40), reduce
The item number of bus does not influence each other between bus.
[embodiment 3]
Fig. 6 illustrates data structure schematic diagram according to the present utility model.Data mentioned here are order data, numerical value number
According to a variety of data such as, character datas.Data format specifically includes significance bit valid, destination address dst id, source address src id
With data data.Kernel can judge that the data packet is order or numerical value, can be assumed 0 here by significance bit valid
Numerical value is represented, 1 represents order.From instruction operation timing, six traditional stage pipeline structures are used in the present embodiment, point
It Wei not fetching, decoding, execution, memory access, alignment and Write-back stage.From instruction set architecture, reduced instruction set computer frame can be taken
Structure.According to the general design method of reduced instruction set computer framework, the utility model instruction set can be divided into register-deposit by function
Type instruction, register-immediate instruction, jump instruction, access instruction, control instruction and intercore communication instruction.
Fig. 7 illustrates the transmission data of the first kernel according to the present utility model and receives the schematic diagram of data.Below with reference to
Attached drawing 5 and Fig. 7 illustrate how the present embodiment kernel sends and receives data or order by taking kernel (703) as an example.Kernel (703)
According to calculating task, the data of kernel to be sent to (707) are calculated, data are produced number as described in Figure 6 by kernel (703)
It according to packet, due to being data, then sets significance bit valid to " 0 ", produces destination address dst id and source address src id.It will
Data packet is sent to the receiving unit of the parallel first in, first out unit pfifo (713), and receiving unit (221) is in control unit
(223) data packet is stored according to reception sequence under control.Control unit (223) controls and receives unit (221) and will connect
The data packet received is sent to the multiple output unit (222).Each the multiple output unit (222) is internally provided with
Waiting time, waiting time record number of the data in the waiting time of pfifo, for guaranteeing to arrive first in Current buffer register
According to it is rear to data there is high priority to be handled.Control unit (223) control the multiple output unit (222) according to when
Between sequentially deliver a packet to selecting unit (331).Selecting unit (331) is numbered according to corresponding kernel or source address
It determines pipe number n, that is, determines the pipeline node PN of selection, since kernel (703) and bus pipeline BS (723) are an a pair
It answers, therefore the node serial number of the corresponding pipeline node of the kernel is also determining；Deliver a packet to the pipe section of selection
Point PN (pipe3/node3).Pipeline node PN (pipe3/node3) determines purpose kernel according to the destination address of data packet
Corresponding node serial number is by taking kernel (707) as an example here, and pipeline node PN (pipe3/node3) is by data packet in " bow " word
The data/address bus of type cabling or " П " font cabling is sent to pipeline node PN (pipe3/node7).Pipeline node PN
(pipe3/node7) data packet is received, judges whether the data packet is this node data according to the destination address in data packet
Packet if it is delivers a packet to convergence unit 332；If it is not, then unidirectionally forwarding downwards or upwards.Converge unit
The data packet received is sent to kernel (707) by 332.
To each bus pipeline BP (30), input data had the parallel first in, first out unit pfifo (20) of local terminal,
With the upper level or next stage data for carrying out adjacent chips.On priority arbitration, the preferential mode for using bandwidth allocation makes multicore
Concurrent data substantially have identical chance or bandwidth, send data to some purpose kernel.Specifically, in pipeline node
The register that one bandwidth of setting is measured inside PN, for controlling corresponding bus utilization power.Can be set local terminal and
The bus occupied bandwidth (bus bandwidth is slowly or in the case where generation data collision) of row first in, first out unit pfifo is without departing from one
Fixed ratio, so that the data packet of other kernels is not to fall into a long wait.Pipeline node PN can pass through priority or meter
When etc. modes realize bandwidth control, here can pass through assign the first priority one life cycle of request；To the life
Order period progress countdown；At the end of the life cycle, the priority of the request is reduced to as the second priority；
Wherein, the life cycle is passed with request.It, can be more accurate by the bus arbitration method using the utility model
Ground control request by the response time, guarantee that request is responded before the deadline.In the present embodiment, to each pipeline
For node PN, equal bandwidth or sending time are distributed for the corresponding pfifo of each core nodes.Above-mentioned bandwidth
Method is only applied to pipeline node PN while having the case where efficient data access, accesses simultaneously when there is no data, then effectively
The problem of data can be handled in time, and there is no arbitrations.
Using description provided herein, embodiment can be realized by using the programming and/or engineering technology of standard
At machine, process or manufacture to generate programming software, firmware, hardware or any combination thereof.
The program (multiple) (having computer readable program code) of any generation can be embodied in one or more
On medium workable for computer, such as resident storage equipment, smart card or other movable memory equipments or transmission equipment,
To make computer program product and manufacture according to embodiment.As such, as used in this article term " manufacture " and
" computer program product " is intended to cover permanently or temporarily non-transitory in the presence of can be used in any computer
Medium on computer program.
As noted above, memory/storage is (all including but not limited to disk, CD, movable memory equipment
Such as smart card, subscriber identity module (SIM), wireless identity module (WIM)), semiconductor memory (such as random access memory
(RAM), read-only memory (ROM), programmable read only memory (PROM)) etc..Transmission medium is including but not limited to via wireless
Communication network, internet, intranet, the network communication based on telephone/modem, hard-wired/cabled communication network, satellite
Communication and other fixations or the transmission of mobile network system/communication link.
Although specific example embodiment has been disclosed, it will be appreciated by those skilled in the art that not carrying on the back
In the case where spirit and scope from the utility model, specific example embodiments can be changed.
Above with reference to attached drawing, the utility model is illustrated based on embodiment, but the utility model be not limited to it is above-mentioned
Embodiment, according to layout need etc. by the part of each embodiment and each variation constitute it is appropriately combined or displacement after side
Case is also contained in the scope of the utility model.Furthermore it is also possible to which the knowledge based on those skilled in the art suitably recombinates each reality
The combination and processing sequence of mode are applied, or the deformation such as various design alterations is applied to each embodiment, has been applied such
The embodiment of deformation may also be included in the scope of the utility model.
Although each conception of species has already been described in detail in the utility model, it will be appreciated by a person skilled in the art that for those
What the various modifications and substitution of concept can be achieved under the spirit disclosed by the utility model integrally instructed.Art technology
Personnel can realize that sheet illustrated in detail in the claims is practical in the case where being not necessarily to undue experimentation with ordinary skill
It is novel.It is understood that disclosed specific concept is merely illustrative, it is not intended to limit the model of the utility model
It encloses, the scope of the utility model is determined by the full scope of the appended claims and its equivalent program.
Claims (11)
1. a kind of multi core chip data/address bus wire structures, the number of cores of the multi core chip is N, and wherein N is more than or equal to 2
Positive integer, it is characterised in that: each kernel in N number of kernel arranges the data/address bus of a transmission data, data described in N item
Each in bus is served only for a kernel in N number of kernel and sends data to other kernels.
2. wire structures according to claim 1, which is characterized in that N number of tie point is set on every data/address bus,
Each of N number of kernel kernel connects the data/address bus by a tie point.
3. wire structures according to claim 2, which is characterized in that only one kernel is logical on every data/address bus
It crosses tie point and sends data, other kernels receive the data transmitted on the data/address bus by tie point.
4. wire structures according to claim 3, which is characterized in that each kernel passes through the institute that is arranged for the kernel
The data/address bus for sending data is stated to other kernels transmission data, is received from data/address bus described in remaining N-1 item from other kernels
Data.
5. according to the described in any item wire structures of claim 2 to 4, which is characterized in that the tie point includes N number of pipe section
Point PN, wherein one in N number of pipeline node PN is connected with the data/address bus for sending data；Remaining N-1 pipeline node
The data/address bus that PN sends data with other kernels respectively is connected.
6. wire structures according to claim 5, which is characterized in that the pipeline of the connection data/address bus for sending data
Node PN passes through the transmission data for obtaining the kernel data to be sent, according to the data destination address to be sent
Data/address bus is sent to the pipeline node PN of purpose kernel.
7. wire structures according to claim 5, which is characterized in that the remaining N-1 pipeline node PN is used for basis
The data destination address transmitted in the data/address bus of other kernels transmission data is forwarded to data or obtains operation；
The data that destination address is this kernel address are obtained and are sent in described by N-1 pipeline node PN of the residue
Core.
8. wire structures according to claim 5, which is characterized in that kernel selects data to be sent by selecting unit
Pipeline node PN.
9. wire structures according to any one of claims 1 to 4, which is characterized in that every data/address bus wire bond
Structure is " bow " font cabling form, and N data bus does not have crosspoint.
10. wire structures according to any one of claims 1 to 4, which is characterized in that the data/address bus wire structures are
" П " font cabling form, N data bus do not have crosspoint.
11. a kind of multi core chip data/address bus wire structures, the number of cores of the multi core chip is N, wherein N be more than or equal to
2 positive integer, it is characterised in that: each kernel in N number of kernel arranges the data/address bus of a transmission data；The multi-core
Each kernel of piece can only give other kernels to send data on its corresponding data/address bus for sending data, and from it is remaining its
The data/address bus that data are sent described in his N-1 item receives data from other kernels；In the corresponding number for sending data of the kernel
According to the data for not transmitting the transmission of other kernels in bus.
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN111258732A (en) * | 2020-01-13 | 2020-06-09 | 中科寒武纪科技股份有限公司 | Data processing method, data processing device and electronic equipment |
| CN116361223A (en) * | 2023-06-02 | 2023-06-30 | 深圳市航顺芯片技术研发有限公司 | Multi-core communication method, device, micro-control chip and storage medium |
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111258732A (en) * | 2020-01-13 | 2020-06-09 | 中科寒武纪科技股份有限公司 | Data processing method, data processing device and electronic equipment |
| CN111258732B (en) * | 2020-01-13 | 2023-07-04 | 中科寒武纪科技股份有限公司 | Data processing method, data processing device and electronic equipment |
| CN116361223A (en) * | 2023-06-02 | 2023-06-30 | 深圳市航顺芯片技术研发有限公司 | Multi-core communication method, device, micro-control chip and storage medium |
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