CN209132659U - A kind of clock signal generating apparatus - Google Patents
A kind of clock signal generating apparatus Download PDFInfo
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- CN209132659U CN209132659U CN201920172507.3U CN201920172507U CN209132659U CN 209132659 U CN209132659 U CN 209132659U CN 201920172507 U CN201920172507 U CN 201920172507U CN 209132659 U CN209132659 U CN 209132659U
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- clock signal
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Abstract
A kind of clock signal generating apparatus, signal frequency to be output is obtained by keyboard input module, and FPGA field programmable gate array generates frequency control code according to signal frequency；DDS frequency synthesizer is sent by frequency control code by FPGA field programmable gate array, is loaded in such a way that frequency control register is by serial or parallel and deposits frequency control code；Phase-accumulated generation phase value is carried out within each clock cycle to frequency control code by phase accumulator；Sinusoidal amplitude is calculated to phase value by sinusoidal calculations device and generates digitized sine wave clock signal.Digitized sine-wave clock signal is converted into analog signal by D/A converter, and low-pass filtering is carried out to analog signal by low-pass filter, the analog signal after low-pass filtering is exported by SMA interface.Support the clock signal of 35MHz~4GHz range arbitrary point frequency exports to generate, using flexible, suitable for the test under field extreme environment, measurement or calibration etc..
Description
Technical field
The utility model embodiment is related to clock signal processing technology field, and in particular to a kind of clock signal fills
It sets.
Background technique
Clock signal is the basis of sequential logic, when is updated for the state in decision logic unit, is to have fixed week
Phase and the semaphore unrelated with operation.Clock signal has fixed clock frequency, and clock frequency is the inverse of clock cycle.In electricity
The synchronous digital circuit of son and especially signal, clock signal are the high and low shapes between a kind of distinctive signal oscillation of signal
State, the digital circuit that the utilization of signal is coordinated actions as a metronome, dagital clock signal is substantially square-wave voltage, only
Two level, first is that low level, the other is high level.High level can be different according to the requirement of circuit, such as TTL standard
High level be 5V.
Common clock signal is in the duty ratio with 50%, that is to say, that high level and low level duration be
The same, the form of usually one fixed constant frequency square wave.Circuit may become living using synchronizing for clock signal
It jumps in any rising edge, failing edge, or in double data rate, it the clock cycle at raising and lowering edge, can be according to number
Circuit is using needing to provide any clock frequency.Currently, that there are volumes is larger, carries for most of signal source of clock in the market
The problem of inconvenient, aspect such as need external power supply, cost higher, it has not been convenient to which user surveys under field extreme environment
Examination, measurement or calibration.
Utility model content
For this purpose, the utility model embodiment provides a kind of clock signal generating apparatus and method, 35MHz~4GHz model is supported
The output for enclosing the sine-wave clock signal of interior arbitrary point frequency generates, small in size, easy to carry, using flexible, is suitable for field and dislikes
Test under bad environment, measurement or calibration etc..
To achieve the goals above, the embodiments of the present invention provides the following technical solutions: a kind of clock signal hair
Generating apparatus, the FPGA field programmable gate array including being equipped with Nios embeded processor, the FPGA field-programmable gate array
Column are integrated with Cyclone chip, and the FPGA field programmable gate array is connected with keyboard input module and DDS frequency synthesis
Device, the keyboard input module are used for the FPGA field programmable gate array frequency input signal and make the scene FPGA
Programmable gate array generates frequency control code；
The DDS frequency synthesizer includes frequency control register, phase accumulator and sinusoidal calculations device；The frequency control
Register processed by way of serial or parallel for being loaded and depositing the frequency control code；The phase accumulator for pair
The frequency control code carries out phase-accumulated generation phase value within each clock cycle；The sinusoidal calculations device be used for by pair
The phase value calculates sinusoidal amplitude and generates digitized sine wave clock signal.
It further include battery module as the preferred embodiment of clock signal generating apparatus, the battery module and the FPGA
Field programmable gate array connection, battery module is for being powered clock signal generating apparatus.
As the preferred embodiment of clock signal generating apparatus, the battery module is connected with power management module, the electricity
Source control module is connect with the FPGA field programmable gate array, and power management module is used for the information about power to battery module
It is managed；The power management module is connected with USB charging interface.
It further include display module as the preferred embodiment of clock signal generating apparatus, the display module and the FPGA
Field programmable gate array is connected by spi bus interface, display module be used for the information about power of clock signal generating apparatus,
Parameter setting status information is shown.
As the preferred embodiment of clock signal generating apparatus, the DDS frequency synthesizer is connected with D/A converter, described
D/A converter is connected with low-pass filter, and the D/A converter is used to digitized sine-wave clock signal being converted to simulation
Signal；The low-pass filter is used to carry out low-pass filtering to analog signal.
As the preferred embodiment of clock signal generating apparatus, the low-pass filter is at least connected with a SMA interface, described
SMA interface is for exporting the analog signal after low-pass filtering.
The utility model embodiment also provides a kind of clock signal generating method, is filled using above-mentioned clock signal
Set, clock signal generating method the following steps are included:
Signal frequency to be output is obtained by keyboard input module, FPGA field programmable gate array is according to the signal
Frequency generates frequency control code；
DDS frequency synthesizer is sent by the frequency control code by FPGA field programmable gate array, using frequency
Control register is loaded by way of serial or parallel and deposits the frequency control code；
Phase-accumulated generation phase value is carried out within each clock cycle to the frequency control code by phase accumulator；
Sinusoidal amplitude is calculated to the phase value by sinusoidal calculations device and generates digitized sine wave clock signal.
It is further comprising the steps of as the preferred embodiment of clock signal generating method, it will be digitized by D/A converter
Sine-wave clock signal is converted to analog signal, and carries out low-pass filtering to the analog signal by low-pass filter, will be low
Analog signal after pass filter is exported by SMA interface.
It is further comprising the steps of as the preferred embodiment of clock signal generating method, by battery module to the scene FPGA
Programmable gate array, DDS frequency synthesizer, D/A converter and low-pass filter are powered, and call power management module to electricity
The information about power of pond module is managed, and the power management module is connected with USB charging interface.
As the preferred embodiment of clock signal generating method, call display module to the information about power of the battery module,
FPGA field programmable gate array parameter setting status information is shown that FPGA field programmable gate array passes through spi bus
Interface carries out data transmission with the display module.
The embodiments of the present invention has the advantages that clock signal generating module Miniaturization Design, completes 35MHz
The output of~4GHz sinusoidal signal；It is designed using low energy-consumption electronic device, guarantees the battery module powered operation time；It is integrated with battery
Module, power management module, charging circuit design etc.；Integrated display screen design, completion status is shown, electricity is shown, parameter is set
Status information is set to show；The design of input key, Mating parameters setting are completed in limited dimensional structure.Support 35MHz
The output of the sine wave signal of arbitrary point frequency generates within the scope of~4GHz, corresponding equipment have it is small in size, easy to carry, use spirit
The advantages such as living, suitable for the test under field extreme environment, measurement or calibration etc..
Detailed description of the invention
It, below will be to reality in order to illustrate more clearly of the embodiments of the present invention or technical solution in the prior art
It applies mode or attached drawing needed to be used in the description of the prior art is briefly described.It should be evident that attached in being described below
Figure is only exemplary, for those of ordinary skill in the art, without creative efforts, can be with
It is extended according to the attached drawing of offer and obtains other implementation attached drawings.
Fig. 1 is a kind of clock signal generating apparatus structural schematic diagram provided in the utility model embodiment；
Fig. 2 is a kind of clock signal generating method flow diagram provided in the utility model embodiment；
In figure: 1, Nios embeded processor；2, FPGA field programmable gate array；3, keyboard input module；4, DDS frequency
Rate synthesizer；5, frequency control register；6, phase accumulator；7, sinusoidal calculations device；8, battery module；9, power management mould
Block；10, display module；11, D/A converter；12, low-pass filter；13, SMA interface；14, USB charging interface.
Specific embodiment
The embodiments of the present invention is illustrated by particular specific embodiment below, those skilled in the art can be by this
Content disclosed by specification understands other advantages and effect of the utility model easily, it is clear that described embodiment is
The utility model a part of the embodiment, instead of all the embodiments.Based on the embodiments of the present invention, this field is common
Technical staff's every other embodiment obtained without making creative work belongs to the utility model protection
Range.
The concrete meaning of english abbreviation involved in the utility model embodiment is as follows:
Nios: Altera Corp aims at the soft-core processor of the Series FPGA exploitation of altera；
Cyclone: Altera Corp's FPGA hurricane series；
FPGA:Field-Programmable Gate Array, i.e. field programmable gate array；
DDS:Direct Digital Synthesizer, digital frequency synthesizer；
USB:Universal Serial Bus, universal serial bus；
SMA:Sub-Miniature-A, radio antenna interface；
SPI:Serial Peripheral Interface, Serial Peripheral Interface (SPI)；
D/A:Digital/Analog, digital-to-analog.
Referring to Fig. 1, the utility model embodiment provides a kind of clock signal generating apparatus, including is equipped with the embedded place Nios
The FPGA field programmable gate array 2 of device 1 is managed, the FPGA field programmable gate array 2 is integrated with Cyclone chip, described
FPGA field programmable gate array 2 is connected with keyboard input module 3 and DDS frequency synthesizer 4, and the keyboard input module 3 is used
In to 2 frequency input signal of FPGA field programmable gate array and the FPGA field programmable gate array 2 being made to generate frequency
Rate control code.Specifically, Nios embeded processor 1 is a commercial processor specifically for FPGA, in the prior art,
Altera provides Nios and Nios II processor, and the key information of keyboard input module 3 can be obtained by Nios kernel, controls
Parameter setting and information processed are shown.
The DDS frequency synthesizer 4 includes frequency control register 5, phase accumulator 6 and sinusoidal calculations device 7；The frequency
Rate control register 5 by way of serial or parallel for being loaded and depositing the frequency control code；The phase accumulator 6
For carrying out phase-accumulated generation phase value within each clock cycle to the frequency control code；The sinusoidal calculations device 7 is used
In by calculating sinusoidal amplitude generation digitized sine wave clock signal to the phase value.
DDS frequency resolution is high, output frequency point is more, up to 2 Nth power frequency point, (N is phase-accumulated digit；Frequency is cut
Throw-over degree is fast, and DDS is an open cycle system, and without any feedback element, thus frequency switching time is extremely short, up to ns magnitude；Frequently
Phase Continuation when rate switches；Wideband orthogonal signal can be exported；Output phase noise is low, the phase separation to reference frequency source；It can
To generate random waveform；Total digitalization is realized, convenient for integrated, small in size, light-weight.DDS is realize equipment total digitalization one
A key technology.It mainly include frequency control register 5, high-speed phase accumulator 6 and sinusoidal calculations in DDS frequency synthesizer 4
7 three parts of device.Frequency control register 5 can load in serial or parallel fashion and deposit the frequency control of user's input
Code；And phase accumulator 6 carries out within each clock cycle phase-accumulated according to frequency control code, obtains a phase value；Just
String calculator 7 then calculates digitized sinusoidal wave amplitude to the phase value (chip, which generally passes through, to be tabled look-up to obtain).
Further include battery module 8 in one embodiment of clock signal generating apparatus, the battery module 8 with it is described
FPGA field programmable gate array 2 connects, and battery module 8 is for being powered clock signal generating apparatus.The battery mould
Block 8 is connected with power management module 9, and the power management module 9 is connect with the FPGA field programmable gate array 2, power supply
Management module 9 is for being managed the information about power of battery module 8；The power management module 9 is connected with USB charging interface
14。
Specifically, consider the structure size of clock signal generating apparatus, 8 volume requirement of battery module of corresponding power supply
Small, when using lithium battery and system circuit design, FPGA field programmable gate array 2 selects the Cyclone core of Altra company
Piece, the chip power-consumption is lower, can satisfy requirement of system design.
Specifically, power management module 9 can use Corrado CES-5103, be able to carry out battery module 8 charging and from
Dynamic switching, main-board on-off, electric power detection are equipped with battery pack interface, power adaptor interface, mainboard control interface, and button connects
Mouthful, USB interface, input voltage: 9~25V, output voltage: 12V/5A and 5V/3A (independent dual output), support 2 string n simultaneously, 3 string n
And 4 string n simultaneously (n >=1), support lithium ion battery/poly-lithium battery of 4.1V, 4.2V, 4.3V and the phosphoric acid of 3.65V
Charging current: lithium iron battery supports 0.5A~2.85A, standby current: < 10uA.
Specifically, FPGA field programmable gate array 2 is a kind of driven by program logical device, similar microprocessor is acted on,
It controls program and is stored in memory, and after power-up, program is loaded into chip execution automatically.FPGA field programmable gate array 2 one
As by two programmable modules and storage SRAM constitute.CLB is programmable logic block, is the core group of field programmable gate array
It is the basic unit for realizing logic function, mainly by numbers such as logical function generator, trigger, data selectors at part
Logic circuit is constituted.SRAM (static memory) has many advantages, such as high reliablity, strong antijamming capability, good confidentiality, is dispatching from the factory
When all by producer carry out security reliability test, guarantee also can guarantee safety in the most adverse case, be unlikely to occur soft
Mistake has height reliability based on the system that FPGA field programmable gate array 2 designs.
Further include display module 10 in one embodiment of clock signal generating apparatus, the display module 10 with it is described
FPGA field programmable gate array 2 is connected by spi bus interface, and display module 10 is used for the electricity to clock signal generating apparatus
Amount information, parameter setting status information are shown.Using displayization Integrated design, integrated LED design of LED, completion status
Display, electricity is shown, parameter setting status information is shown.
In one embodiment of clock signal generating apparatus, the DDS frequency synthesizer 4 is connected with D/A converter 11, institute
It states D/A converter 11 and is connected with low-pass filter 12, the D/A converter 11 is used to turn digitized sine-wave clock signal
It is changed to analog signal；The low-pass filter 12 is used to carry out low-pass filtering to analog signal.The low-pass filter 12 is at least
A SMA interface 13 is connected, the SMA interface 13 is for exporting the analog signal after low-pass filtering.D/A converter 11 includes number
Code memory, analog electronic switching circuit, decoding network, summing circuit and reference voltage.Digital quantity is in a manner of serial or parallel
It inputs and is stored in digital register, the bits per inch code of digital register output drives the electronic switch in corresponding numerical digit will be
The respective digital weight obtained in resistance decoding network is sent into summing circuit.Summing circuit just obtains the addition of each weight and number
Measure corresponding analog quantity.D/A conversion digital quantity D is converted into analog quantity V proportional therewith, it may be assumed that V=R × D, wherein R be than
Example coefficient.
Referring to Fig. 1 and Fig. 2, the utility model embodiment also provides a kind of clock signal generating method, using it is above-mentioned when
Clock signal generation apparatus, clock signal generating method the following steps are included:
S1: signal frequency to be output is obtained by keyboard input module 3, FPGA field programmable gate array 2 is according to institute
It states signal frequency and generates frequency control code；
S2: sending DDS frequency synthesizer 4 for the frequency control code by FPGA field programmable gate array 2, uses
Frequency control register 5 is loaded by way of serial or parallel and deposits the frequency control code；
S3: phase-accumulated generation phase is carried out to the frequency control code within each clock cycle by phase accumulator 6
Place value；
S4: sinusoidal amplitude is calculated to the phase value by sinusoidal calculations device 7 and generates digitized sine wave clock signal.
It further include step S5 in one embodiment of clock signal generating method: will be digitized by D/A converter 11
Sine-wave clock signal is converted to analog signal, and carries out low-pass filtering to the analog signal by low-pass filter 12, will
Analog signal after low-pass filtering is exported by SMA interface 13.
In one embodiment of clock signal generating method, by battery module 8 to FPGA field programmable gate array 2,
DDS frequency synthesizer 4, D/A converter 11 and low-pass filter 12 are powered, and call power management module 9 to battery module 8
Information about power be managed, the power management module 9 is connected with USB charging interface 14.Call display module 10 to described
The information about power of battery module 8,2 parameter setting status information of FPGA field programmable gate array are shown that the scene FPGA can
Programming gate array 2 is carried out data transmission by spi bus interface with the display module 10.
The embodiments of the present invention controls the letter of DDS frequency synthesizer 4 by FPGA field programmable gate array 2
Number output, pass through power management module 9 obtain battery module 8 information about power；Pass through spi bus Interface Controller display module 10
Liquid crystal display the display of status information is exported；By Nios kernel, key information is obtained, control parameter setting and information are aobvious
Show.Clock signal output is to control what DDS frequency synthesizer 4 was completed by FPGA field programmable gate array 2, wherein DDS frequency
Synthesizer 4 can generate the sinusoidal clock signal of 35MHz~4GHz by control, and signal frequency is given by keyboard input module 3
FPGA field programmable gate array 2, FPGA field programmable gate array 2 generates corresponding control frequency code, by respective frequencies code
It is sent to the chip of DDS frequency synthesizer 4,4 chip of DDS frequency synthesizer completes the generation of corresponding frequencies signal.Clock signal
Generation module Miniaturization Design completes the output of 35MHz~4GHz sinusoidal signal；It is designed using low energy-consumption electronic device, guarantees electricity
The 8 powered operation time of pond module；It is integrated with battery module 8, power management module 9, charging circuit design etc.；Integrated display screen is set
Meter, completion status is shown, electricity is shown, parameter setting status information is shown；Input is completed in limited dimensional structure to press
The design of key, Mating parameters setting.The output of the sine wave signal of arbitrary point frequency within the scope of 35MHz~4GHz is supported to generate, it is right
Answer equipment that there are the advantages such as small in size, easy to carry, using flexible, suitable for the test under field extreme environment, measurement or mark
School etc..
Although above having made detailed description to the utility model with generality explanation and specific embodiment,
On the basis of the utility model, it can be made some modifications or improvements, this is apparent to those skilled in the art
's.Therefore, these modifications or improvements on the basis of without departing from the spirit of the present invention, belong to the utility model and want
Seek the range of protection.
Claims (6)
1. a kind of clock signal generating apparatus, which is characterized in that the scene FPGA including being equipped with Nios embeded processor (1) can
It programs gate array (2), the FPGA field programmable gate array (2) is integrated with Cyclone chip, the FPGA field-programmable
Gate array (2) is connected with keyboard input module (3) and DDS frequency synthesizer (4), and the keyboard input module (3) is used for institute
It states FPGA field programmable gate array (2) frequency input signal and the FPGA field programmable gate array (2) is made to generate frequency
Control code；
The DDS frequency synthesizer (4) includes frequency control register (5), phase accumulator (6) and sinusoidal calculations device (7)；Institute
Frequency control register (5) are stated for loading by way of serial or parallel and depositing the frequency control code；The phase
Accumulator (6) within each clock cycle for carrying out phase-accumulated generation phase value to the frequency control code；The sine
Calculator (7) is used to generate digitized sine wave clock signal by calculating sinusoidal amplitude to the phase value.
2. a kind of clock signal generating apparatus according to claim 1, which is characterized in that further include battery module (8), institute
It states battery module (8) to connect with the FPGA field programmable gate array (2), battery module (8) is used to that clock signal to occur
Device is powered.
3. a kind of clock signal generating apparatus according to claim 2, which is characterized in that
The battery module (8) is connected with power management module (9), and the power management module (9) and the scene FPGA can
Gate array (2) connection is programmed, power management module (9) is for being managed the information about power of battery module (8)；
The power management module (9) is connected with USB charging interface (14).
4. a kind of clock signal generating apparatus according to claim 1, which is characterized in that it further include display module (10),
The display module (10) is connect with the FPGA field programmable gate array (2) by spi bus interface, display module (10)
It is shown for the information about power to clock signal generating apparatus, parameter setting status information.
5. a kind of clock signal generating apparatus according to claim 1, which is characterized in that the DDS frequency synthesizer (4)
It is connected with D/A converter (11), the D/A converter (11) is connected with low-pass filter (12), and the D/A converter (11) is used
In digitized sine-wave clock signal is converted to analog signal；The low-pass filter (12) is used to carry out analog signal
Low-pass filtering.
6. a kind of clock signal generating apparatus according to claim 5, which is characterized in that the low-pass filter (12) is extremely
A SMA interface (13) is connected less, and the SMA interface (13) is for exporting the analog signal after low-pass filtering.
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109542161A (en) * | 2019-01-30 | 2019-03-29 | 北京昊海雅正科技有限公司 | A kind of clock signal generating apparatus and method |
| CN111338424A (en) * | 2020-02-26 | 2020-06-26 | 济南浪潮高新科技投资发展有限公司 | Waveform synchronous output method and device |
-
2019
- 2019-01-30 CN CN201920172507.3U patent/CN209132659U/en active Active
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109542161A (en) * | 2019-01-30 | 2019-03-29 | 北京昊海雅正科技有限公司 | A kind of clock signal generating apparatus and method |
| CN111338424A (en) * | 2020-02-26 | 2020-06-26 | 济南浪潮高新科技投资发展有限公司 | Waveform synchronous output method and device |
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