CN111338424A - Waveform synchronous output method and device - Google Patents
Waveform synchronous output method and device Download PDFInfo
- Publication number
- CN111338424A CN111338424A CN202010119903.7A CN202010119903A CN111338424A CN 111338424 A CN111338424 A CN 111338424A CN 202010119903 A CN202010119903 A CN 202010119903A CN 111338424 A CN111338424 A CN 111338424A
- Authority
- CN
- China
- Prior art keywords
- phase
- dds
- output
- core
- offset
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Images
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
- G06F1/02—Digital function generators
- G06F1/03—Digital function generators working, at least partly, by table look-up
- G06F1/0321—Waveform generators, i.e. devices for generating periodical functions of time, e.g. direct digital synthesizers
- G06F1/0342—Waveform generators, i.e. devices for generating periodical functions of time, e.g. direct digital synthesizers for generating simultaneously two or more related waveforms, e.g. with different phase angles only
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
- G06F1/02—Digital function generators
- G06F1/03—Digital function generators working, at least partly, by table look-up
- G06F1/0321—Waveform generators, i.e. devices for generating periodical functions of time, e.g. direct digital synthesizers
- G06F1/0328—Waveform generators, i.e. devices for generating periodical functions of time, e.g. direct digital synthesizers in which the phase increment is adjustable, e.g. by using an adder-accumulator
- G06F1/0335—Waveform generators, i.e. devices for generating periodical functions of time, e.g. direct digital synthesizers in which the phase increment is adjustable, e.g. by using an adder-accumulator the phase increment itself being a composed function of two or more variables, e.g. frequency and phase
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
- G06F1/04—Generating or distributing clock signals or signals derived directly therefrom
- G06F1/12—Synchronisation of different clock signals provided by a plurality of clock generators
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)
Abstract
The invention provides a waveform synchronous output method and a device, wherein the method comprises the following steps: calculating a phase increment according to a phase accumulator and a target waveform data output frequency, wherein the phase accumulator is used for setting the position of waveform output; calculating a basic phase offset parameter according to the phase increment; calculating the initial phase of each DDS IP core according to the basic phase offset parameters, wherein a serializer serdes of 4:1 conversion is connected with a field programmable logic gate array (FPGA) and a digital-to-analog conversion (DA) chip, 4 direct digital synthesizer DDS IP cores are arranged in the FPGA, and the 4 DDS IP cores are connected with the DA chip through the serdes; and calculating the output phase of each DDS IP core according to each initial phase increment and the phase increment, and controlling each DDS IP core to output the output phase to the DA chip so that the DA chip enables the oscilloscope to output the target waveform data through the phase accumulator. The invention can synchronously output the waveform.
Description
Technical Field
The invention relates to the technical field of computers, in particular to a waveform synchronous output method and a waveform synchronous output device.
Background
With the development of science and technology, various chips are widely applied to various fields such as computers, cloud ends, internet of things, multimedia and the like, and with the increasing requirements of the fields on performance, the DA chip is widely used due to the high sampling rate of the DA chip.
At present, in order to meet the sampling rate of the DA chip of 1Ghz at most, because the FPGA adopts an internal data processing clock of 250mHz, 4 DDS IP cores need to be used, and parallel-serial conversion of data is realized through a parallel port Serdes of 4:1 conversion.
However, in this way, because the time for outputting valid data of each DDS IP core is different, the 4 DDS IP cores sometimes cannot work effectively at the same time, and thus the backend waveform output is not synchronous.
Disclosure of Invention
The embodiment of the invention provides a waveform synchronous output method and a device, which can synchronously output waveforms.
In a first aspect, an embodiment of the present invention provides a waveform synchronization output method, including:
calculating a phase increment according to a phase accumulator and a target waveform data output frequency, wherein the phase accumulator is used for setting the position of waveform output;
calculating a basic phase offset parameter according to the phase increment;
calculating the initial phase of each DDS IP core according to the basic phase offset parameters, wherein a serializer serdes of 4:1 conversion is connected with a field programmable logic gate array (FPGA) and a digital-to-analog conversion (DA) chip, 4 direct digital synthesizer DDS IP cores are arranged in the FPGA, and the 4 DDS IP cores are connected with the DA chip through the serdes;
and calculating the output phase of each DDS IP core according to each initial phase increment and the phase increment, and controlling each DDS IP core to output the output phase to the DA chip so that the DA chip enables the oscilloscope to output the target waveform data through the phase accumulator.
Preferably, the first and second electrodes are formed of a metal,
the calculating of the phase increment according to the phase accumulator and the target waveform data output frequency comprises: and calculating the phase increment according to the precision digit number of the phase accumulator and 4 times of the output frequency of the target waveform.
Preferably, the first and second electrodes are formed of a metal,
the calculating of the basic phase shift parameter according to the phase increment includes: dividing the phase increment by 4 to calculate the basic phase shift parameter.
Preferably, the first and second electrodes are formed of a metal,
the calculating the initial phase of each DDS IP core according to the basic phase offset parameter includes: respectively calculating the initial phase of each DDS IP core by the following first formula:
the first formula includes:
phase_offset_0＝phase_inc*0；
phase_offset_1＝phase_inc*1；
phase_offset_2＝phase_inc*2；
phase_offset_3＝phase_inc*3；
wherein the phase _ inc is used for representing the basic phase offset parameter, the phase _ offset _0 is used for representing an initial phase of a first DDS IP core of the four DDS IP cores, the phase _ offset _1 is used for representing an initial phase of a second DDS IP core, the phase _ offset _2 is used for representing an initial phase of a third DDS IP core, and the phase _ offset _3 is used for representing an initial phase of a fourth DDS IP core.
Preferably, the first and second electrodes are formed of a metal,
the calculating the output phase of each DDS IP core according to each initial phase increment and the phase increment comprises:
calculating the output phase according to the initial phase and the phase increment of each DDS IP core by a second formula;
phase_out＝phase_inc_int+phase_offset；
wherein phase _ out is used to characterize the output phase, phase _ inc _ int is used to characterize the phase increment, and phase _ offset is used to characterize the initial phase of the currently computed DDS IP core.
Preferably, the first and second electrodes are formed of a metal,
before the 4 DDS IP cores are connected to the DA chip through the serdes, the method further includes:
and each DDS IP core is connected with a first-in first-out FIFO module so that the FIFO module controls each DDS IP core to output the output phase at the same time.
In a second aspect, an embodiment of the present invention provides a waveform synchronization output apparatus, including:
a calculation unit and a control unit;
the calculating unit is used for calculating a phase increment according to a phase accumulator and a target waveform data output frequency, wherein the phase accumulator is used for setting the position of waveform output;
calculating a basic phase offset parameter according to the phase increment;
calculating the initial phase of each DDS IP core according to the basic phase offset parameters, wherein a serializer serdes of 4:1 conversion is connected with a field programmable logic gate array (FPGA) and a digital-to-analog conversion (DA) chip, 4 direct digital synthesizer DDS IP cores are arranged in the FPGA, and the 4 DDS IP cores are connected with the DA chip through the serdes;
and the control unit is used for calculating an output phase according to each initial phase increment and each phase increment and controlling each DDS IP core to output the output phase to the DA chip so that the DA chip enables the oscilloscope to output the target waveform data through the phase accumulator.
Preferably, the first and second electrodes are formed of a metal,
when the calculating unit calculates the phase increment according to the phase accumulator and the target waveform data output frequency, the calculating unit specifically executes: and calculating the phase increment according to the precision digit number of the phase accumulator and 4 times of the output frequency of the target waveform.
Preferably, the first and second electrodes are formed of a metal,
when the calculating unit executes the calculation of the basic phase offset parameter according to the phase increment, specifically executing: dividing the phase increment by 4 to calculate the basic phase offset parameter.
Preferably, the first and second electrodes are formed of a metal,
when the calculating unit executes the initial phase of each DDS IP core calculated according to the basic phase offset parameter, specifically execute: calculating the initial phase of each DDS IP core respectively according to the following first formula:
the first formula includes:
phase_offset_0＝phase_inc*0；
phase_offset_1＝phase_inc*1；
phase_offset_2＝phase_inc*2；
phase_offset_3＝phase_inc*3；
wherein the phase _ inc is used for representing the basic phase offset parameter, the phase _ offset _0 is used for representing an initial phase of a first DDS IP core of the four DDS IP cores, the phase _ offset _1 is used for representing an initial phase of a second DDS IP core, the phase _ offset _2 is used for representing an initial phase of a third DDS IP core, and the phase _ offset _3 is used for representing an initial phase of a fourth DDS IP core.
Preferably, the first and second electrodes are formed of a metal,
the calculating unit, when performing the calculating of the output phase of each DDS IP core according to each initial phase increment and the phase increment, specifically performs: calculating the output phase according to the initial phase and the phase increment of each DDS IP core by using a second formula;
phase_out＝phase_inc_int+phase_offset；
wherein phase _ out is used to characterize the output phase, phase _ inc _ int is used to characterize the phase increment, and phase _ offset is used to characterize the initial phase of the currently computed DDS IP core.
Preferably, the first and second electrodes are formed of a metal,
further comprising: 4 FIFO modules;
the 4 FIFO modules are respectively connected with each DDS IP core;
and the FIFO module is used for controlling each DDS IP core to output the output phase at the same time.
The embodiment of the invention provides a waveform synchronous output method and a device, wherein the waveform synchronous output method comprises the following steps: calculating a phase increment according to the phase accumulator and the target waveform data output frequency, calculating a basic phase offset parameter according to the phase increment, calculating an initial phase of each DDS IP core according to the basic phase offset parameter, calculating the output phase of each DDS IP core by using the initial phase and the phase increment respectively, outputting the output phase to a DA chip, and enabling the oscilloscope to output correct target waveform data through the phase accumulator by the DA chip. According to the invention, 4 DDS IP cores are arranged and the position of each DDS IP core is separately calculated, so that the 4 DDS IP cores can be in effective working time at the same time, the target waveform can be accurately output, and the 4 DDS IP cores can synchronously output the waveform.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below, and it is obvious that the drawings in the following description are some embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to these drawings without creative efforts.
FIG. 1 is a flow chart of a waveform synchronization output method according to an embodiment of the present invention;
FIG. 2 is a schematic diagram of a waveform synchronization output apparatus according to an embodiment of the present invention;
fig. 3 is a flow chart of a method according to an embodiment of the present invention.
Detailed Description
In order to make the objects, technical solutions and advantages of the embodiments of the present invention clearer and more complete, the technical solutions in the embodiments of the present invention will be described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are some but not all embodiments of the present invention, and based on the embodiments of the present invention, all other embodiments obtained by a person of ordinary skill in the art without creative efforts belong to the protection scope of the present invention.
As shown in fig. 1, an embodiment of the present invention provides a waveform synchronization output method, which may include the following steps:
step 101: calculating a phase increment according to a phase accumulator and the target waveform data output frequency, wherein the phase accumulator is used for setting the position of waveform output;
step 102: calculating a basic phase offset parameter according to the phase increment;
step 103: calculating the initial phase of each DDS IP core according to the basic phase offset parameters, wherein a serializer serdes of 4:1 conversion is connected with a Field Programmable Gate Array (FPGA) and a digital-to-analog conversion (DA) chip, 4 direct digital synthesizer DDS IP cores are arranged in the FPGA, and the DDS IP cores are connected with the DA chip through the serdes;
step 104: and calculating the output phase of each DDS IP core according to each initial phase increment and each phase increment, controlling each DDS IP core to output the output phase to a DA chip, and enabling the oscilloscope to output target waveform data by the DA chip through the phase accumulator.
The embodiment of the invention provides a waveform synchronous output method and a device, comprising the following steps: calculating a phase increment according to the phase accumulator and the target waveform data output frequency, calculating a basic phase offset parameter according to the phase increment, calculating the initial phase of each DDS IP core according to the basic phase offset parameter, calculating the output phase of each DDS IP core respectively by using the initial phase and the phase increment, outputting the output phase to a DA chip, and enabling the oscilloscope to output correct target waveform data through the phase accumulator by the DA chip. The invention sets 4 DDS IP cores and separately calculates the position of each DDS IP core, so that the 4 DDSIP cores can be in effective working time at the same time, the target waveform can be accurately output, and the synchronous output waveform of the 4 DDS IP cores is realized.
Specifically, the data bit width of the DA chip is 16 bits, the sampling rate is 1GHz, the data processing clock inside the FPGA is 250MHz, and in order to meet the sampling rate of the DA chip, the FPGA needs to use 4:1 parallel-to-serial conversion serdes, so that 64 bits of data need to be transmitted by the FPGA in one clock cycle, the output bit width of one DDS IP core is 3-26 bits, and in order to meet the requirement of 64 bit width, 4 DDS IP cores with 16 bits are selected and combined together to form 64 bits. The first DDS IP core outputs 0-15 bit data, the second DDS IP core outputs 16-31 bit data, the third DDS IP core outputs 32-47 bit data, and the fourth DDSIP core outputs 48-63 bit data. Because 4 DDS IP cores satisfy the relation of 4:1 conversion, the 4 IP cores need different initial phases, and if the 4 DDS IP cores do not perform calculation and adjustment, the waveform output is not synchronous. The invention can make 4 DDS IP cores output data synchronously by calculating the initial phase and the corresponding output phase of each DDS IP core, thereby outputting correct waveforms.
In an embodiment of the present invention, the step 101 of calculating the phase increment according to the phase accumulator and the target waveform data output frequency includes: the phase increment is calculated from the number of precision bits of the phase accumulator and 4 times the output frequency of the target waveform.
Specifically, for example, the target waveform data is 4MHz, and the phase accumulator uses 32-bit precision, and multiplies by 4 to obtain a phase increment of 32' h 04189374.
In an embodiment of the present invention, the calculating the basic phase shift parameter according to the phase increment in step 102 includes: the phase increment is divided by 4 to calculate the basic phase shift parameter.
Specifically, the phase increment is 32'h04189374, and the division by 4 results in a basic phase shift parameter of 32' h010624 DD.
In an embodiment of the present invention, the calculating the initial phase of each DDS IP core in step 103 according to the basic phase offset parameter includes: the initial phase of each DDS IP core is respectively calculated by the following first formula,
the first formula includes:
phase_offset_0＝phase_inc*0；
phase_offset_1＝phase_inc*1；
phase_offset_2＝phase_inc*2；
phase_offset_3＝phase_inc*3；
phase _ inc is used for representing a basic phase offset parameter, phase _ offset _0 is used for representing an initial phase of a first DDS IP core of the four DDSIP cores, phase _ offset _1 is used for representing an initial phase of a second DDS IP core, phase _ offset _2 is used for representing an initial phase of a third DDS IP core, and phase _ offset _3 is used for representing an initial phase of a fourth DDS IP core.
Specifically, the phase increment and the basic phase shift parameter calculated in the above embodiment are substituted.
Obtaining:
phase_inc_int＝32'h04189374；
phase_inc＝32'h010624DD；
phase_offset_0＝phase_inc*0＝32'h0；
phase_offset_1＝phase_inc*1＝32'h010624DD；
phase_offset_2＝phase_inc*2＝32'h020C49BA；
phase_offset_3＝phase_inc*3＝32'h03126E97；
in this embodiment of the present invention, calculating the output phase of each DDS IP core according to each initial phase increment and phase increment in step 104 includes:
calculating an output phase according to the initial phase and the phase increment of each DDS IP core by a second formula;
phase_out＝phase_inc_int+phase_offset；
phase _ out is used for representing output phase, phase _ inc _ int is used for representing phase increment, and phase _ offset is used for representing initial phase of the currently calculated DDS IP core.
Specifically, the initial phase of each DDS IP core calculated in the previous embodiment is substituted into the second formula to obtain the output phases of 4 DDS IP cores, and the output phases are sent to the DA chip to output the correct target waveform.
In an embodiment of the present invention, a first-in first-out FIFO module is connected to the DDS IP cores, so that the FIFO module controls each DDS IP core to output the output phase at the same time.
Specifically, the method in the above embodiment can ensure synchronous output waveform, and in order to further increase the reliability of the invention, a FIFO module is added, and the full signal of the FIFO module is used to determine when to read data from the FIFO and send the data to the rear-end DA chip.
For example, if one of the 4 DDS IP cores outputs data later than the other three DDS IP cores by several clock cycles, the FIFO flag is not empty after the other three routes of data are entered into the FIFO, but the non-empty flag of the FIFO of late valid data is in an empty state, at this time, the DA control module at the back end does not read data, and only if all the 4 routes of FIFO non-empty flags are not empty, the DA control module at the back end reads data.
As shown in fig. 2, an embodiment of the present invention provides a waveform synchronization output apparatus, including:
a calculation unit 201 and a control unit 202;
the calculating unit 201 calculates a phase increment according to a phase accumulator and a target waveform data output frequency, wherein the phase accumulator is used for setting the position of waveform output;
calculating a basic phase offset parameter according to the phase increment;
calculating the initial phase of each DDS IP core according to the basic phase offset parameters, wherein a serializer serdes of 4:1 conversion is connected with a Field Programmable Gate Array (FPGA) and a digital-to-analog conversion (DA) chip, 4 direct digital synthesizer DDS IP cores are arranged in the FPGA, and the 4 DDS IP cores are connected with the DA chip through serdes;
the control unit 202 calculates an output phase according to each initial phase increment and each phase increment and controls each DDSIP core to output the output phase to the DA chip, so that the DA chip enables the oscilloscope to output target waveform data through the phase accumulator.
In an embodiment of the present invention, when the calculating unit 101 calculates the phase increment according to the phase accumulator and the target waveform data output frequency, it specifically performs: the phase increment is calculated from the number of precision bits of the phase accumulator and 4 times the output frequency of the target waveform.
In an embodiment of the present invention, when the calculating unit 101 calculates the basic phase shift parameter according to the phase increment, it specifically performs: the phase increment is divided by 4 to calculate the basic phase shift parameter.
In one embodiment of the present invention, the first and second electrodes are,
when calculating the initial phase of each DDS IP core according to the basic phase offset parameter, the calculating unit 101 specifically performs: the initial phase of each DDS IP core is respectively calculated by the following first formula:
the first formula includes:
phase_offset_0＝phase_inc*0；
phase_offset_1＝phase_inc*1；
phase_offset_2＝phase_inc*2；
phase_offset_3＝phase_inc*3；
phase _ inc is used for representing a basic phase offset parameter, phase _ offset _0 is used for representing an initial phase of a first DDS IP core of the four DDSIP cores, phase _ offset _1 is used for representing an initial phase of a second DDS IP core, phase _ offset _2 is used for representing an initial phase of a third DDS IP core, and phase _ offset _3 is used for representing an initial phase of a fourth DDS IP core.
In an embodiment of the present invention, when the calculating unit 101 calculates the output phase of each DDS IP core according to each initial phase increment and phase increment, it specifically performs: calculating an output phase according to the initial phase and the phase increment of each DDS IP core by a second formula;
phase_out＝phase_inc_int+phase_offset；
phase _ out is used for representing output phase, phase _ inc _ int is used for representing phase increment, and phase _ offset is used for representing initial phase of the currently calculated DDS IP core.
In an embodiment of the present invention, the waveform synchronization output apparatus further includes: 4 FIFO modules;
4 FIFO modules connected to each DDS IP core;
and the FIFO module is used for controlling each DDS IP core to output the output phase at the same time.
Because the information interaction, execution process, and other contents between the units in the device are based on the same concept as the method embodiment of the present invention, specific contents may refer to the description in the method embodiment of the present invention, and are not described herein again.
As shown in fig. 3, one implementation of the embodiment of the present invention includes the following steps:
step 301: connecting a board card power supply with a rear-end oscilloscope, and setting an internal DDS working mode through a switch;
step 302: electrifying the board card, and configuring the waveform frequency expected to be output through an upper computer control interface, if 4MHz is expected to be output;
step 303: after the working switch key is pushed, the oscilloscope at the back end displays a sine wave with expected frequency.
The embodiments of the invention have at least the following beneficial effects:
1. in an embodiment of the invention, a phase increment is calculated according to a phase accumulator and a target waveform data output frequency, a basic phase offset parameter is calculated according to the phase increment, an initial phase of each DDS IP core is calculated according to the basic phase offset parameter, the output phase of each DDS IP core is respectively calculated by using the initial phase and the phase increment, the output phase is output to a DA chip, and the DA chip enables an oscilloscope to output correct target waveform data through a phase accumulator. According to the invention, 4 DDS IP cores are arranged and the position of each DDS IP core is calculated separately, so that the 4 DDS IP cores can be in effective working time at the same time, a target waveform can be accurately output, and the 4 DDS IP cores can synchronously output the waveform.
2. In the embodiment of the invention, 4 DDS IP cores are arranged in the FPGA, so that the high sampling rate of the DA chip can be met, the DDSIP core generation device is suitable for application scenes of the high sampling rate DA chip, such as the computer field, cloud terminals, Internet of things terminals, multimedia terminals, automobile electronic terminals and the like, and the usability of the DDSIP core generation device is improved.
3. In the embodiment of the invention, each DDS IP core is connected with a first-in first-out FIFO module so that the FIFO module controls each DDS IP core to output an output phase at the same time, and the reliability of the invention is further improved.
The present invention also provides a computer-readable medium storing instructions for causing a computer to perform a waveform synchronization output method as described herein. Specifically, a system or an apparatus equipped with a storage medium on which software program codes that realize the functions of any of the above-described embodiments are stored may be provided, and a computer (or a CPU or MPU) of the system or the apparatus is caused to read out and execute the program codes stored in the storage medium.
In this case, the program code itself read from the storage medium can realize the functions of any of the above-described embodiments, and thus the program code and the storage medium storing the program code constitute a part of the present invention.
Examples of the storage medium for supplying the program code include a floppy disk, a hard disk, a magneto-optical disk, an optical disk (e.g., CD-ROM, CD-R, CD-RW, DVD-ROM, DVD-RAM, DVD-RW, DVD + RW), a magnetic tape, a nonvolatile memory card, and a ROM. Alternatively, the program code may be downloaded from a server computer via a communications network.
Further, it should be clear that the functions of any one of the above-described embodiments may be implemented not only by executing the program code read out by the computer, but also by causing an operating system or the like operating on the computer to perform a part or all of the actual operations based on the instructions of the program code.
Further, it is to be understood that the program code read out from the storage medium is written to a memory provided in an expansion board inserted into the computer or to a memory provided in an expansion unit connected to the computer, and then causes a CPU or the like mounted on the expansion board or the expansion unit to perform part or all of the actual operations based on instructions of the program code, thereby realizing the functions of any of the above-described embodiments.
It should be noted that not all steps and modules in the above flows and system structure diagrams are necessary, and some steps or modules may be omitted according to actual needs. The execution order of the steps is not fixed and can be adjusted as required. The system structures described in the above embodiments may be physical structures or logical structures, that is, some modules may be implemented by the same physical entity, or some modules may be implemented by a plurality of physical entities separately, or some components in a plurality of independent devices may be implemented together.
In the above embodiments, the hardware unit may be implemented mechanically or electrically. For example, a hardware unit may include permanently dedicated circuitry or logic (e.g., a dedicated processor, FPGA or ASIC) to perform the corresponding operations. The hardware elements may also comprise programmable logic or circuitry, such as a general purpose processor or other programmable processor, that may be temporarily configured by software to perform the corresponding operations. The specific implementation (mechanical, or dedicated permanent, or temporarily set) may be determined based on cost and time considerations.
While the invention has been shown and described in detail in the drawings and in the preferred embodiments, it is not intended to limit the invention to the embodiments disclosed, and it will be apparent to those skilled in the art that various combinations of the code auditing means in the various embodiments described above may be used to obtain further embodiments of the invention, which are also within the scope of the invention.
Claims (10)
1. The waveform synchronization output method is characterized by comprising the following steps:
calculating a phase increment according to a phase accumulator and a target waveform data output frequency, wherein the phase accumulator is used for setting the position of waveform output;
calculating a basic phase offset parameter according to the phase increment;
calculating the initial phase of each DDS IP core according to the basic phase offset parameters, wherein a serializer serdes of 4:1 conversion is connected with a field programmable logic gate array (FPGA) and a digital-to-analog conversion (DA) chip, 4 direct digital synthesizer DDSIP cores are arranged in the FPGA, and the 4 DDS IP cores are connected with the DA chip through the serdes;
and calculating the output phase of each DDS IP core according to each initial phase increment and the phase increment, and controlling each DDS IP core to output the output phase to the DA chip so that the DA chip enables the oscilloscope to output the target waveform data through the phase accumulator.
2. The method of claim 1,
the calculating of the phase increment according to the phase accumulator and the target waveform data output frequency comprises: and calculating the phase increment according to the precision digit number of the phase accumulator and 4 times of the output frequency of the target waveform.
3. The method of claim 2,
the calculating of the basic phase shift parameter according to the phase increment includes: dividing the phase increment by 4 to calculate the basic phase offset parameter.
4. The method of claim 1,
the calculating the initial phase of each DDSIP core according to the basic phase offset parameter comprises: respectively calculating the initial phase of each DDS IP core by the following first formula:
the first formula includes:
phase_offset_0＝phase_inc*0；
phase_offset_1＝phase_inc*1；
phase_offset_2＝phase_inc*2；
phase_offset_3＝phase_inc*3；
wherein the phase _ inc is used for representing the basic phase offset parameter, the phase _ offset _0 is used for representing an initial phase of a first DDS IP core of the four DDS IP cores, the phase _ offset _1 is used for representing an initial phase of a second DDS IP core, the phase _ offset _2 is used for representing an initial phase of a third DDS IP core, and the phase _ offset _3 is used for representing an initial phase of a fourth DDS IP core.
5. The method of claim 1,
the calculating the output phase of each DDS IP core according to each initial phase increment and the phase increment comprises:
calculating the output phase according to the initial phase and the phase increment of each DDS IP core by using a second formula;
phase_out＝phase_inc_int+phase_offset；
wherein phase _ out is used to characterize the output phase, phase _ inc _ int is used to characterize the phase increment, and phase _ offset is used to characterize the initial phase of the currently computed DDS IP core.
6. The method according to any one of claims 1 to 5,
further comprising: and each DDS IP core is connected with a first-in first-out FIFO module so that the FIFO module controls each DDS IP core to output the output phase at the same time.
7. A waveform synchronization output apparatus, comprising:
a calculation unit and a control unit;
the calculating unit is used for calculating a phase increment according to a phase accumulator and a target waveform data output frequency, wherein the phase accumulator is used for setting the position of waveform output;
calculating a basic phase offset parameter according to the phase increment;
calculating the initial phase of each DDS IP core according to the basic phase offset parameters, wherein a serializer serdes of 4:1 conversion is connected with a field programmable logic gate array (FPGA) and a digital-to-analog conversion (DA) chip, 4 direct digital synthesizer DDS IP cores are arranged in the FPGA, and the 4 DDS IP cores are connected with the DA chip through the serdes;
and the control unit is used for calculating an output phase according to each initial phase increment and each phase increment and controlling each DDS IP core to output the output phase to the DA chip so that the DA chip enables the oscilloscope to output the target waveform data through the phase accumulator.
8. The apparatus of claim 7,
when the calculating unit calculates the phase increment according to the phase accumulator and the target waveform data output frequency, the calculating unit specifically executes: and calculating the phase increment according to the precision digit number of the phase accumulator and 4 times of the output frequency of the target waveform.
9. The apparatus of claim 8,
when the calculating unit executes the calculation of the basic phase offset parameter according to the phase increment, specifically executing: dividing the phase increment by 4 to calculate the basic phase offset parameter.
And/or the presence of a gas in the gas,
when the calculating unit executes the initial phase of each DDS IP core calculated according to the basic phase offset parameter, specifically execute: respectively calculating the initial phase of each DDS IP core by the following first formula:
the first formula includes:
phase_offset_0＝phase_inc*0；
phase_offset_1＝phase_inc*1；
phase_offset_2＝phase_inc*2；
phase_offset_3＝phase_inc*3；
wherein the phase _ inc is used for representing the basic phase offset parameter, the phase _ offset _0 is used for representing an initial phase of a first DDS IP core of the four DDS IP cores, the phase _ offset _1 is used for representing an initial phase of a second DDS IP core, the phase _ offset _2 is used for representing an initial phase of a third DDS IP core, and the phase _ offset _3 is used for representing an initial phase of a fourth DDS IP core.
And/or the presence of a gas in the gas,
the calculating unit, when performing the calculating of the output phase of each DDS IP core according to each initial phase increment and the phase increment, specifically performs: calculating the output phase according to the initial phase and the phase increment of each DDS IP core by using a second formula;
phase_out＝phase_inc_int+phase_offset；
wherein phase _ out is used to characterize the output phase, phase _ inc _ int is used to characterize the phase increment, and phase _ offset is used to characterize the initial phase of the currently computed DDS IP core.
10. The apparatus according to any one of claims 7 to 9,
further comprising: 4 FIFO modules;
the 4 FIFO modules are respectively connected with each DDS IP core;
and the FIFO module is used for controlling each DDS IP core to output the output phase at the same time.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202010119903.7A CN111338424A (en) | 2020-02-26 | 2020-02-26 | Waveform synchronous output method and device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202010119903.7A CN111338424A (en) | 2020-02-26 | 2020-02-26 | Waveform synchronous output method and device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN111338424A true CN111338424A (en) | 2020-06-26 |
Family
ID=71181899
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202010119903.7A Pending CN111338424A (en) | 2020-02-26 | 2020-02-26 | Waveform synchronous output method and device |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN111338424A (en) |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103595675A (en) * | 2012-08-16 | 2014-02-19 | 电子科技大学 | Continuous phase 8PSK modulation method |
| CN105207671A (en) * | 2015-09-08 | 2015-12-30 | 四川鸿创电子科技有限公司 | High-speed digital signal parallel DDS synthesis method |
| CN106774628A (en) * | 2016-12-01 | 2017-05-31 | 中国电子科技集团公司第四十研究所 | A kind of multichannel editing device and method |
| CN107505053A (en) * | 2017-08-23 | 2017-12-22 | 浙江工业大学 | A kind of sinusoidal signal method for measuring phase difference based on FPGA and FFT technique |
| CN209132659U (en) * | 2019-01-30 | 2019-07-19 | 北京昊海雅正科技有限公司 | A kind of clock signal generating apparatus |
-
2020
- 2020-02-26 CN CN202010119903.7A patent/CN111338424A/en active Pending
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103595675A (en) * | 2012-08-16 | 2014-02-19 | 电子科技大学 | Continuous phase 8PSK modulation method |
| CN105207671A (en) * | 2015-09-08 | 2015-12-30 | 四川鸿创电子科技有限公司 | High-speed digital signal parallel DDS synthesis method |
| CN106774628A (en) * | 2016-12-01 | 2017-05-31 | 中国电子科技集团公司第四十研究所 | A kind of multichannel editing device and method |
| CN107505053A (en) * | 2017-08-23 | 2017-12-22 | 浙江工业大学 | A kind of sinusoidal signal method for measuring phase difference based on FPGA and FFT technique |
| CN209132659U (en) * | 2019-01-30 | 2019-07-19 | 北京昊海雅正科技有限公司 | A kind of clock signal generating apparatus |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US6532561B1 (en) | Event based semiconductor test system | |
| CN105183423B (en) | A kind of cross-clock domain asynchronous data treating method and apparatus | |
| KR101139141B1 (en) | Timing generator and semiconductor testing apparatus | |
| KR101310724B1 (en) | Method and circuit for local clock generation and smartcard including it thereon | |
| CN109687867B (en) | Clock calibration method and calibration circuit for crystal-oscillator-free USB (universal serial bus) equipment | |
| US8962965B2 (en) | Musical sound generation device, storage medium, and musical sound generation method | |
| CN113312863B (en) | Analog clock generation method and device, electronic equipment and readable storage medium | |
| US11188115B2 (en) | Sequence signal generator and sequence signal generation method | |
| US7480688B2 (en) | Phase persistent agile signal source method, apparatus, and computer program product | |
| CN117234461B (en) | Multichannel pseudo-random noise modulation device | |
| CN111338424A (en) | Waveform synchronous output method and device | |
| JP2000321340A (en) | Event type test system | |
| CN113491082B (en) | Data processing device | |
| CN107800429B (en) | Signal generator with external trigger synchronization function and signal generation method | |
| WO2016134632A1 (en) | Data processing system | |
| CN103377690A (en) | Data sending and receiving device and system and method for data transmission | |
| CN114924614B (en) | Multi-board output signal synchronization method and device | |
| US20240168721A1 (en) | Apparatus for generating a plurality of ultra-high speed pseudo-random signals and multichannel pseudo-random noise modulation device thereof | |
| CN110688811B (en) | Random weight controllable method for accelerating design verification of SOC module | |
| Wenxing et al. | The Design of Digital Frequency Synthesizer Based on VHDL | |
| KR101364267B1 (en) | Timing generation and format apparatus in large scale integrated circuit tester | |
| CN107819533B (en) | Method and system for creating infinite-time long-wave-shape signal capable of being changed at will | |
| CN112737571A (en) | Clock circuit and clock circuit generating method, device, equipment and medium | |
| CN117990978A (en) | Method, device, equipment and medium for determining measurement and control signal frequency band | |
| CN104375968A (en) | Host-side peripheral interface circuit |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| RJ01 | Rejection of invention patent application after publication | ||
| RJ01 | Rejection of invention patent application after publication |
Application publication date: 20200626 |