CN209071338U - Super node MOSFET terminal structure - Google Patents
Super node MOSFET terminal structure Download PDFInfo
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- CN209071338U CN209071338U CN201821941302.9U CN201821941302U CN209071338U CN 209071338 U CN209071338 U CN 209071338U CN 201821941302 U CN201821941302 U CN 201821941302U CN 209071338 U CN209071338 U CN 209071338U
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- cellular region
- termination environment
- epitaxial layer
- lightly doped
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- 230000001413 cellular effect Effects 0.000 claims abstract description 35
- 239000000758 substrate Substances 0.000 claims abstract description 8
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 10
- 229920005591 polysilicon Polymers 0.000 claims description 10
- 229910021421 monocrystalline silicon Inorganic materials 0.000 claims description 3
- 238000000034 method Methods 0.000 abstract description 7
- 238000004519 manufacturing process Methods 0.000 abstract description 4
- 239000010936 titanium Substances 0.000 description 9
- 230000015556 catabolic process Effects 0.000 description 5
- 238000010586 diagram Methods 0.000 description 4
- 238000000407 epitaxy Methods 0.000 description 4
- 238000005516 engineering process Methods 0.000 description 3
- 239000004065 semiconductor Substances 0.000 description 3
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- 239000012535 impurity Substances 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 230000008859 change Effects 0.000 description 1
- 230000007812 deficiency Effects 0.000 description 1
- 230000001419 dependent effect Effects 0.000 description 1
- 238000007599 discharging Methods 0.000 description 1
- 239000002019 doping agent Substances 0.000 description 1
- 230000005684 electric field Effects 0.000 description 1
- 230000005611 electricity Effects 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 238000002474 experimental method Methods 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 238000005286 illumination Methods 0.000 description 1
- 239000004973 liquid crystal related substance Substances 0.000 description 1
- 238000001459 lithography Methods 0.000 description 1
- VDGJOQCBCPGFFD-UHFFFAOYSA-N oxygen(2-) silicon(4+) titanium(4+) Chemical compound [Si+4].[O-2].[O-2].[Ti+4] VDGJOQCBCPGFFD-UHFFFAOYSA-N 0.000 description 1
- 238000002360 preparation method Methods 0.000 description 1
- 230000008569 process Effects 0.000 description 1
- 230000009467 reduction Effects 0.000 description 1
- 235000012239 silicon dioxide Nutrition 0.000 description 1
- 239000000377 silicon dioxide Substances 0.000 description 1
Abstract
A kind of super node MOSFET terminal structure, comprising: N-type heavy doping substrate and N-type lightly doped epitaxial layer formed thereon；The N-type lightly doped epitaxial layer includes cellular region and termination environment；At least one transistor unit is formed in the cellular region, the transistor unit includes a pair of of the cellular region P column being formed in the N-type lightly doped epitaxial layer；A pair of cellular region top end P is connected separately with an area PXing Ti；N-type lightly doped epitaxial layer surface is formed with gate structure；At least one termination environment P column is formed in the termination environment；The width of the termination environment P column is equal to the half of the cellular region P column width, and spacing is also the half of cellular region P column width, and the spacing in terminal p-shaped area is gradually increased.The utility model can promote device termination environment voltage endurance capability, improve the multifrequency nature of high pressure super-junction MOSFET device；Device manufacture method is compatible with prior art, and there are many implementations, and the voltage endurance capability of super node MOSFET terminal structure can be further promoted under the conditions of prior art.
Description
Technical field
The utility model belongs to field of semiconductor devices, is related to a kind of super node MOSFET terminal structure.
Background technique
High-voltage power MOSFET (referred to as VDMOSFET) can reduce conducting by the way that the thickness of drain terminal drift region is thinned
Resistance improves device however, the thickness that drain terminal drift region is thinned will reduce the breakdown voltage of device, therefore in VDMOSFET
The breakdown voltage of part and the conducting resistance for reducing device are conflicts, and super node MOSFET uses new structure of voltage-sustaining layer, are utilized
A series of alternately arranged p-type and N-type semiconductor thin layer, exhaust p-type N-type region under lower backward voltage, realize charge
It mutually compensates, to make N-type region realize high breakdown voltage under high-dopant concentration, to obtain low on-resistance and height simultaneously
Breakdown voltage breaks the theoretical limit of conventional power MOSFET conducting resistance.
It is excellent that super node MOSFET has that conduction loss is low, gate charge is low, switching speed is fast, device heating is small and efficiency is high
Point, product can be widely used for PC, laptop, net book or mobile phone, illumination (high-voltage gas discharging light) product, electricity
Depending on the power supply or adapter of the high-end consumption electronic products such as machine (liquid crystal or plasma TV) and game machine.
Fig. 2, Fig. 3 are please referred to, Fig. 2, Fig. 3 are respectively indicated as conventional high pressure super node MOSFET structure (hereinafter referred to as HV-
) and low pressure super node MOSFET structure (hereinafter referred to as LV-MOS) MOS.As shown in Fig. 2, high pressure super node MOSFET includes that N-type is heavily doped
Miscellaneous substrate 101, N-type lightly doped epitaxial layer 102 and the P column 103 being formed in the N-type lightly doped epitaxial layer 102 and the area PXing Ti
104,102 surface of N-type lightly doped epitaxial layer is formed with gate oxide 105 and polysilicon gate 106.As shown in figure 3, low pressure
Super node MOSFET includes the polysilicon pillar 107 and polysilicon gate 108 being formed in N-type epitaxy layer.HV-MOS and LV-MOS are
It is that the groove structure of a longitudinal direction is formed by certain technology mode in N-type epitaxy layer, it in this way can be in device pressure resistance
Meanwhile conducting resistance is greatly reduced, improve device performance.
But high-voltage MOS pipe and low pressure metal-oxide-semiconductor have many differences again on device architecture and process:
1) in lateral device dimensions, the primitive unit cell size (pitch) of HV-MOS is generally at more than ten microns, and LV-MOS
Pitch generally only has several microns.On identical chip area, the primitive unit cell density of LV-MOS can be higher by much than HV-MOS, institute
Higher for requirements such as technology feature sizes and lithography alignment accuracy with low-voltage device, difficulty is bigger.
2) on device longitudinal size, the N-type epitaxy layer thickness and trench depth of HV-MOS generally has tens microns, and LV-
MOS can be in several microns.For such a deep groove structure of introducing, depth is deeper, and technology difficulty is bigger, so high-voltage device
Part is more dependent on the depth and technique of groove；
3) in the technique that groove is realized, the P column (Ppillar-trench) of HV-MOS is made of p type impurity, in N-type
Groove structure is directly dug out first with deep etching technique on epitaxial layer, then epitaxial growth p type impurity layer.And LV-MOS
Polysilicon pillar is made of silicon dioxide layer and polysilicon layer, and groove is dug out in N-type epitaxy layer, then thermally grown titanium dioxide
Silicon dielectric layer forms required polysilicon pillar in the deposit for carrying out polysilicon.
Nowadays, the cellular region of power device has been able to reach higher resistance to voltage levels by design, but in reality
In the production process on border, it is also necessary to the fringe region for considering transistor, for vertical devices, the marginal portion of a chip
Cellular other than the voltage in vertical direction to be born, still suffer from the voltage in horizontal direction, therefore the terminal edge of device
Edge region becomes a very important factor for restricting entire device electric breakdown strength.
Therefore it provides a kind of super node MOSFET terminal structure and preparation method thereof, to further increase high pressure superjunction
The voltage endurance capability of the termination environment MOSFET becomes those skilled in the art and urgently solves to improve the whole voltage endurance capability of transistor
An important technological problems certainly.
Utility model content
In view of the foregoing deficiencies of prior art, the purpose of this utility model is to provide a kind of super node MOSFET terminals
Structure, the structure can promote device termination environment voltage endurance capability, improve the multifrequency nature of high pressure super-junction MOSFET device；Device system
It is compatible with prior art to make method, there are many implementations, can further promote super node MOSFET under the conditions of prior art
The voltage endurance capability of terminal structure.
In order to achieve the above objects and other related objects, the technical solution of the utility model is as follows:
A kind of super node MOSFET terminal structure, comprising: N-type heavy doping substrate and be formed in the N-type heavy doping substrate
N-type lightly doped epitaxial layer；The N-type lightly doped epitaxial layer includes cellular region and the termination environment for surrounding the cellular region；Institute
At least one transistor unit is formed in the cellular region stated, the transistor unit includes being formed in the N-type to be lightly doped
A pair of of cellular region P column in epitaxial layer；The top of a pair of cellular region P column is separately connected an area PXing Ti, and the p-type body position
In in the N-type lightly doped epitaxial layer；Gate structure is formed on the surface in a pair of of area PXing Ti；And the gate structure
Between a pair of of cellular region P column；At least multiple termination environment P columns and more than one termination environment are formed in the termination environment
The area PXing Ti；It is characterized in that:
The width of the termination environment P column is equal to the half of the cellular region P column width, the spacing of the termination environment P column
It is also the half of cellular region P column width, the spacing in the area terminal PXing Ti is gradually increased.
The depth bounds of the termination environment P column are 30~60 microns.
The cellular region P column and the termination environment P column are p type single crystal silicon.
The gate structure includes being formed in the gate oxide on N-type lightly doped epitaxial layer surface and being formed in described
The polysilicon gate on gate oxide surface.
The super node MOSFET terminal structure of the utility model, has the advantages that
In the super node MOSFET terminal structure of the utility model, the depth of termination environment P column is greater than the depth of cellular region P column,
The upper end of terminal P column is conventional VDMOS terminal, is conducive to the having lateral depletion of electric field, and the reduction of the spacing of terminal P column has
High pressure super-junction MOSFET device can be improved to improve termination environment voltage endurance capability conducive to the concentration for improving the doping of terminal p-type
Multifrequency nature.The production method of the super node MOSFET terminal structure of the utility model is compatible with prior art, and there are many realize
Mode can further promote the voltage endurance capability of super node MOSFET terminal structure under the conditions of prior art.
Detailed description of the invention
Fig. 1 is the schematic diagram of the utility model super node MOSFET terminal structure
Fig. 2 is shown as the structural schematic diagram of prior art mesohigh super node MOSFET.
Fig. 3 is shown as the structural schematic diagram of prior art mesolow super node MOSFET.
Specific embodiment
Below with reference to embodiment and attached drawing, the utility model is described in further detail, but should not limit the utility model with this
Protection scope.
First referring to Fig. 1, Fig. 1 is the schematic diagram of the utility model super node MOSFET terminal structure, as seen from the figure, this is practical
Novel super node MOSFET terminal structure embodiment, comprising: N-type heavy doping substrate 201 and be formed in the N-type heavy doping substrate
N-type lightly doped epitaxial layer 202；The N-type lightly doped epitaxial layer 202 includes cellular region I and the end for surrounding the cellular region
Petiolarea II；At least one transistor unit is formed in the cellular region, the transistor unit includes being formed in the N
A pair of of cellular region P column 203 in type lightly doped epitaxial layer 202；The top of a pair of cellular region P column 203 is separately connected a p-type body
Area 205, and the area PXing Ti 205 is located in the N-type lightly doped epitaxial layer 202；On the surface in a pair of of area PXing Ti 205
It is formed with gate structure；And the gate structure is located between a pair of of cellular region P column 203；It is formed at least in the termination environment
Multiple termination environment P columns 204 and the area more than one termination environment PXing Ti 206；It is characterized in that:
The width of the termination environment P column 204 is equal to the half of 203 width of cellular region P column, the termination environment P column
204 spacing is also the half of 203 width of cellular region P column, and the spacing in the area terminal PXing Ti 206 is gradually increased.
The depth bounds of the termination environment P column 204 are 30~60 microns.
The cellular region P column 203 and the termination environment P column (204) are p type single crystal silicon.
The gate structure includes being formed in the gate oxide 207 on N-type lightly doped epitaxial layer surface and being formed in
The polysilicon gate 208 on the gate oxide surface.
Experiment shows that the utility model improves termination environment voltage endurance capability, can improve high pressure super-junction MOSFET device
Multifrequency nature.
The production method of the super node MOSFET terminal structure of the utility model is compatible with prior art, and there are many realization sides
Formula can further promote the voltage endurance capability of super node MOSFET terminal structure under the conditions of prior art.So the utility model
It effectively overcomes various shortcoming in the prior art and there is high industrial utilization value.
The above embodiments are only illustrative of the principle and efficacy of the utility model, and not for limitation, this is practical new
Type.Any person skilled in the art can all carry out above-described embodiment under the spirit and scope without prejudice to the utility model
Modifications and changes.Therefore, such as those of ordinary skill in the art without departing from the revealed essence of the utility model
All equivalent modifications or change completed under mind and technical idea, should be covered by the claim of the utility model.
Claims (4)
1. a kind of super node MOSFET terminal structure, comprising: N-type heavy doping substrate (201) and be formed in the N-type heavy doping substrate
On N-type lightly doped epitaxial layer (202)；The N-type lightly doped epitaxial layer (202) includes cellular region (I) and the encirclement member
The termination environment (II) in born of the same parents area；At least one transistor unit is formed in the cellular region, the transistor unit includes
A pair of of the cellular region P column (203) being formed in the N-type lightly doped epitaxial layer (202)；The top of a pair of cellular region P column (203)
End is separately connected an area PXing Ti (205), and the area PXing Ti (205) is located in the N-type lightly doped epitaxial layer (202)；Institute
The surface for a pair of of the area PXing Ti (205) stated is formed with gate structure；And the gate structure be located at a pair of of cellular region P column (203) it
Between；At least multiple termination environment P columns (204) and the area more than one termination environment PXing Ti (206) are formed in the termination environment；
It is characterized by:
The width of the termination environment P column (204) is equal to the half of cellular region P column (203) width, the termination environment P column
(204) spacing is also the half of cellular region P column (203) width, and the spacing in the area terminal PXing Ti (206) is gradually increased.
2. super node MOSFET terminal structure according to claim 1, it is characterised in that: the termination environment P column (204)
Depth bounds are 30~60 microns.
3. super node MOSFET terminal structure according to claim 1, it is characterised in that: the cellular region P column (203) and
The termination environment P column (204) is p type single crystal silicon.
4. super node MOSFET terminal structure according to any one of claims 1 to 3, it is characterised in that: the grid knot
Structure includes being formed in the gate oxide (207) on N-type lightly doped epitaxial layer surface and being formed in the gate oxide surface
Polysilicon gate (208).
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201821941302.9U CN209071338U (en) | 2018-11-23 | 2018-11-23 | Super node MOSFET terminal structure |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201821941302.9U CN209071338U (en) | 2018-11-23 | 2018-11-23 | Super node MOSFET terminal structure |
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| Publication Number | Publication Date |
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| CN209071338U true CN209071338U (en) | 2019-07-05 |
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| CN201821941302.9U Active CN209071338U (en) | 2018-11-23 | 2018-11-23 | Super node MOSFET terminal structure |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111146271A (en) * | 2019-12-20 | 2020-05-12 | 北京时代民芯科技有限公司 | Super-junction MOSFET structure with terminal structure and preparation method |
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2018
- 2018-11-23 CN CN201821941302.9U patent/CN209071338U/en active Active
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111146271A (en) * | 2019-12-20 | 2020-05-12 | 北京时代民芯科技有限公司 | Super-junction MOSFET structure with terminal structure and preparation method |
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| TR01 | Transfer of patent right |
Effective date of registration: 20231025 Address after: Room 402, Building A10, No. 777 Jianshe West Road, Binhu District, Wuxi City, Jiangsu Province Patentee after: Wuxi Gufeng Semiconductor Co.,Ltd. Address before: 518000 Room 501, 2-6 / F, building 9 (block f), huachuangda culture and Technology Industrial Park, Hedong commercial city, district 49, Bao'an District, Shenzhen City, Guangdong Province Patentee before: SHENZHEN GOFORD ELECTRONICS CO.,LTD. Patentee before: GOFORD SEMICONDUCTOR (HONG KONG) LTD. |