CN209030163U - A kind of operation amplifier circuit of low noise - Google Patents
A kind of operation amplifier circuit of low noise Download PDFInfo
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- CN209030163U CN209030163U CN201821739839.7U CN201821739839U CN209030163U CN 209030163 U CN209030163 U CN 209030163U CN 201821739839 U CN201821739839 U CN 201821739839U CN 209030163 U CN209030163 U CN 209030163U
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- pmos tube
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Abstract
The utility model discloses a kind of operation amplifier circuits of low noise, are related to technical field of integrated circuits.The operation amplifier circuit of the low noise includes connected first order amplifier and second level amplifier, the second level amplifier connection is also connected with electric current and folds sub-circuit and tail current source, and the electric current folds sub-circuit and the tail current source is connected to the first bias voltage and the second bias voltage；The operation amplifier circuit folds sub-circuit and tail current source by electric current respectively and provides bias voltage for circuit.Secondary common-source amplifier circuit is added using differential pair tube as circuit input end in technical solutions of the utility model between output stage and input stage, so that the ratio of output noise conversion to output noise reduces, to realize the function of reducing entire circuit system noise.
Description
Technical field
The utility model relates to technical field of integrated circuits, more particularly to a kind of operational amplifier of low noise.
Background technique
Operational amplifier is the circuit unit with very high-amplification-factor.In actual circuit, feedback network is usually combined
Collectively constitute certain functional module.It is a kind of amplifier with special Coupling circuit and feedback.Its output signal can be
Input signal adds, subtracts or the result of the mathematical operations such as differential, integral.Since early stage is applied in simulation computer, to realize
Mathematical operation, therefore gain the name " operational amplifier ".Operational amplifier is the circuit unit named from the angle of function, Ke Yiyou
Discrete device is realized, also may be implemented in semiconductor chip.With the development of semiconductor technology, most operation is put
Big device is existed in the form of single-chip.Operational amplifier it is many kinds of, be widely used in electronics industry.
In the design of chip, operational amplifier is one of indispensable module of numerous systems, is answered in some special
With in system, there is very high requirement for the noise of operational amplifier, low noise audio technology is just particularly important；Present technology
In the middle, the noise that low frequency is reduced usually using chopper technology, for the noise in white noise region, usually by adjusting pipe
Size, size of current reduce noise.
Summary of the invention
The main purpose of the utility model is to provide a kind of operation amplifier circuits of low noise, it is intended to reduce operation and put
The noise of big device circuit.
To achieve the above object, the utility model provides a kind of operation amplifier circuit of low noise, the operation amplifier
Device circuit includes connected first order amplifier and second level amplifier, and the second level amplifier connection is also connected with electric current folding
Folded sub-circuit and tail current source, the electric current folds sub-circuit and the tail current source is connected to the first bias voltage and the
Two bias voltages；The operation amplifier circuit folds sub-circuit and tail current source by electric current respectively and provides biased electrical for circuit
Pressure.
Preferably, the first order amplifier includes the first PMOS tube and the second PMOS tube for being connected to bias supply.
Preferably, the second level amplifier includes third PMOS tube, the 4th PMOS tube, the first NMOS tube and the 2nd NMOS
Pipe；The third PMOS tube and the 4th PMOS tube are connected to first PMOS tube and second PMOS tube, institute
It states the first NMOS tube and second NMOS tube is connected to the third PMOS tube and the 4th PMOS tube.
Preferably, the source electrode of the third PMOS tube and the 4th PMOS tube is all connected to the bias supply；It is described
The grid of third PMOS tube is connected to the drain electrode of first PMOS tube, and drain electrode is connected to the source electrode of second NMOS tube；
The grid of 4th PMOS tube is connected to the drain electrode of second PMOS tube, and drain electrode is connected to the source of first NMOS tube
Pole；The source electrode of first NMOS tube and second NMOS tube is also attached to the tail current source, first NMOS tube and
The grid of second NMOS tube is connected with each other, drain electrode is connected to the electric current and folds sub-circuit.
Preferably, the source electrode of first PMOS tube and second PMOS tube is all connected to the bias supply；It is described
The drain electrode of first PMOS tube and second PMOS tube passes through first resistor and second resistance ground connection respectively；First PMOS tube
Differential input end is connected to the grid of second PMOS tube.
Preferably, it includes the 5th PMOS tube interconnected, the 6th PMOS tube that the electric current, which folds sub-circuit, and mutually
The 7th PMOS tube and the 8th PMOS tube of connection；5th PMOS tube is connected to first NMOS tube, the 6th PMOS
Pipe is connected to second NMOS tube, and the 7th PMOS tube is connected to the 5th PMOS tube, the 8th PMOS tube connection
In the 6th PMOS tube.
Preferably, the grid of the 5th PMOS tube and the grid of the 6th PMOS tube are connected with each other, and the described 7th
The grid of PMOS tube and the grid of the 8th PMOS tube are connected with each other；The drain electrode of 5th PMOS tube is connected to described first
The source electrode of the drain electrode of NMOS tube, the 5th PMOS tube is connected to the drain electrode of the 7th PMOS tube；6th PMOS tube
Drain electrode is connected to the drain electrode of second NMOS tube, and the source electrode of the 6th PMOS tube is connected to the leakage of the 8th PMOS tube
Pole；The source electrode of 7th PMOS tube and the 8th PMOS tube is connected to power supply.
Preferably, the tail current source includes third NMOS tube and the 4th NMOS tube interconnected, and the third
NMOS tube and the 4th NMOS tube are connected to the second bias voltage.
Preferably, the drain electrode of the third NMOS tube is connected to the drain electrode and first NMOS tube of the 4th PMOS tube
Source electrode；The drain electrode of 4th NMOS tube is connected to drain electrode and the source electrode of second NMOS tube of the third PMOS tube；
The source electrode of the third NMOS tube and the 4th NMOS tube ground connection, the grid of the third NMOS tube and the 4th NMOS tube
It is connected with each other and is connected to second bias voltage.
Technical solutions of the utility model are added between output stage and input stage using differential pair tube as circuit input end
Secondary common-source amplifier circuit, so that the ratio of output noise conversion to output noise reduces, so that realizing reduces entire circuit
The function of system noise.
Detailed description of the invention
Fig. 1 is the circuit diagram of the operation amplifier circuit of the utility model low noise.
The embodiments will be further described with reference to the accompanying drawings for the realization, functional characteristics and advantage of the utility model aim.
Specific embodiment
It should be appreciated that specific embodiment described herein is only used to explain the utility model, it is not used to limit this
Utility model.
The present invention will be further described with reference to the accompanying drawing.
As shown in Figure 1, the utility model provides a kind of operation amplifier circuit of low noise, the operation amplifier circuit
Including connected first order amplifier and second level amplifier, the second level amplifier connection is also connected with electric current and folds son electricity
Road and tail current source, the electric current folds sub-circuit and the tail current source is connected to the first bias voltage Vp and second partially
Set voltage Vn；The operation amplifier circuit folds sub-circuit and tail current source by electric current respectively and provides biased electrical for circuit
Pressure.
By using differential pair tube as circuit input end, and secondary common-source amplifier is added between output stage and input stage
Circuit, so that the ratio of output noise conversion to output noise reduces, to realize the function of reducing entire circuit system noise.
Preferably, the first order amplifier includes the first PMOS tube PM1 and the 2nd PMOS for being connected to bias supply Ib
Pipe PM2.First PMOS tube PM1 and the second PMOS tube PM2 is the Differential Input of first order amplifier circuit to pipe.
Preferably, the second level amplifier includes third PMOS tube PM3, the 4th PMOS tube PM4, the first NMOS tube and
Two NMOS tubes；The third PMOS tube PM3 and the 4th PMOS tube PM4 are connected to the first PMOS tube PM1 and institute
The second PMOS tube PM2 is stated, first NMOS tube and second NMOS tube are connected to the third PMOS tube PM3 and institute
State the 4th PMOS tube PM4.
Third PMOS tube PM3, the 4th PMOS tube PM4, the first NMOS tube NM1 and the second NMOS tube NM2 are second level folding
Common source and common grid amplifier, third PMOS tube PM3 and the 4th PMOS tube PM4 play isolation third NMOS tube NM3 and the 4th NMOS tube
The effect of NM4 tail current noise, to reduce the noise of operational amplifier.
By using differential pair tube as circuit input end, and be added between output stage and input stage third PMOS tube PM3,
4th PMOS tube PM4 is as secondary common-source amplifier circuit, so that the ratio of output noise conversion to output noise reduces, thus
Realize the function of reducing entire circuit system noise.
Preferably, the source electrode of the third PMOS tube PM3 and the 4th PMOS tube PM4 are all connected to the bias supply
Ib；The grid of the third PMOS tube PM3 is connected to the drain electrode of the first PMOS tube PM1, and drain electrode is connected to described second
The source electrode of NMOS tube NM2；The grid of the 4th PMOS tube PM4 is connected to the drain electrode of the second PMOS tube PM2, and drain electrode connects
It is connected to the source electrode of the first NMOS tube NM1；The source electrode of the first NMOS tube NM1 and the second NMOS tube NM2 are also connected with
In the tail current source, the grid of the first NMOS tube NM1 and the second NMOS tube NM2 are connected with each other, drain electrode is connected to
The electric current folds sub-circuit.
Preferably, the source electrode of the first PMOS tube PM1 and the second PMOS tube PM2 are all connected to the bias supply
Ib；The drain electrode of the first PMOS tube PM1 and the second PMOS tube PM2 pass through first resistor and second resistance ground connection respectively；
The grid of the first PMOS tube PM1 and the second PMOS tube PM2 are connected to differential input end.
Preferably, it includes the 5th PMOS tube PM5 interconnected, the 6th PMOS tube PM6 that the electric current, which folds sub-circuit, with
And the 7th PMOS tube PM7 and the 8th PMOS tube PM8 interconnected；The 5th PMOS tube PM5 is connected to the first NMOS
Pipe NM1, the 6th PMOS tube PM6 are connected to the second NMOS tube NM2, and the 7th PMOS tube PM7 is connected to described
Five PMOS tube PM5, the 8th PMOS tube PM8 are connected to the 6th PMOS tube PM6.
Preferably, the grid of the grid of the 5th PMOS tube PM5 and the 6th PMOS tube PM6 are connected with each other, described
The grid of the grid of 7th PMOS tube PM7 and the 8th PMOS tube PM8 are connected with each other；The drain electrode of the 5th PMOS tube PM5
It is connected to the drain electrode of the first NMOS tube NM1, the source electrode of the 5th PMOS tube PM5 is connected to the 7th PMOS tube PM7
Drain electrode；The drain electrode of the 6th PMOS tube PM6 is connected to the drain electrode of the second NMOS tube NM2, the 6th PMOS tube PM6
Source electrode be connected to the drain electrode of the 8th PMOS tube PM8；The source of the 7th PMOS tube PM7 and the 8th PMOS tube PM8
Pole is connected to power supply.
Preferably, the tail current source includes third NMOS tube NM3 and the 4th NMOS tube NM4 interconnected, and described
Third NMOS tube NM3 and the 4th NMOS tube NM4 are connected to the second bias voltage.
Preferably, the drain electrode of the third NMOS tube NM3 is connected to the drain electrode and described first of the 4th PMOS tube PM4
The source electrode of NMOS tube NM1；The drain electrode of the 4th NMOS tube NM4 is connected to the drain electrode and described of the third PMOS tube PM3
The source electrode of two NMOS tube NM2；The source electrode of the third NMOS tube NM3 and the 4th NMOS tube NM4 ground connection, the 3rd NMOS
The grid of pipe NM3 and the 4th NMOS tube NM4 are connected with each other and are connected to second bias voltage.
It should be understood that cannot therefore limit the utility model the above is only the preferred embodiment of the utility model
The scope of the patents, equivalent structure or equivalent flow shift made by using the description of the utility model and the drawings, or it is straight
It connects or is used in other related technical areas indirectly, be also included in the patent protection scope of the utility model.
Claims (9)
1. a kind of operation amplifier circuit of low noise, which is characterized in that the operation amplifier circuit includes connected first
Grade amplifier and second level amplifier, the second level amplifier connection are also connected with electric current and fold sub-circuit and tail current source,
The electric current folds sub-circuit and the tail current source is connected to the first bias voltage and the second bias voltage；The operation
Amplifier circuit folds sub-circuit and tail current source by electric current respectively and provides bias voltage for circuit.
2. the operation amplifier circuit of low noise according to claim 1, which is characterized in that the first order amplifier packet
Include the first PMOS tube and the second PMOS tube for being connected to bias supply.
3. the operation amplifier circuit of low noise according to claim 2, which is characterized in that the second level amplifier packet
Include third PMOS tube, the 4th PMOS tube, the first NMOS tube and the second NMOS tube；The third PMOS tube and the 4th PMOS tube
It is connected to first PMOS tube and second PMOS tube, first NMOS tube and second NMOS tube connect respectively
It is connected to the third PMOS tube and the 4th PMOS tube.
4. the operation amplifier circuit of low noise according to claim 3, which is characterized in that the third PMOS tube and institute
The source electrode for stating the 4th PMOS tube is all connected to the bias supply；The grid of the third PMOS tube is connected to the first PMOS
The drain electrode of pipe, drain electrode are connected to the source electrode of second NMOS tube；The grid of 4th PMOS tube is connected to described second
The drain electrode of PMOS tube, drain electrode are connected to the source electrode of first NMOS tube；First NMOS tube and second NMOS tube
Source electrode be also attached to the tail current source, the grid of first NMOS tube and second NMOS tube is connected with each other, drain electrode
It is connected to the electric current and folds sub-circuit.
5. the operation amplifier circuit of low noise according to claim 3, which is characterized in that first PMOS tube and institute
The source electrode for stating the second PMOS tube is all connected to the bias supply；The drain electrode of first PMOS tube and second PMOS tube point
It Tong Guo not first resistor and second resistance ground connection；It is defeated that the grid of first PMOS tube and second PMOS tube is connected to difference
Enter end.
6. the operation amplifier circuit of low noise according to claim 3, which is characterized in that the electric current folds sub-circuit
Including the 5th PMOS tube, the 6th PMOS tube and the 7th PMOS tube interconnected interconnected and the 8th PMOS tube；It is described
5th PMOS tube is connected to first NMOS tube, and the 6th PMOS tube is connected to second NMOS tube, and the described 7th
PMOS tube is connected to the 5th PMOS tube, and the 8th PMOS tube is connected to the 6th PMOS tube.
7. the operation amplifier circuit of low noise according to claim 6, which is characterized in that the grid of the 5th PMOS tube
The grid of pole and the 6th PMOS tube is connected with each other, the grid and the grid phase of the 8th PMOS tube of the 7th PMOS tube
It connects；The drain electrode of 5th PMOS tube is connected to the drain electrode of first NMOS tube, and the source electrode of the 5th PMOS tube connects
It is connected to the drain electrode of the 7th PMOS tube；The drain electrode of 6th PMOS tube is connected to the drain electrode of second NMOS tube, described
The source electrode of 6th PMOS tube is connected to the drain electrode of the 8th PMOS tube；The source of 7th PMOS tube and the 8th PMOS tube
Pole is connected to power supply.
8. the operation amplifier circuit of low noise according to claim 3, which is characterized in that the tail current source includes phase
The third NMOS tube and the 4th NMOS tube to connect, and the third NMOS tube and the 4th NMOS tube are connected to the second biasing
Voltage.
9. the operation amplifier circuit of low noise according to claim 8, which is characterized in that the leakage of the third NMOS tube
Pole is connected to drain electrode and the source electrode of first NMOS tube of the 4th PMOS tube；The drain electrode of 4th NMOS tube is connected to
The drain electrode of the third PMOS tube and the source electrode of second NMOS tube；The source of the third NMOS tube and the 4th NMOS tube
The grid of pole ground connection, the third NMOS tube and the 4th NMOS tube is connected with each other and is connected to second bias voltage.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201821739839.7U CN209030163U (en) | 2018-10-26 | 2018-10-26 | A kind of operation amplifier circuit of low noise |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201821739839.7U CN209030163U (en) | 2018-10-26 | 2018-10-26 | A kind of operation amplifier circuit of low noise |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN209030163U true CN209030163U (en) | 2019-06-25 |
Family
ID=66907912
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201821739839.7U Active CN209030163U (en) | 2018-10-26 | 2018-10-26 | A kind of operation amplifier circuit of low noise |
Country Status (1)
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| CN (1) | CN209030163U (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110491333A (en) * | 2019-10-15 | 2019-11-22 | 上海视欧光电科技有限公司 | A kind of interpolation operational amplifier circuit and display panel |
-
2018
- 2018-10-26 CN CN201821739839.7U patent/CN209030163U/en active Active
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110491333A (en) * | 2019-10-15 | 2019-11-22 | 上海视欧光电科技有限公司 | A kind of interpolation operational amplifier circuit and display panel |
| US11050397B2 (en) | 2019-10-15 | 2021-06-29 | Seeya Optronics Co., Ltd. | Interpolation operational amplifier circuit and display panel |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| GR01 | Patent grant | ||
| GR01 | Patent grant | ||
| PE01 | Entry into force of the registration of the contract for pledge of patent right | ||
| PE01 | Entry into force of the registration of the contract for pledge of patent right |
Denomination of utility model: Low noise operational amplifier circuit Effective date of registration: 20190926 Granted publication date: 20190625 Pledgee: Bank of Chengdu science and technology branch of Limited by Share Ltd Pledgor: Chengdu Rui core micro Polytron Technologies Inc Registration number: Y2019510000026 |
|
| PC01 | Cancellation of the registration of the contract for pledge of patent right | ||
| PC01 | Cancellation of the registration of the contract for pledge of patent right |
Date of cancellation: 20220614 Granted publication date: 20190625 Pledgee: Bank of Chengdu science and technology branch of Limited by Share Ltd. Pledgor: CHENGDU ANALOG CIRCUIT TECHNOLOGY Inc. Registration number: Y2019510000026 |