CN209017016U - A kind of branch realization high-speed data summation circuit - Google Patents

Abstract

The utility model discloses a kind of branches to realize high-speed data summation circuit, including din input signal, clk clock signal, clkdiv2 input signal, first selector, first accumulator, second selector, second accumulator, first adder, third accumulator, second adder, 4th accumulator and third selector, wherein, the first selector, the second selector and the third selector include the input end D, input the end CLK, export the end Q and the output end QN, the din input signal is connect with the end input CLK of the first selector, first accumulator, second accumulator, the third accumulator and the 4th accumulator include the input end D, input the end CLK and the output end Q, the end output Q of the first selector and the input D1 End connection, the first selector input end D is connect with the first selector output end QN respectively, the end input D for exporting the end Q and second selector of first accumulator connects.

Description

A kind of branch realization high-speed data summation circuit

Technical field

The utility model relates to circuit design fields, it particularly relates to which a kind of branch realizes high-speed data summation circuit.

Background technique

In VLSI Design, with the continuous increase of data bit width, the complexity of logic increases and clock Frequency becomes faster.Generally for design correctness and the advance for improving technique of having to, more advanced technique anticipates simultaneously Taste higher price.Thus under conditions of not improving technique, by the circuit structure design of innovation come in accordance with higher frequency Rate requirement, this is a huge challenge.

As shown in Fig. 2, input frequency word din does a sub-addition in each operating clock cycle: tiring out with last Value added sum does addition；With the increase of frequency word bit wide and the quickening of clock frequency, two are completed within a clock cycle Several additions will become more and more difficult under existing process conditions greatly, and even without possibility, common practice is exactly to improve Process conditions；Faster logic unit is provided to realize higher speed.

In the design of high-speed DDS D/A converting circuit, frequency accumulator is a clock bottleneck circuit in design: frequency Accumulator requires a clock cycle that will add up a frequency word.Thus as the required precision of frequency word is higher and higher, frequency The bit wide of rate word is also increasing, and the rate of digital-to-analogue conversion also require it is higher and higher.The challenge of design is also increasing.

For the problems in the relevant technologies, currently no effective solution has been proposed.

Utility model content

The purpose of the utility model is to provide a kind of branches to realize high-speed data summation circuit, to overcome existing the relevant technologies Existing above-mentioned technical problem.

Technical solutions of the utility model are achieved in that

A kind of branch realization high-speed data summation circuit, including din input signal, clk clock signal, clkdiv2 input Signal, first selector, the first accumulator, second selector, the second accumulator, first adder, third accumulator, second add Musical instruments used in a Buddhist or Taoist mass, the 4th accumulator and third selector, wherein the first selector, the second selector and third selection Device includes the input end D, the input end CLK, the output end Q and exports the end QN, the din input signal and the first selector The connection of the end CLK is inputted, first accumulator, second accumulator, the third accumulator and the 4th accumulator are equal Including the input end D, the input end CLK and the output end Q, the end output Q of the first selector is connect with the end input D1, described First selector input the end D respectively with the first selector output end QN connect, the end output Q of first accumulator and The end input D of second selector connects, and the end input D of the second selector connects with the second selector output end QN respectively Connect, first accumulator output the end Q and first adder input terminal connection, the clk input signal respectively with institute The input end CLK for stating the first accumulator is connected with the end input CLK of the second accumulator, the end output Q of second accumulator with The input terminal of the first adder connects, and generates data select signal dsel by frequency-halving circuit, is selected by this data Signal dsel selection is selected successively to be spaced from input frequency word signal din and extract din_1 and din_2；And when postponing one respectively Clock obtains din_1_d signal and din_2_d signal；

The din_1_d signal and the din_2_d signal are connect with the first adder respectively, first addition The output signal of device is connect with the end input D of the third accumulator, and the end output Q of the third accumulator adds with described second The input terminal of musical instruments used in a Buddhist or Taoist mass connects, and the output end of the second adder is connect with the end input D of the 4th accumulator, the mat woven of fine bamboo strips four The output end Q of accumulator is connect with the input terminal of the second adder, the clkdiv2 input signal respectively with the third The input end CLK of accumulator is connected with the end input CLK of the 4th accumulator, and din_1_d is added with din_2_d, is added Result add0 add up under the two divided-frequency clock cycle, obtain accumulated value sum0, din_1 be added with din_2_d, be added Result add1 add up under the two divided-frequency clock cycle, accumulated value sum1 is obtained, by two under the two divided-frequency clock cycle Cumulative obtained accumulated value sum0 and sum1 leads to more third selectors, and successively selection combining is exported at a sum signal to get arriving Complete frequency accumulated value.

In conclusion the beneficial effects of the utility model are: generating data select signal by frequency-halving circuit first dsel；It is successively spaced secondly by dsel selection from input signal din and extracts din_1 and din_2；And postpone one respectively Clock obtains din_1_d signal and din_2_d signal；It is added by din_1_d with din_2_d, the result of addition is in two divided-frequency It adds up under clock cycle；Din_1 is added with din_2_d, and the result of addition adds up under the two divided-frequency clock cycle； Most latter two obtained accumulated value that adds up under the two divided-frequency clock cycle leads to more dsel signals and is merged into a sum signal output, Complete frequency accumulated value is obtained, by way of improving circuit structure rather than improves technique to meet the requirement of design.

Detailed description of the invention

In order to illustrate the embodiment of the utility model or the technical proposal in the existing technology more clearly, below will be to embodiment Needed in attached drawing be briefly described, it should be apparent that, the accompanying drawings in the following description is only the utility model Some embodiments for those of ordinary skill in the art without creative efforts, can also be according to this A little attached drawings obtain other attached drawings.

(a) and (b) figure are to realize high-speed data summation circuit according to a kind of branch of the utility model embodiment in Fig. 1 Way circuit figure；

Fig. 2 is the circuit diagram of frequency accumulator in existing high-speed DDS D/A converting circuit design.

Specific embodiment

The following will be combined with the drawings in the embodiments of the present invention, carries out the technical scheme in the embodiment of the utility model Clearly and completely describe, it is clear that the described embodiments are only a part of the embodiments of the utility model, rather than whole Embodiment.Based on the embodiments of the present invention, those of ordinary skill in the art's every other embodiment obtained, all belongs to In the range of the utility model protection.

Embodiment according to the present utility model provides a kind of branch realization high-speed data summation circuit.

As shown in Figure 1, a kind of branch realizes high-speed data summation circuit, including din input signal, clk clock signal, Clkdiv2 input signal, first selector, the first accumulator, second selector, the second accumulator, first adder, third are tired Add device, second adder, the 4th accumulator and third selector, wherein the first selector, the second selector and institute State third selector and include the input end D, the input end CLK, the output end Q and the output end QN, the din input signal and described the The end input CLK of one selector connects, first accumulator, second accumulator, the third accumulator and described the Four accumulators include the input end D, the input end CLK and the output end Q, the end output Q of the first selector and the input D1 End connection, the first selector input end D connect with the first selector output end QN respectively, first accumulator The end the input D connection of the end Q and second selector is exported, the end input D of the second selector is selected with described second respectively Device exports the input terminal connection of the connection of the end QN, the output end Q of first accumulator and first adder, the clk input Signal is connect with the end input CLK at the input end CLK of first accumulator and the second accumulator respectively, and described second is cumulative The output end Q of device is connect with the input terminal of the first adder, is generated data select signal dsel by frequency-halving circuit, is led to This data select signal dsel selection is crossed successively to be spaced from input frequency word signal din and extract din_1 and din_2；And point Not Yan Chi a clock obtain din_1_d signal and din_2_d signal；

The din_1_d signal and the din_2_d signal are connect with the first adder respectively, first addition The output signal of device is connect with the end input D of the third accumulator, and the end output Q of the third accumulator adds with described second The input terminal of musical instruments used in a Buddhist or Taoist mass connects, and the output end of the second adder is connect with the end input D of the 4th accumulator, and the described 4th The output end Q of accumulator is connect with the input terminal of the second adder, the clkdiv2 input signal respectively with the third The input end CLK of accumulator is connected with the end input CLK of the 4th accumulator, and din_1_d is added with din_2_d, is added Result add0 add up under the two divided-frequency clock cycle, obtain accumulated value sum0, din_1 be added with din_2_d, be added Result add1 add up under the two divided-frequency clock cycle, accumulated value sum1 is obtained, by two under the two divided-frequency clock cycle Cumulative obtained accumulated value sum0 and sum1 leads to more third selectors, and successively selection combining is exported at a sum signal to get arriving Complete frequency accumulated value.

In conclusion the utility model can be by being filled using gear by means of the above-mentioned technical proposal of the utility model The effect of acceleration and the principle of lever force-saving are set, pulls 15 bottom end of sector gear that rubbish box body 2 is made to incline by way of transmission Tiltedly, it to have the function that easy cleaning, avoids cleaner and directly contacts rubbish, ensure that the health of workpeople, activity The use of lid 20 prevents rubbish to give out peculiar smell, and the use of dustbin wheel 18 also makes the utility model facilitate transfer and support Fortune, the utility model structure is simple, easy cleaning, and function is more and practical.

The above is only the preferred embodiment of the utility model only, is not intended to limit the utility model, all at this Within the spirit and principle of utility model, any modification, equivalent replacement, improvement and so on should be included in the utility model Protection scope within.

Claims (1)

1. a kind of branch realizes high-speed data summation circuit, which is characterized in that including din input signal, clk clock signal, Clkdiv2 input signal, first selector, the first accumulator, second selector, the second accumulator, first adder, third are tired Add device, second adder, the 4th accumulator and third selector, wherein the first selector, the second selector and institute State third selector and include the input end D, the input end CLK, the output end Q and the output end QN, the din input signal and described the The end input CLK of one selector connects, first accumulator, second accumulator, the third accumulator and described the Four accumulators include the input end D, the input end CLK and the output end Q, the end output Q of the first selector and the input D1 End connection, the first selector input end D connect with the first selector output end QN respectively, first accumulator The end the input D connection of the end Q and second selector is exported, the end input D of the second selector is selected with described second respectively Device exports the input terminal connection of the connection of the end QN, the output end Q of first accumulator and first adder, the clk input Signal is connect with the end input CLK at the input end CLK of first accumulator and the second accumulator respectively, second accumulator The output end Q connect with the input terminal of the first adder, by frequency-halving circuit generate data select signal dsel, pass through This data select signal dsel selection is successively spaced from input frequency word signal din and extracts din_1 and din_2；And respectively Postpone a clock and obtains din_1_d signal and din_2_d signal；

The din_1_d signal and the din_2_d signal are connect with the first adder respectively, the first adder Output signal is connect with the end input D of the third accumulator, the end output Q of the third accumulator and the second adder Input terminal connection, the output end of the second adder connect with the end input D of the 4th accumulator, and the described 4th adds up The output end Q of device is connect with the input terminal of the second adder, and the clkdiv2 input signal is cumulative with the third respectively The input end CLK of device is connected with the end input CLK of the 4th accumulator, din_1_d is added with din_2_d, the knot of addition Fruit add0 adds up under the two divided-frequency clock cycle, obtains accumulated value sum0, din_1 is added with din_2_d, the knot of addition Fruit add1 adds up under the two divided-frequency clock cycle, obtains accumulated value sum1, and two are added up under the two divided-frequency clock cycle Obtained accumulated value sum0 and sum1 leads to more third selectors, and successively selection combining is complete to get arriving at a sum signal output Frequency accumulated value.