CN110120811A - A kind of branch realization high-speed data summation circuit - Google Patents
A kind of branch realization high-speed data summation circuit Download PDFInfo
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- CN110120811A CN110120811A CN201810115799.7A CN201810115799A CN110120811A CN 110120811 A CN110120811 A CN 110120811A CN 201810115799 A CN201810115799 A CN 201810115799A CN 110120811 A CN110120811 A CN 110120811A
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- 101100063435 Caenorhabditis elegans din-1 gene Proteins 0.000 claims description 10
- 239000000284 extract Substances 0.000 claims description 5
- 101100108191 Vibrio parahaemolyticus serotype O3:K6 (strain RIMD 2210633) add gene Proteins 0.000 claims description 3
- 230000001186 cumulative effect Effects 0.000 claims description 2
- 235000013399 edible fruits Nutrition 0.000 claims 2
- 238000000034 method Methods 0.000 description 5
- 238000005516 engineering process Methods 0.000 description 4
- 230000005611 electricity Effects 0.000 description 2
- 230000009286 beneficial effect Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
Classifications
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
- G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
- G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
- G06F7/57—Arithmetic logic units [ALU], i.e. arrangements or devices for performing two or more of the operations covered by groups G06F7/483 – G06F7/556 or for performing logical operations
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/16—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop
- H03L7/18—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop
- H03L7/1806—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop the frequency divider comprising a phase accumulator generating the frequency divided signal
Abstract
The invention discloses a kind of branches to realize high-speed data summation circuit, including din input signal, clk clock signal, clkdiv2 input signal, first selector, first accumulator, second selector, second accumulator, first adder, third accumulator, second adder, 4th accumulator and third selector, wherein, the first selector, the second selector and the third selector include the input end D, input the end CLK, export the end Q and the output end QN, the din input signal is connect with the end input CLK of the first selector, first accumulator, second accumulator, the third accumulator and the 4th accumulator include the input end D, input the end CLK and the output end Q, the end output Q of the first selector and the end input D1 connect It connects, the first selector input end D is connect with the first selector output end QN respectively, the end input D for exporting the end Q and second selector of first accumulator connects.
Description
Technical field
The present invention relates to circuit design fields, it particularly relates to which a kind of branch realizes high-speed data summation circuit.
Background technique
As shown in Fig. 2, input frequency word din does a sub-addition in each operating clock cycle: tiring out with last
Value added sum does addition；With the increase of frequency word bit wide and the quickening of clock frequency, two are completed within a clock cycle
A addition several greatly will become more and more difficult under existing process conditions, and even without possibility, common practice is exactly to mention
High technology condition provides faster logic unit to realize higher speed.
And under conditions of not improving technique, by the circuit structure design of innovation come in accordance with higher frequency requirement, this
It is a huge challenge.
For the problems in the relevant technologies, currently no effective solution has been proposed.
Summary of the invention
The object of the present invention is to provide a kind of branches to realize high-speed data summation circuit, to overcome existing the relevant technologies institute
Existing above-mentioned technical problem.
The technical scheme is that be achieved:
A kind of branch realization high-speed data summation circuit, including din input signal, clk clock signal, clkdiv2 input
Signal, first selector, the first accumulator, second selector, the second accumulator, first adder, third accumulator, second
Adder, the 4th accumulator and third selector, wherein the first selector, the second selector and third choosing
Selecting device includes the input end D, the input end CLK, the output end Q and the output end QN, the din input signal and the first choice
The end input CLK of device connects, and first accumulator, second accumulator, the third accumulator and the described 4th tire out
Adding device includes the input end D, the input end CLK and the output end Q, and the end output Q of the first selector and the end input D1 connect
Connect, the first selector input end D connect with the first selector output end QN respectively, first accumulator it is defeated
The end Q and the connection of the end input D of second selector, the end input D of the second selector are selected with described second respectively out
Device exports the input terminal connection of the connection of the end QN, the output end Q of first accumulator and first adder, the clk input
Signal is connect with the end input CLK at the input end CLK of first accumulator and the second accumulator respectively, and described second is cumulative
The output end Q of device is connect with the input terminal of the first adder, generates data select signal by above-mentioned frequency-halving circuit
Dsel, by this data select signal dsel selection from input frequency word signal din successively be spaced extract din_1 with
din_2；And postpones a clock respectively and obtain din_1_d signal and din_2_d signal；
The din_1_d signal and the din_2_d signal are connect with the first adder respectively, and described first adds
The output signal of musical instruments used in a Buddhist or Taoist mass is connect with the end input D of the third accumulator, the end output Q of the third accumulator and described the
The input terminal of two adders connects, and the output end of the second adder is connect with the end input D of the 4th accumulator, institute
The output end Q for stating the 4th accumulator is connect with the input terminal of the second adder, the clkdiv2 input signal respectively with
The input end CLK of the third accumulator is connected with the end input CLK of the 4th accumulator, by din_1_d and din_2_d
It is added, the result add0 of addition adds up under the two divided-frequency clock cycle, accumulated value sum0 is obtained, by din_1 and din_2_
D is added, and the result add1 of addition adds up under the two divided-frequency clock cycle, accumulated value sum1 is obtained, by two in two divided-frequency
Add up under clock cycle obtained accumulated value sum0 and sum1 lead to more third selectors successively selection combining at a sum signal
It exports to get complete frequency accumulated value is arrived.
In conclusion the beneficial effects of the present invention are: generating data select signal dsel by frequency-halving circuit first；
It is successively spaced secondly by dsel selection from input signal din and extracts din_1 and din_2；And postpones a clock respectively and obtain
To din_1_d signal and din_2_d signal；It is added by din_1_d with din_2_d, the result of addition is in two divided-frequency clock week
It adds up under phase；Din_1 is added with din_2_d, and the result of addition adds up under the two divided-frequency clock cycle；Last two
A obtained accumulated value that adds up under the two divided-frequency clock cycle leads to more dsel signals and is merged into a sum signal output to get arriving
Complete frequency accumulated value by way of improving circuit structure rather than improves technique to meet the requirement of design.
Detailed description of the invention
It in order to more clearly explain the embodiment of the invention or the technical proposal in the existing technology, below will be in embodiment
Required attached drawing is briefly described, it should be apparent that, the accompanying drawings in the following description is only some realities of the invention
Example is applied, it for those of ordinary skill in the art, without creative efforts, can also be attached according to these
Figure obtains other attached drawings.
Fig. 1 (a) and Fig. 1 (b) is total electricity that a kind of branch according to an embodiment of the present invention realizes high-speed data summation circuit
Lu Tu；
Fig. 2 is the circuit diagram of frequency accumulator in existing high-speed DDS D/A converting circuit design.
Specific embodiment
Following will be combined with the drawings in the embodiments of the present invention, and technical solution in the embodiment of the present invention carries out clear, complete
Site preparation description, it is clear that described embodiments are only a part of the embodiments of the present invention, instead of all the embodiments.It is based on
Embodiment in the present invention, those of ordinary skill in the art's every other embodiment obtained belong to what the present invention protected
Range.
According to an embodiment of the invention, providing a kind of branch realization high-speed data summation circuit.
As shown in Fig. 1 (a) and Fig. 1 (b), a kind of branch realization high-speed data summation circuit, including din input signal,
Clk clock signal, clkdiv2 input signal, first selector, the first accumulator, second selector, the second accumulator, first
Adder, third accumulator, second adder, the 4th accumulator and third selector, wherein the first selector, described
Second selector and the third selector include the input end D, the input end CLK, the output end Q and the output end QN, the din
Input signal is connect with the end input CLK of the first selector, first accumulator, second accumulator, described
Three accumulators and the 4th accumulator include the input end D, the input end CLK and the output end Q, the first selector it is defeated
The end Q is connect with the end input D1 out, and the first selector input end D connects with the first selector output end QN respectively
It connects, the end the input D connection for exporting the end Q and second selector of first accumulator, the input D of the second selector
End connect with the second selector output end QN respectively, first accumulator exports the defeated of the end Q and first adder
Enter end connection, the clk input signal respectively with first accumulator input the end CLK and the second accumulator input CLK
End connection, the output end Q of second accumulator are connect with the input terminal of the first adder, pass through above-mentioned two divided-frequency electricity
Road generates data select signal dsel, is selected from input frequency word signal din successively by this data select signal dsel
Interval extracts din_1 and din_2；And postpones a clock respectively and obtain din_1_d signal and din_2_d signal；
The din_1_d signal and the din_2_d signal are connect with the first adder respectively, and described first adds
The output signal of musical instruments used in a Buddhist or Taoist mass is connect with the end input D of the third accumulator, the end output Q of the third accumulator and described the
The input terminal of two adders connects, and the output end of the second adder is connect with the end input D of the 4th accumulator, institute
The output end Q for stating the 4th accumulator is connect with the input terminal of the second adder, the clkdiv2 input signal respectively with
The input end CLK of the third accumulator is connected with the end input CLK of the 4th accumulator, by din_1_d and din_2_d
It is added, the result add0 of addition adds up under the two divided-frequency clock cycle, accumulated value sum0 is obtained, by din_1 and din_2_
D is added, and the result add1 of addition adds up under the two divided-frequency clock cycle, accumulated value sum1 is obtained, by two in two divided-frequency
Add up under clock cycle obtained accumulated value sum0 and sum1 lead to more third selectors successively selection combining at a sum signal
It exports to get complete frequency accumulated value is arrived.
In conclusion generating data selection letter by frequency-halving circuit first by means of above-mentioned technical proposal of the invention
Number dsel；It is successively spaced secondly by dsel selection from input signal din and extracts din_1 and din_2；And postpone one respectively
A clock obtains din_1_d signal and din_2_d signal；It is added by din_1_d with din_2_d, the result of addition is at two points
Frequency adds up under the clock cycle；Din_1 is added with din_2_d, and the result of addition carries out tired under the two divided-frequency clock cycle
Add；Most latter two obtained accumulated value of adding up under the two divided-frequency clock cycle leads to more dsel signals, and to be merged into a sum signal defeated
Out to get complete frequency accumulated value is arrived, by way of improving circuit structure rather than technique is improved to meet wanting for design
It asks.
The foregoing is merely illustrative of the preferred embodiments of the present invention, is not intended to limit the invention, all in essence of the invention
Within mind and principle, any modification, equivalent replacement, improvement and so on be should all be included in the protection scope of the present invention.
Claims (1)
1. a kind of branch realizes high-speed data summation circuit, which is characterized in that including din input signal, clk clock signal,
Clkdiv2 input signal, first selector, the first accumulator, second selector, the second accumulator, first adder, third are tired
Add device, second adder, the 4th accumulator and third selector, wherein the first selector, the second selector and institute
State third selector and include the input end D, the input end CLK, the output end Q and the output end QN, the din input signal and described the
The end input CLK of one selector connects, first accumulator, second accumulator, the third accumulator and described the
Four accumulators include the input end D, the input end CLK and the output end Q, the end output Q of the first selector and the input D1
End connection, the first selector input end D connect with the first selector output end QN respectively, first accumulator
The end the input D connection of the end Q and second selector is exported, the end input D of the second selector is selected with described second respectively
Device exports the input terminal connection of the connection of the end QN, the output end Q of first accumulator and first adder, the clk input
Signal is connect with the end input CLK at the input end CLK of first accumulator and the second accumulator respectively, second accumulator
The output end Q connect with the input terminal of the first adder, by above-mentioned frequency-halving circuit generate data select signal dsel,
It is successively spaced by this data select signal dsel selection from input frequency word signal din and extracts din_1 and din_2；And
Postpone a clock respectively and obtains din_1_d signal and din_2_d signal；
The din_1_d signal and the din_2_d signal are connect with the first adder respectively, the first adder
Output signal is connect with the end input D of the third accumulator, the end output Q of the third accumulator and the second adder
Input terminal connection, the output end of the second adder connect with the end input D of the 4th accumulator, and the described 4th adds up
The output end Q of device is connect with the input terminal of the second adder, and the clkdiv2 input signal is cumulative with the third respectively
The input end CLK of device is connected with the end input CLK of the 4th accumulator, din_1_d is added with din_2_d, the knot of addition
Fruit add0 adds up under the two divided-frequency clock cycle, obtains accumulated value sum0, din_1 is added with din_2_d, the knot of addition
Fruit add1 adds up under the two divided-frequency clock cycle, obtains accumulated value sum1, and two are added up under the two divided-frequency clock cycle
Obtained accumulated value sum0 and sum1 leads to more third selectors, and successively selection combining is complete to get arriving at a sum signal output
Frequency accumulated value.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201810115799.7A CN110120811A (en) | 2018-02-06 | 2018-02-06 | A kind of branch realization high-speed data summation circuit |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201810115799.7A CN110120811A (en) | 2018-02-06 | 2018-02-06 | A kind of branch realization high-speed data summation circuit |
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| Publication Number | Publication Date |
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| CN110120811A true CN110120811A (en) | 2019-08-13 |
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| CN201810115799.7A Pending CN110120811A (en) | 2018-02-06 | 2018-02-06 | A kind of branch realization high-speed data summation circuit |
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Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1297286A (en) * | 1999-10-29 | 2001-05-30 | 松下电器产业株式会社 | Frequency synthesizer and oscillation frequency controlling method |
| CN107222210A (en) * | 2017-06-07 | 2017-09-29 | 中国电子科技集团公司第二十四研究所 | It is a kind of that the DDS systems of numeric field clock phase can be configured by SPI |
| CN209017016U (en) * | 2018-02-06 | 2019-06-21 | 长沙泰科阳微电子有限公司 | A kind of branch realization high-speed data summation circuit |
-
2018
- 2018-02-06 CN CN201810115799.7A patent/CN110120811A/en active Pending
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1297286A (en) * | 1999-10-29 | 2001-05-30 | 松下电器产业株式会社 | Frequency synthesizer and oscillation frequency controlling method |
| CN107222210A (en) * | 2017-06-07 | 2017-09-29 | 中国电子科技集团公司第二十四研究所 | It is a kind of that the DDS systems of numeric field clock phase can be configured by SPI |
| CN209017016U (en) * | 2018-02-06 | 2019-06-21 | 长沙泰科阳微电子有限公司 | A kind of branch realization high-speed data summation circuit |
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