CN209016061U - A kind of groove-shaped cut-off ring structure of power semiconductor - Google Patents

Abstract

The utility model discloses a kind of groove-shaped cut-off ring structures of power semiconductor.Cut-off ring in cut-off region by being arranged to the structure of double level polysilicon by the structure, the slot type structure of the second polycrystal layer is formed inside the first polysilicon, effectively increase cut-off ring cut-off efficiency, the shortcomings that when each technology being avoided to be used alone, the pressure-resistant efficiency and reduction terminal for improving knot terminal use size and reverse leakage current.It not will increase dramatically design difficulty and cost of manufacture simultaneously.

Description

A kind of groove-shaped cut-off ring structure of power semiconductor

[technical field]

The utility model belongs to semiconductor power device technology field, is related to a kind of groove-shaped cut-off of power semiconductor Ring structure.

[background technique]

It is even more important in addition to needing itself internal each parameter in order to improve the breakdown voltage and job stability of device Be using suitable terminal technology prevent as PN junction be bent and caused by electric field concentration ultimately cause device ahead of time puncture.Example If field limiting ring is exactly using the horizontal proliferation of main knot and ring knot, so that field limiting ring has the function of partial pressure.When being added in main tie When voltage is continuously increased, the depletion region of main knot is also increased with it and is laterally outwardly extended.Before voltage increases to breakdown voltage, The depletion region of main knot and the depletion region of ring knot converge, and two knots are in pass-through state.Main knot is reverse-biased with ring knot shared at this time Voltage, to achieve the purpose that promote device electric breakdown strength.Because the size of all semiconductor devices is all limited, devices use gold Hard rock blade cutting crystal wafer is made into chip to encapsulate, this process can cause lattice seriously to damage.If power device is cut The PN junction for bearing high pressure is had passed through, lattice damage can cause very big leakage current, cause punch through voltage and serious reliability be asked Topic.And the influence of reversed bias voltage is received for the ring knot of outermost, depletion region can be constantly extending transversely outward, it is likely that can expand The position for opening up Wafer Dicing road, gently it will cause integrity problem after scribing process, serious device parameters can be direct Failure.

[utility model content]

The shortcomings that the purpose of the utility model is to overcome the above-mentioned prior arts provides a kind of power semiconductor groove Type ends ring structure.Cut-off ring structure setting can effectively prevent the damage of outer collarette knot, to improve in active area periphery The pressure-resistant efficiency of knot terminal reduces terminal and uses size and reverse leakage current.

In order to achieve the above objectives, the utility model is achieved using following technical scheme:

A kind of groove-shaped cut-off ring structure of power semiconductor, the groove-shaped cut-off ring are arranged in power semiconductor device The cut-off region of part, the groove-shaped cut-off ring includes cricoid second groove, and the inner wall surface of second groove is provided with the first grid Oxide layer, the first gate oxide is interior to be filled with the first polysilicon, and the trench wall surface in the first polysilicon is provided with second gate Oxide layer, the second gate oxide is interior to be filled with the second polysilicon.

Further improvement of the utility model is:

Preferably, power semiconductor includes the cut-off region of N-type lightly doped epitaxial layer, active area and active area periphery； Active area and cut-off region are arranged at the top inside N-type lightly doped epitaxial layer.

Preferably, the bottom of N-type lightly doped epitaxial layer is fixedly installed N-type heavily-doped semiconductor substrate.

Preferably, the upper surface of N-type lightly doped epitaxial layer is covered with isolating oxide layer.

Preferably, the outer edge of isolating oxide layer is provided with cricoid metal electrode.

Preferably, the top of N-type lightly doped epitaxial layer is injected with the main knot of p-type；The upper surface of the main knot of p-type is lightly doped for N-type The upper surface of epitaxial layer.

Preferably, several cricoid first grooves are offered in active area；The inner wall surface of first groove is provided with One gate oxide, the first gate oxide is interior to be filled with the first polysilicon；The two sides outer wall of first groove and the main knot of p-type and N-type are light Doped epitaxial layer contacts.

Preferably, the two sides outer wall of second groove is contacted with the main knot of p-type and N-type lightly doped epitaxial layer.

Preferably, the doping type of the first polysilicon and the second polysilicon, concentration are identical.

Compared with prior art, the utility model has the following beneficial effects:

The utility model discloses a kind of groove-shaped cut-off ring structures of power semiconductor.The structure is by by cut-off region Interior cut-off ring is arranged to the structure of double level polysilicon, and the slot type structure of the second polysilicon is formed inside the first polysilicon, Cut-off ring cut-off efficiency is effectively increased, the shortcomings that when each technology being avoided to be used alone, the pressure-resistant efficiency of knot terminal is improved, reduces eventually End uses size and reverse leakage current；It not will increase dramatically design difficulty and cost of manufacture simultaneously.

[Detailed description of the invention]

Fig. 1 is the sectional view of the semiconductor devices of the utility model；

Wherein: 1-N type heavily-doped semiconductor substrate；2-N type lightly doped epitaxial layer；The first gate oxide of 3-；More than 4- first Crystal silicon；The second gate oxide of 5-；6- active area；7- cut-off region；The second polysilicon of 8-；The main knot of 9-P type；10- isolating oxide layer； 11- metal electrode；12- first groove；13- second groove.

[specific embodiment]

The utility model is described in further detail with reference to the accompanying drawing:

Referring to Fig. 1, the utility model discloses a kind of groove-shaped cut-off ring structures of power semiconductor.The power is partly led Body device includes N-type heavily-doped semiconductor substrate 1 and N-type lightly doped epitaxial layer 2；The surface of N-type lightly doped epitaxial layer 2 is provided with Source region 6 is provided with cut-off region 7 in the periphery of active area 6, is pressure ring between active area 6 and cut-off region 7；Extension is lightly doped in N-type The surface of layer 2 is covered with isolating oxide layer 10；The top of N-type lightly doped epitaxial layer 2 be filled with the main knot 9 of p-type, the main knot 9 of p-type it is upper Surface is contacted with isolating oxide layer 10；The outer ring edge of isolating oxide layer 10 is provided with cricoid metal electrode 11；It is described single Pressure ring is an entirety, and junction termination structures are finally spaced apart by multiple single pressure rings and are formed, can be according to specific Pressure-resistant demand adjust the interval width and quantity of the pressure ring.And the groove-shaped cut-off ring is located at device outermost.

Active area 6 offers several cricoid first grooves 12；Depth direction first groove 12 passes through the main knot 9 of p-type, bottom The outer wall in portion is contacted with N-type lightly doped epitaxial layer 2, transverse direction, and the outer wall and the main knot 9 of p-type and N-type of 12 two sides of first groove are light Doped epitaxial layer 2 contacts；Along laterally laying layer by layer in active area 6, area coverage is gradually increased first groove 12, each The inner wall growth of a first groove 12 has the first gate oxide 3, is filled with the first polysilicon 4 in the first gate oxide 3.

A cricoid second groove 13 is offered in cut-off region 7, depth direction second groove 13 passes through the main knot 9 of p-type, bottom The outer wall in portion is contacted with N-type lightly doped epitaxial layer 2, transverse direction, and the outer wall and the main knot 9 of p-type and N-type of 13 two sides of second groove are light Doped epitaxial layer 2 contacts；The growth of 13 inner wall of second groove has the first gate oxide 3, is filled with first in the first gate oxide 3 Polysilicon 4；Growth has the second gate oxide 5 in first polysilicon 4, is filled with the second polysilicon 8 in the second gate oxide 5；The Two grooves 13 and its first gate oxide 3, the first polysilicon 4, the second gate oxide 5 and the common structure of the second polysilicon 8 of inside At cut-off ring.

The top of the two sides outer wall of first groove 12 and second groove 13 is contacted with the main knot 9 of p-type, the lower part of two sides outer wall And bottom is contacted with N-type lightly doped epitaxial layer 2.

First polysilicon 4 is identical with the doping type of the second polysilicon 8, concentration；But adulterated in the two and the main knot 9 of p-type from Subtype is opposite.

The semiconductor devices it is groove-shaped cut-off ring structure preparation process the following steps are included:

Step 1, prepare epitaxial slice structure, the epitaxial slice structure includes that N-type heavily-doped semiconductor substrate 1 and N-type are gently mixed Miscellaneous epitaxial layer 2；

Step 2, several first grooves 12 and cut-off in active area 6 are formed in the upper surface of N-type lightly doped epitaxial layer 2 A second groove 13 in area 7；

Step 3, one layer of gate oxide, first groove are grown in all trench interiors and 2 surface of N-type lightly doped epitaxial layer 12 and 13 inner wall of second groove grow the first gate oxide 3；

Step 4, the first polysilicon 4 of n-type doping is filled in all grooves；

Step 5, first polysilicon 4 at 2 top of N-type lightly doped epitaxial layer is removed with the mode of etching；

Step 6, groove is formed inside the first polysilicon 4 in second groove 13；

Step 7, through mode of oxidizing inside 2 surface of N-type lightly doped epitaxial layer of cut-off region 7 and second groove 13 One layer of gate oxide is grown, grows the second gate oxide 5 on the trench wall surface of first polysilicon 4 in second groove 13；

Step 8, the second polysilicon 8 of n-type doping is filled in the second gate oxide 5；

Step 9, second polysilicon at 2 top of N-type lightly doped epitaxial layer of cut-off region 7 is removed with the mode of etching；

Step 10, the main knot 9 of p-type is partially formed inside N-type lightly doped epitaxial layer 2 by ion implanting, then led to Cross annealing process activation doped chemical；

Step 11, one layer of isolating oxide layer is formed on 2 surface of N-type lightly doped epitaxial layer with the mode of deposit silica 10；

Step 12, metal electrode 11 is formed by sputtering mode to draw the main knot 9 of p-type.

Since the utility model provides a kind of groove-shaped cut-off ring structure of power semiconductor.Therefore for device function Energy area is not detailed.Processing step involved in the utility model can be formed together while forming device functional areas, because This is without increasing process costs.Ultimately form peripheral structure diagrammatic cross-section as shown in Figure 1.

The above is only the preferred embodiment of the utility model only, is not intended to limit the utility model, all at this Within the spirit and principle of utility model, any modification, equivalent replacement, improvement and so on should be included in the utility model Protection scope within.

Claims (9)

1. a kind of groove-shaped cut-off ring structure of power semiconductor, which is characterized in that the groove-shaped cut-off ring is arranged in function The cut-off region (7) of rate semiconductor devices, the groove-shaped cut-off ring includes cricoid second groove (13), second groove (13) Inner wall surface is provided with the first gate oxide (3), is filled with the first polysilicon (4) in the first gate oxide (3), the first polysilicon (4) the trench wall surface in is provided with the second gate oxide (5), and the second polysilicon is filled in the second gate oxide (5) (8)。

2. the groove-shaped cut-off ring structure of a kind of power semiconductor according to claim 1, which is characterized in that power half Conductor device includes the cut-off region (7) of N-type lightly doped epitaxial layer (2), active area (6) and active area (6) periphery；Active area (6) The internal top of N-type lightly doped epitaxial layer (2) is arranged at cut-off region (7).

3. the groove-shaped cut-off ring structure of a kind of power semiconductor according to claim 2, which is characterized in that N-type is light The bottom of doped epitaxial layer (2) is fixedly installed N-type heavily-doped semiconductor substrate (1).

4. the groove-shaped cut-off ring structure of a kind of power semiconductor according to claim 2, which is characterized in that N-type is light The upper surface of doped epitaxial layer (2) is covered with isolating oxide layer (10).

5. the groove-shaped cut-off ring structure of a kind of power semiconductor according to claim 4, which is characterized in that isolation from oxygen The outer edge for changing layer (10) is provided with cricoid metal electrode (11).

6. a kind of groove-shaped cut-off ring structure of power semiconductor, feature according to claim 2-5 any one It is, the top of N-type lightly doped epitaxial layer (2) is injected with the main knot (9) of p-type；The upper surface of the main knot (9) of p-type is outside N-type is lightly doped Prolong the upper surface of layer (2).

7. the groove-shaped cut-off ring structure of a kind of power semiconductor according to claim 6, which is characterized in that active area (6) several cricoid first grooves (12) are offered in；The inner wall surface of first groove (12) is provided with the first gate oxide (3), the first polysilicon (4) are filled in the first gate oxide (3)；The two sides outer wall of first groove (12) and the main knot (9) of p-type and N-type lightly doped epitaxial layer (2) contacts.

8. the groove-shaped cut-off ring structure of a kind of power semiconductor according to claim 6, which is characterized in that the second ditch The two sides outer wall of slot (13) is contacted with the main knot (9) of p-type and N-type lightly doped epitaxial layer (2).

9. the groove-shaped cut-off ring structure of a kind of power semiconductor according to claim 1, which is characterized in that more than first Crystal silicon (4) is identical with the doping type of the second polysilicon (8), concentration.