CN208986921U - A kind of synchronization system applied to multi-channel high-speed digital analog converter - Google Patents
A kind of synchronization system applied to multi-channel high-speed digital analog converter Download PDFInfo
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- CN208986921U CN208986921U CN201821850326.3U CN201821850326U CN208986921U CN 208986921 U CN208986921 U CN 208986921U CN 201821850326 U CN201821850326 U CN 201821850326U CN 208986921 U CN208986921 U CN 208986921U
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- 210000001367 artery Anatomy 0.000 claims abstract description 15
- 210000003462 vein Anatomy 0.000 claims abstract description 15
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Abstract
The utility model discloses a kind of synchronization systems applied to multi-channel high-speed digital analog converter, including coarse tuning circuit: receiving the feedback clock that synchronised clock, the high-frequency clock of DAC kernel and high-frequency clock frequency dividing generate；Arteries and veins is gulped down treated high-frequency clock to the transmission of delay circuit input terminal；Or；Reset signal is issued to trimming circuit, and transmits high-frequency clock to delay circuit input terminal；Trimming circuit: reset signal, trimming circuit starting are received；Synchronised clock and feedback clock are received, to delay circuit control terminal transmission delay amount；Delay circuit: reception gulps down arteries and veins treated high-frequency clock, to the transmission of DAC kernel according to the high-frequency clock after presetting amount of delay delay process；Or；High-frequency clock is received, the high-frequency clock after transmitting the amount of delay delay process transmitted according to trimming circuit to DAC kernel.The utility model is aligned by the feedback clock after frequency dividing with synchronised clock, realizes the synchronization of all device clock logic states, and then realize the synchronization of multichannel.
Description
Technical field
The utility model relates to a kind of synchronization systems for being applied to multi-channel high-speed digital analog converter (DAC), belong to high speed
Hybrid digital-analog integrated circuit technical field.
Background technique
In a communications system, it usually needs use monolithic multichannel DAC or multi-disc single channel (or multichannel) DAC, channel
Between matching and stationary problem it is most important.Interchannel matches usually for the analog portion in multiple DAC,
It can reduce this partial mismatch using static shift correction technology.But as crossed the synchronization it cannot be guaranteed that multiple DAC data load moment, i.e.,
Just the analog portion exact matching of DAC, the phase of DAC output signal will not be identical.In this way, cannot guarantee multichannel DAC
The synchronization of output signal.
The data load moment of DAC depends on used clock, corresponding high-speed DAC system, since internal data loads
The clock of register has clock state machine, and multichannel DAC is synchronous other than guaranteeing the matching of above-mentioned analog portion, also to handle
The problem of numeric field, i.e. the state synchronized problem of clock state machine.
Utility model content
The utility model provides a kind of synchronization system applied to multi-channel high-speed digital analog converter, solves existing
Multichannel DAC system is existing only to synchronize master clock, cannot achieve the stationary problem of DAC internal clocking state machine.
In order to solve the above-mentioned technical problem, the technical scheme adopted by the utility model is
A kind of synchronization system applied to multi-channel high-speed digital analog converter, including coarse tuning circuit, trimming circuit and delay
Circuit；
Coarse tuning circuit:
Receive the feedback clock that synchronised clock, the high-frequency clock of DAC kernel and high-frequency clock frequency dividing generate；
Arteries and veins is gulped down treated high-frequency clock to the transmission of delay circuit input terminal；Or；Reset signal is issued to trimming circuit,
And high-frequency clock is transmitted to delay circuit input terminal；
Trimming circuit:
Receive reset signal, trimming circuit starting；
Synchronised clock and feedback clock are received, to delay circuit control terminal transmission delay amount；
Delay circuit:
Reception gulps down arteries and veins treated high-frequency clock, to the transmission of DAC kernel according to the high speed after presetting amount of delay delay process
Clock；
Or；
High-frequency clock is received, when high speed after the amount of delay delay process transmitted to the transmission of DAC kernel according to trimming circuit
Clock.
Coarse tuning circuit includes phase discriminator and swallow pulse generator；
The input terminal input synchronised clock and feedback clock of phase discriminator, the output end connection swallow pulse generator of phase discriminator
Input terminal, high-frequency clock input the input terminal of swallow pulse generator, the output end connection delay circuit input of swallow pulse generator
End and trimming circuit the RESET input.
Swallow pulse generator include trigger DFF1, trigger DFF2, NAND gate and with door；
The output end of the end the D connection phase discriminator of trigger DFF1, the clock end of trigger DFF1 input high-frequency clock, and non-
Two input terminals of door are separately connected the output end of phase discriminator and the end Q of trigger DFF1, and the output end of NAND gate connects triggering
The end D of device DFF1, the clock end of trigger DFF2 input high-frequency clock, and the end the Q connection trimming circuit of trigger DFF2 resets defeated
Enter end, an input terminal of the end the Q connection and door of trigger DFF2 inputs high-frequency clock with another input terminal of door, with door
Output end connects delay circuit input terminal.
Trimming circuit includes TDC and logic controller；
The input terminal input synchronised clock and feedback clock of TDC, the RESET input of TDC connect coarse tuning circuit, and TDC's is defeated
Outlet connects the input terminal of logic controller, the control terminal of the output end connection delay circuit of logic controller.
Logic controller is Approach by inchmeal logic controller.
Synchronised clock is benchmark clock, is provided by outside or DAC is provided.
Delay circuit is programmable delay control unit.
The utility model is achieved the utility model has the advantages that 1, the utility model passes through the feedback clock and synchronised clock after frequency dividing
Alignment realizes the synchronization of all device clock logic states, and then realizes the synchronization of multichannel；2, the existing coarse adjustment of the utility model
Also there is fine tuning, different synchronization accuracy and synchronization time can be configured, it is flexible to use comparison；3, the application of TDC in finely tuning,
Directly will difference information quantify, overcome in conventional phase locked loops synchronization scheme locking time is slow, synchronization accuracy it is limited lack
Point.
Detailed description of the invention
Fig. 1 is the structural schematic diagram of the utility model；
Fig. 2 is logic control process.
Specific embodiment
The utility model is further described with reference to the accompanying drawing.Following embodiment is only used for clearly illustrating this
The technical solution of utility model, and cannot be used as a limitation the limitation protection scope of the utility model.
A kind of synchronization system applied to multi-channel high-speed digital analog converter, including coarse tuning circuit, trimming circuit and delay
Circuit.
Coarse tuning circuit:
The feedback clock that synchronised clock, the high-frequency clock of DAC kernel and high-frequency clock frequency dividing generate is received, wherein when synchronous
Clock is benchmark clock, is provided by outside or DAC is provided；
Arteries and veins is gulped down treated high-frequency clock to the transmission of delay circuit input terminal；Or；Reset signal is issued to trimming circuit,
And high-frequency clock is transmitted to delay circuit input terminal.
Specific work process are as follows:
Coarse tuning circuit identification synchronised clock is differed with feedback clock；
In response to a cycle for differing by more than high-frequency clock of synchronised clock and feedback clock, when coarse tuning circuit is to high speed
Clock gulp down arteries and veins processing, and will gulp down arteries and veins treated that high-frequency clock is transferred to delay circuit；
In response to being not much different in a cycle of high-frequency clock for synchronised clock and feedback clock, coarse tuning circuit is to fine tuning
Circuit issues reset signal, and high-frequency clock is transferred to delay circuit by coarse tuning circuit.
Trimming circuit:
Receive reset signal, trimming circuit starting；Synchronised clock and feedback clock are received, is transmitted to delay circuit control terminal
Amount of delay.
Specific work process are as follows:
Trimming circuit receives synchronised clock and feedback clock, quantifies to synchronised clock with differing for feedback clock, root
According to the result computation delay amount of quantization；Amount of delay is transferred to delay circuit by trimming circuit.
Delay circuit:
Reception gulps down arteries and veins treated high-frequency clock, to the transmission of DAC kernel according to the high speed after presetting amount of delay delay process
Clock；
Or；
High-frequency clock is received, when high speed after the amount of delay delay process transmitted to the transmission of DAC kernel according to trimming circuit
Clock.
Specific work process are as follows:
Arteries and veins is gulped down treated high-frequency clock in response to receiving, delay circuit is delayed to it according to preset amount of delay
Processing, and the high-frequency clock after delay process is transferred to DAC kernel；
In response to receiving high-frequency clock, delay circuit carries out at delay it according to the amount of delay that trimming circuit transmits
Reason, and the high-frequency clock after delay process is transferred to DAC kernel.
Specific circuit structure is as shown in Figure 1, wherein coarse tuning circuit includes phase discriminator and swallow pulse generator, fine tuning electricity
Road includes TDC (time-to-digit converter) and logic controller.
Coarse tuning circuit connection structure is as follows: the input terminal of phase discriminator input synchronised clock and feedback clock, phase discriminator it is defeated
Outlet connects the input terminal of swallow pulse generator, and high-frequency clock inputs the input terminal of swallow pulse generator, swallow pulse generator
Output end connects delay circuit input terminal and trimming circuit the RESET input.
Impulse generator include trigger DFF1, trigger DFF2, NAND gate and with door；The end D of trigger DFF1 connects
The clock end of the output end of phase discriminator, trigger DFF1 inputs high-frequency clock, and two input terminals of NAND gate are separately connected phase demodulation
The output end of device and the end Q of trigger DFF1, NAND gate output end connection trigger DFF1 the end D, trigger DFF2 when
Clock end inputs high-frequency clock, and the end Q connection trimming circuit the RESET input of trigger DFF2 (exports to trimming circuit and resets letter
Number), an input terminal of the end the Q connection and door of trigger DFF2 inputs high-frequency clock with another input terminal of door, defeated with door
Outlet connects delay circuit input terminal.
Trimming circuit connection structure is as follows: the input terminal input synchronised clock and feedback clock of TDC, the reset input of TDC
End connection coarse tuning circuit (i.e. the end Q of trigger DFF2 receives reset signal), the output end of TDC connects the defeated of logic controller
Enter end, the control terminal of the output end connection delay circuit of logic controller exports the amount of delay for calculating and obtaining to delay circuit.
Logic controller is Approach by inchmeal logic controller, has been internally integrated a state of a control machine, according to setting in advance
The algorithm of meter, the amount of delay of accurately controlling clock, specific logic control are as shown in Figure 2.
The output TDC [n-1:0] (expression TDC signal is n BITBUS network, the common literary style in this field) of TDC connects logic controller,
The output TDC_Q [n-1:0] of logic controller connects the control terminal of delay circuit.By taking n=16 as an example, TDC_Q's [15:0] is initial
Value is set as 0x00FFH, and system judges the value of TDC [15:0], if it is 0x00FFH, when illustrating synchronised clock and feedback
Difference very little between clock, within the precision of TDC, trimming circuit locking.If the value of TDC [15:0] is greater than 0x00FFH,
Logic controller control TDC_Q [15:0] moves to right, (if TDC_Q until the value of TDC [15:0] is less than or equal to 0x00FFH
When [15:0] is 0x0000H, the value of TDC [15:0] is also greater than 0x00FFH, then trimming circuit locking failure)；, whereas if TDC
The value of [15:0] is less than 0x00FFH, then logic controller control TDC_Q [15:0] moves to left, until the value of TDC [15:0] is greater than
(if TDC_Q [15:0] is 0xFFFFH, the value of TDC [15:0] is also less than 0x00FFH, then finely tunes electricity until equal to 0x00FFH
Road locking failure).
Delay circuit is programmable delay control unit.
The course of work of above system is as follows:
Phase discriminator identify synchronised clock and feedback clock differ whether greater than high-frequency clock a cycle, if more than,
Swallow pulse generator gulps down arteries and veins processing to high-frequency clock disengaging, and to gulping down arteries and veins treated, high-frequency clock carries out at delay delay circuit
Reason, and the high-frequency clock after delay process is transferred to DAC kernel；Trimming circuit does not work in this process, delay process
Amount of delay be preset definite value.
After repeatedly gulping down arteries and veins delay process, it is not much different in a cycle of high-frequency clock, swallow pulse generator does not gulp down arteries and veins, gulps down
Impulse generator issues reset signal (this is a wake-up signal, and TDC is made to work) to TDC, and swallow pulse generator is by high rapid pulse
Punching is transferred directly to delay circuit, and TDC quantifies synchronised clock with differing for feedback clock with thermometer-code, logic control
The hot code that device is exported according to TDC, according to the algorithm being pre-designed, computation delay amount, delay circuit is transmitted according to logic controller
Amount of delay delay process is carried out to high-frequency clock, and the high-frequency clock after delay process is transferred to DAC kernel.
Above system is aligned by the feedback clock after frequency dividing with synchronised clock, realizes all device clock logic states
It is synchronous, and then realize the synchronization of multichannel.The existing coarse adjustment of above system also has fine tuning, can configure different synchronization accuracy and same
The time is walked, it is flexible to use comparison.The application of TDC in above system fine tuning, difference information is directly quantified, overcome
The disadvantage that locking time is slow in conventional phase locked loops synchronization scheme, synchronization accuracy is limited.
The above is only the preferred embodiment of the utility model, it is noted that for the common skill of the art
For art personnel, without deviating from the technical principle of the utility model, several improvement and deformations can also be made, these change
It also should be regarded as the protection scope of the utility model into deformation.
Claims (7)
1. a kind of synchronization system applied to multi-channel high-speed digital analog converter, it is characterised in that: including coarse tuning circuit, fine tuning electricity
Road and delay circuit；
Coarse tuning circuit:
Receive the feedback clock that synchronised clock, the high-frequency clock of DAC kernel and high-frequency clock frequency dividing generate；
Arteries and veins is gulped down treated high-frequency clock to the transmission of delay circuit input terminal；Or；To trimming circuit sending reset signal, and to
Delay circuit input terminal transmits high-frequency clock；
Trimming circuit:
Receive reset signal, trimming circuit starting；
Synchronised clock and feedback clock are received, to delay circuit control terminal transmission delay amount；
Delay circuit:
Reception gulps down arteries and veins treated high-frequency clock, to the transmission of DAC kernel according to the high-frequency clock after presetting amount of delay delay process；
Or；
High-frequency clock is received, the high-frequency clock after transmitting the amount of delay delay process transmitted according to trimming circuit to DAC kernel.
2. a kind of synchronization system applied to multi-channel high-speed digital analog converter according to claim 1, it is characterised in that:
Coarse tuning circuit includes phase discriminator and swallow pulse generator；
The input terminal input synchronised clock and feedback clock of phase discriminator, the input of the output end connection swallow pulse generator of phase discriminator
End, high-frequency clock input swallow pulse generator input terminal, swallow pulse generator output end connection delay circuit input terminal and
Trimming circuit the RESET input.
3. a kind of synchronization system applied to multi-channel high-speed digital analog converter according to claim 2, it is characterised in that:
Swallow pulse generator include trigger DFF1, trigger DFF2, NAND gate and with door；
The output end of the end the D connection phase discriminator of trigger DFF1, the clock end of trigger DFF1 input high-frequency clock, NAND gate
Two input terminals are separately connected the output end and trigger DFF1 of phase discriminatorThe output end at end, NAND gate connects trigger
The clock end at the end D of DFF1, trigger DFF2 inputs high-frequency clock, trigger DFF2'sEnd connection trimming circuit resets input
End, an input terminal of the end the Q connection and door of trigger DFF2 input high-frequency clock with another input terminal of door, defeated with door
Outlet connects delay circuit input terminal.
4. a kind of synchronization system applied to multi-channel high-speed digital analog converter according to claim 1, it is characterised in that:
Trimming circuit includes TDC and logic controller；
The input terminal input synchronised clock and feedback clock of TDC, the RESET input of TDC connect coarse tuning circuit, the output end of TDC
Connect the input terminal of logic controller, the control terminal of the output end connection delay circuit of logic controller.
5. a kind of synchronization system applied to multi-channel high-speed digital analog converter according to claim 4, it is characterised in that:
Logic controller is Approach by inchmeal logic controller.
6. a kind of synchronization system applied to multi-channel high-speed digital analog converter according to claim 1, it is characterised in that:
Synchronised clock is benchmark clock, is provided by outside or DAC is provided.
7. a kind of synchronization system applied to multi-channel high-speed digital analog converter according to claim 1, it is characterised in that:
Delay circuit is programmable delay circuit.
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201821850326.3U CN208986921U (en) | 2018-11-12 | 2018-11-12 | A kind of synchronization system applied to multi-channel high-speed digital analog converter |
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| Application Number | Priority Date | Filing Date | Title |
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| CN201821850326.3U CN208986921U (en) | 2018-11-12 | 2018-11-12 | A kind of synchronization system applied to multi-channel high-speed digital analog converter |
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| CN208986921U true CN208986921U (en) | 2019-06-14 |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109194334A (en) * | 2018-11-12 | 2019-01-11 | 苏州云芯微电子科技有限公司 | A kind of synchronization system applied to multi-channel high-speed digital analog converter |
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2018
- 2018-11-12 CN CN201821850326.3U patent/CN208986921U/en not_active Withdrawn - After Issue
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109194334A (en) * | 2018-11-12 | 2019-01-11 | 苏州云芯微电子科技有限公司 | A kind of synchronization system applied to multi-channel high-speed digital analog converter |
| CN109194334B (en) * | 2018-11-12 | 2024-01-23 | 苏州云芯微电子科技有限公司 | Synchronous system applied to multichannel high-speed digital-to-analog converter |
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