CN109947030A - The method in dynamic following EtherCat bus synchronous period in servo internal control period - Google Patents
The method in dynamic following EtherCat bus synchronous period in servo internal control period Download PDFInfo
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- CN109947030A CN109947030A CN201910292890.0A CN201910292890A CN109947030A CN 109947030 A CN109947030 A CN 109947030A CN 201910292890 A CN201910292890 A CN 201910292890A CN 109947030 A CN109947030 A CN 109947030A
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- G—PHYSICS
- G05—CONTROLLING; REGULATING
- G05B—CONTROL OR REGULATING SYSTEMS IN GENERAL; FUNCTIONAL ELEMENTS OF SUCH SYSTEMS; MONITORING OR TESTING ARRANGEMENTS FOR SUCH SYSTEMS OR ELEMENTS
- G05B19/00—Programme-control systems
- G05B19/02—Programme-control systems electric
- G05B19/04—Programme control other than numerical control, i.e. in sequence controllers or logic controllers
- G05B19/042—Programme control other than numerical control, i.e. in sequence controllers or logic controllers using digital processors
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04J—MULTIPLEX COMMUNICATION
- H04J3/00—Time-division multiplex systems
- H04J3/02—Details
- H04J3/06—Synchronising arrangements
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Abstract
A kind of method in servo internal control period dynamic following EtherCat bus synchronous period of disclosure of the invention.Note servo internal control cycle time is T, and EtherCat bus synchronous cycle time is Tesync.If n × T is greater than the EtherCat bus cycles, force to generate servo internal control periodic signal in advance, to keep synchronous with bus synchronous periodic signal；If on the contrary, n × T is less than the EtherCat bus synchronous period, even if the time point that should then generate servo internal control signal arrives, also it does not generate, but bus synchronous signal is waited to arrive, once arriving, the last one servo internal control periodic signal is generated immediately, to keep synchronous with bus synchronous periodic signal.Each later EtherCat bus synchronous period is equally handled all in accordance with mentioned above principle.The present invention uses servo internal control periodic signal and the dynamic adjustment of bus synchronous periodic signal to eliminate in a manner of dynamic error, and the error caused by eliminating because of the inherent variability between non-homogeneous clock between synchronization signal maintains the final synchronization of slave stations at different levels.
Description
Technical field
The present invention relates to a kind of methods of EtherCat bus synchronous period dynamic alignment error, are especially,
The method in EtherCat dynamic following EtherCat bus synchronous period in bus-type servo internal control period, belongs to servo motor
Control field.
Background technique
Currently, EtherCat bus-type servo-driver, the synchronization signal of bus by host computer due to being handled and leading to
The influence of content size is interrogated, the EtherCat bus synchronous period is commonly greater than the servo internal control period.What we were usually taken
Method is to set the Integer n (n >=1) times that the EtherCat bus synchronous period is the servo internal control period.Such as, of the invention to test
Card platform sets the EtherCat bus synchronous period as 2ms, and the servo internal control period is 125us, i.e., each EtherCat is total
Have 16 servo internal control periods in line synch period, and 16 in section of each EtherCat bus synchronous cycle time
The servo internal control period is that oneself is generated according to local clock, non-since local clock and bus clock are non-homogeneous clock
There are inherent variabilities for homologous clock, thus the servo internal control periodic signal that generates of this local clock the last one (the
16) and EtherCat bus synchronous periodic signal between be certain to generate error.
Existing general framework is that the bus synchronous signal that EtherCat slave station generates is transferred to programmable logic device
(FPGA/CPLD), programmable logic device (FPGA/CPLD) can generate servo internal control period letter according to oneself internal clocking
Number give algorithm processor unit, and can according in the bus synchronous signal correction EtherCat bus synchronous period the last one watch
The generation time point for taking internal control periodic signal is allowed to arrive point unanimously with EtherCat bus synchronous periodic signal, that is, exists
The last one servo internal control period concentrates forced synchronism.Also have without programmable logic device (FPGA/CPLD),
But the bus synchronous signal that slave station chip comes out is directly connected on MCU, but principle is the same, it is all by bus synchronous week
Phase signal concentrates forced synchronism servo internal control periodic signal.
In the prior art, the method for eliminating above-mentioned error is:
As shown in Fig. 2, if servo internal control period for generating of local clock when being totally slower than the EtherCat bus synchronous period,
The last one (the 16th servo internal control week in servo internal control period of meeting within an EtherCat bus synchronous period
Phase) on when showing as EtherCat bus synchronous periodic signal Δ T more early than the servo internal control periodic signal that should be generated
Between arrive, this when, force in advance generate servo internal control periodic signal, with keep with the EtehrCat bus synchronous period
The synchronization of signal, each later EtehrCat bus synchronous period is equally to handle.As a result it shows as, each EtehrCat
In the bus synchronous period, the last one servo internal control period is all shorter than other servo internal control periods, repeats,
The phenomenon will not passage at any time and eliminate, servo performance can be had an impact.
As shown in figure 4, if when the locally generated servo internal control period is totally faster than the EtherCat bus synchronous period,
The last one (the 16th servo internal control week in servo internal control period of meeting within an EtherCat bus synchronous period
Phase) on when showing as EtherCat bus synchronous periodic signal Δ T more late than the servo internal control periodic signal that should be generated
Between arrive, this when, even if the time point that slave station should generate the last one servo internal control periodic signal arrives, also not
It generates, but EtherCat bus synchronous periodic signal is waited to arrive, once arriving, generate control inside the last one servo immediately
Periodic signal processed is to keep synchronous with EtherCat bus synchronous periodic signal, each EtherCat bus synchronous is all later
Phase is all equally to handle, and is as a result shown as, in each EtherCat bus synchronous period, the last one servo internal control period
It is all longer than other servo internal control periods, repeat, the phenomenon will not passage at any time and eliminate, can be to servo
It can have an impact.
Summary of the invention
The technical problems to be solved by the invention are to overcome defect of the existing technology, propose in a kind of servo
The method in portion's control period dynamic following EtherCat bus synchronous period.Its basic ideas is: error is uniformly broken up down
A cycle then further according to the error of next cycle, then uniformly breaks up down the next period, iterates, follow always,
It is eliminated with the dynamic error during reaching bus synchronous period and servo internal control week.
The present invention is a kind of method in servo internal control period dynamic following EtherCat bus synchronous period, step
It is:
Servo receives EtherCat instruction, and completes distribution clock function, generates the periodic EtherCat bus synchronous period
Signal is synchronized in multinode (slave station) system for whole system for the periodic synchronization servo internal control period
EtherCat bus.
The bus synchronous periodic signal that EtherCat slave station restores to generate is transferred to programmable logic device (such as FPGA/
CPLD), programmable logic device (FPGA/CPLD) generates servo internal control periodic signal signal to algorithm according to local clock
Processor unit, the frequency of usual servo internal control periodic signal are the integral multiple of bus synchronous periodic signal frequency, are denoted as n
(n≥1)；It that is: include n servo internal control period in an EtherCat bus synchronous period.Remember each servo internal control
Cycle time is T, and EtherCat bus synchronous cycle time is Tesync.Ideally, an EtherCat bus is same
Step period should be for the sum of n servo internal control period i.e.: Tesync=n × T.Each slave station is generated using respective local clock
Servo internal control periodic signal, the internal control period generated due to the no doubt presence of non-homogeneous clock jitter, local clock
T can not fully meet Tesync=n × T relationship with EtherCat bus synchronous cycle T esync.
If n × T is greater than the EtherCat bus synchronous period, Tesync-n × T=- Δ T is remembered, then: at first
The EtherCat bus synchronous period is shown as on the last one servo internal control period in the EtherCat bus synchronous period
Signal Δ T time more early than the last one the servo internal control periodic signal that should be generated arrives, at this point, forcing to generate in advance
Servo internal control periodic signal, to keep synchronous with EtherCat bus synchronous periodic signal；But in next EtherCat
In the bus synchronous period, the time in each servo internal control period is adjusted to T- Δ T/n；Each later EtherCat is total
Line synch period is all equally handled.Performance results are as follows: dynamic eliminates error, adjusts in real time, makes servo internal control periodic signal
Substantially it is consistent with bus synchronous signal, once there is error, i.e., is eliminated within next bus cycles.
If n × T is less than the EtherCat bus synchronous period, Tesync-n × T=Δ T is remembered, then: at first
The EtherCat bus synchronous period is shown as on the last one servo internal control period in the EtherCat bus synchronous period
Signal Δ T time more late than the last one the servo internal control periodic signal that should be generated arrives, at this point, even if inside should
The time point for generating servo internal control periodic signal arrives, and does not also generate, but bus synchronous signal is waited to arrive, once it arrives
Come, generates the last one servo internal control periodic signal immediately to keep same with EtherCat bus synchronous periodic signal
Step；But within next EtherCat bus synchronous period, each servo internal control cycle time is adjusted to T+ Δ T/n；
Each later EtherCat bus synchronous period is equally to handle.Performance results are as follows: dynamic eliminates error, adjusts in real time,
It is consistent servo internal control periodic signal with bus synchronous periodic signal substantially, once there is error, i.e., next total
It is eliminated in line synch period.
Error is uniformly broken up next cycle by the method for the present invention, is iterated, and is followed always, and dynamic corrections reach
Dynamic error during EtherCat bus synchronous period and servo internal control week is eliminated.The method of the present invention is applied drives in servo
In dynamic device, integrates servo internal control period generation counter and control the feelings that motor PWM generation counter is a counter
Under condition, fully synchronized servo internal control period and PWM generate the period, and the control for being more conducive to servo motor is steady.
Detailed description of the invention
Fig. 1 is servo structure of the embodiment of the present invention and synchronization signal connection schematic diagram.
Fig. 2 is in the prior art, when being totally slower than the EtherCat bus synchronous period in the servo internal control period, to disappear
Except the processing mode schematic diagram of error.
Fig. 3 are as follows: when the sum of n servo internal control period n × T is greater than in an EtherCat bus synchronous period
The method of the present invention Error processing schematic diagram when the EtherCat bus synchronous period.
Fig. 4 is in the prior art, when being totally faster than the EtherCat bus synchronous period in the servo internal control period, to eliminate
Error processing schematic diagram.
Fig. 5 are as follows: when the sum of n servo internal control period n × T is less than in an EtherCat bus synchronous period
The method of the present invention Error processing schematic diagram when the EtherCat bus synchronous period.
Specific embodiment
The present invention is described in further detail below in conjunction with the accompanying drawings.
As shown in Figure 1, the method for the present invention is mainly realized in programmable logic device FPGA, servo receives EtherCat and refers to
It enables, and completes distribution clock function, then can generate bus synchronous periodic signal, for periodic synchronization servo internal control week
Phase is synchronized with EtherCat bus for whole system in multinode (slave station) system.Verification platform we set one
EtherCat bus synchronous cycle T esync is 2ms, and the servo internal control period is T=125us, i.e., each EtherCat bus
N=16 servo internal control the period is had in synchronizing cycle, and the servo internal control period in this period is oneself root
It is generated according to local clock, and the servo internal control periodic signal of this local clock generation and EtherCat bus synchronous period
It is certain to generate error delta T.
Existing general framework is that the bus synchronous signal that EtherCat slave station generates is transferred to programmable logic device
(FPGA/CPLD), programmable logic device (FPGA/CPLD) can generate servo internal control period letter according to oneself internal clocking
Number algorithm processor unit is given, and can be according to EtherCat bus synchronous periodic signal revised version EtherCat bus synchronous week
The generation time point of the last one servo internal control periodic signal in phase makes to generate time point and bus synchronous periodic signal is raw
It is consistent at point.Also have without FPGA/CPLD, but the bus synchronous signal that slave station chip comes out is directly connected on MCU
, but principle is the same, is all by bus synchronous periodic signal come forced synchronism servo internal control periodic signal.
Fig. 3 is table when being totally slower than the EtherCat bus synchronous period in the servo internal control period that local clock generates
Now arrive for bus synchronous periodic signal earlier than the servo internal control periodic signal Δ T time that should be generated, side of the present invention
Method can be on the last one servo internal control period within first EtherCat bus synchronous period (inside the 16th servo
Control the period) it forces to generate servo internal control periodic signal in advance, to keep synchronous with bus synchronous signal, but simultaneously can
It writes down this time point and the error delta T between time point of the last one servo internal control periodic signal should be generated,
Within next EtherCat bus synchronous period, the time that the adjustment servo internal control period generates is T- Δ T/16.After
Each EtherCat bus synchronous period is equally to handle.Performance results are as follows: dynamic eliminates error, adjusts in real time, makes to watch
Internal control periodic signal is taken to be consistent with bus synchronous periodic signal substantially, once there is error, i.e., it is same in next bus
It is eliminated in step period.
When the servo internal control period that Fig. 5 local clock generates totally is faster than the EtherCat bus synchronous period, performance
The servo internal control periodic signal Δ T that being later than for bus synchronous periodic signal should generate arrives, processing mode of the present invention
It is: for the first time, even if the internal time point that should generate servo internal control signal arrives, does not also generate, but wait
EtherCat bus synchronous periodic signal arrives, once arriving, generates the last one (the 16th) servo internal control week immediately
Phase signal to keep synchronous with EtherCat bus synchronous periodic signal, while being write down this time point and should be generated
Error delta T between the time point of the last one servo internal control periodic signal, in next EtherCat bus synchronous week
In phase, the time that adjustment servo internal control periodic signal generates is T+ Δ T/16.Each later period is equally to handle,
Performance results are as follows: dynamic eliminates error, adjusts in real time, keeps servo internal control periodic signal with bus synchronous signal substantially
Unanimously, it once there is error, i.e., is eliminated within next bus cycles.
Verifying of the invention is realized in FPGA, and specific method is two sets of counters, a set of to be used to monitor EtherCat
In the bus synchronous period, another is used to generate servo internal control periodic signal.The generation of servo internal control periodic signal is adopted
Method is decimally divided, period computing module is only needed to provide the cycle value that generate internal control periodic signal, it can be accurate
Generation synchronization signal.Fractional frequency division method itself is also a kind of method for eliminating cumulative errors, is also very suitable for being applied to FPGA
It realizes.Period computing module only need to calculate error, compensation according to the bus synchronous period of monitoring and the internal control period of generation
In the period that each servo internal control periodic signal in next bus synchronous period generates.
The present invention applies in servo-driver, integrates servo internal control period generation counter and control motor PWM
In the case where counter is generated as a counter, fully synchronized servo internal control period and PWM generate the period, advantageously
It is steady in the control of servo motor.
The above is only a preferred embodiment of the present invention, it is noted that for the ordinary skill people of the art
For member, several improvement can also be made without departing from the principle of the present invention, these improvement also should be regarded as of the invention
Protection scope.
Claims (1)
1. a kind of method in servo internal control period dynamic following EtherCat bus synchronous period, the steps include:
Servo receives EtherCat instruction, and completes distribution clock function, generates periodic bus synchronous signal, for regular
The synchronous servo internal control period is synchronized with EtherCat bus for whole system in multi-node system；
The bus synchronous periodic signal that EtherCat slave station restores to generate is transferred to programmable logic device, programmable logic device
Servo internal control periodic signal, which is generated, according to oneself internal clocking gives algorithm processor unit, the frequency in servo internal control period
Rate is the integral multiple of bus synchronous period frequency, is denoted as n, n >=1, it may be assumed that includes n servo in an EtherCat bus cycles
Control the period；Remember that each servo internal control cycle time is T, EtherCat bus synchronous cycle time is Tesync；
If n × T is greater than the EtherCat bus synchronous period, Tesync-n × T=- Δ T is remembered, then: pressure generates servo in advance
Internal control periodic signal, to keep synchronous with bus synchronous periodic signal；But it, will be each within next bus synchronous period
Servo internal control cycle time is adjusted to T- Δ T/n；
If n × T is less than the EtherCat bus cycles, Tesync-n × T=Δ T is remembered, then: even if control inside servo should be generated
The time point of periodic signal processed arrives, and does not also generate this servo internal control periodic signal, but waits bus synchronous signal, and one
Denier bus synchronous signal arrives, and generates the last one servo internal control periodic signal immediately, to keep and bus synchronous signal
Synchronization；But within next bus synchronous period, each servo internal control cycle time is adjusted to T+ Δ T/n；
Each later EtherCat bus synchronous period is equally handled all in accordance with mentioned above principle.
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201910292890.0A CN109947030A (en) | 2019-04-12 | 2019-04-12 | The method in dynamic following EtherCat bus synchronous period in servo internal control period |
| PCT/CN2019/087247 WO2020206808A1 (en) | 2019-04-12 | 2019-05-16 | Method for enabling servo internal control cycle to dynamically follow ethercat bus synchronization cycle |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201910292890.0A CN109947030A (en) | 2019-04-12 | 2019-04-12 | The method in dynamic following EtherCat bus synchronous period in servo internal control period |
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| CN109947030A true CN109947030A (en) | 2019-06-28 |
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| CN201910292890.0A Pending CN109947030A (en) | 2019-04-12 | 2019-04-12 | The method in dynamic following EtherCat bus synchronous period in servo internal control period |
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| WO (1) | WO2020206808A1 (en) |
Cited By (5)
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|---|---|---|---|---|
| CN111381539A (en) * | 2020-03-18 | 2020-07-07 | 深圳市小步数控有限公司 | Bus real-time synchronous control device |
| CN111552325A (en) * | 2020-04-28 | 2020-08-18 | 深圳易能电气技术股份有限公司 | Position instruction synchronization method, device and computer readable storage medium |
| CN111953469A (en) * | 2020-07-21 | 2020-11-17 | 季华实验室 | Method and device for synchronizing servo driver and Ethercat DC clock and electronic equipment |
| CN112115079A (en) * | 2020-08-19 | 2020-12-22 | 苏州伟创电气科技股份有限公司 | Method and system for bus cycle synchronization |
| CN114679249A (en) * | 2022-05-26 | 2022-06-28 | 深圳市杰美康机电有限公司 | EtherCAT communication synchronization method and device |
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Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN111381539A (en) * | 2020-03-18 | 2020-07-07 | 深圳市小步数控有限公司 | Bus real-time synchronous control device |
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| CN114679249A (en) * | 2022-05-26 | 2022-06-28 | 深圳市杰美康机电有限公司 | EtherCAT communication synchronization method and device |
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| WO2020206808A1 (en) | 2020-10-15 |
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Application publication date: 20190628 |