CN105245304B - A kind of method for synchronizing time of double mainboard structure intelligent substation emulation regulating and measuring systems - Google Patents
A kind of method for synchronizing time of double mainboard structure intelligent substation emulation regulating and measuring systems Download PDFInfo
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Abstract
A kind of method for synchronizing time of double mainboard structure intelligent substation emulation regulating and measuring systems, it includes the following steps：Select clock synchronisation source：It determines clock synchronous reference source, and selects clock synchronisation source from clock synchronous reference source；Generation time synchronization message：Obtain time synchronization source information and generation time synchronization message；Carry out time synchronization：Time synchronization message distribution is subjected to time synchronization to each unit.The present invention ensure that the accuracy for obtaining clock source by selecting suitable clock synchronous reference source；Take full advantage of the steady characteristic of length in time synchronization source and the short steady characteristic of OCXO, the available high steady clock of generation system with it is synchronous, used for each unit in device systems is unified；It realizes to the time synchronization using two mainboard structure intelligent substation emulation and regulating and measuring system, solves time synchronization problem existing for existing double mainboard dual-system devices.
Description
Technical field
The present invention relates to a kind of method for synchronizing time, specifically a kind of double mainboard structure intelligent substations emulate commissioning
The method for synchronizing time of system, belongs to power system automation technology field.
Background technology
State Grid Corporation of China's intelligent grid just strong in all-round construction in recent years, that is, build using extra-high voltage grid as backbone
Rack, electric network coordination at different levels development sturdy power grid, and realize the informationization of power grid, digitlization, automation, interactive.Network
The normal work of intelligent node and the performance of effect be unable to do without unified the whole network time reference.As intelligent substation is once set
Standby, comprehensive intelligent use of secondary device etc., precision and stabilization to the time propose harsher requirement.
With the development of intelligent substation, the integrated level of station equipment is also higher and higher, some are in digital transformer substation
A secondary device be incorporated into together, be developed into intelligent primary equipment；To be had a single function there are also equipment supplier and
Relevant secondary device has been incorporated into together, is existed in the form of double mainboard dual systems even more mainboard multisystems；In standing
The convenience of staff, the interior common tool in some stations have also obtained the integration of function, such as the emulation platform of intelligent substation
With intelligent substation regulating and measuring system.The Time synchronization technique of intelligent substation has reached its maturity, and interior each smart machine of standing can also obtain
Accurate clock source is taken, but for the equipment of double mainboards, dual system, how realized using two mainboards or two systems
The time synchronization of one equipment becomes urgent problem to be solved instantly.
Invention content
In order to overcome the deficiencies of the above existing technologies, the present invention provides a kind of double mainboard structure intelligent substations to emulate
The method for synchronizing time of regulating and measuring system can realize two mainboards or the time of two systems of one equipment of intelligent substation
It is synchronous, and the clock source accuracy obtained is high.
The technical scheme adopted by the invention to solve the technical problem is that：A kind of double mainboard structure intelligent substation emulation tune
The method for synchronizing time of examining system, characterized in that include the following steps：
Select clock synchronisation source：It determines clock synchronous reference source, and selects clock synchronisation source from clock synchronous reference source；
Generation time synchronization message：Obtain time synchronization source information and generation time synchronization message；
Carry out time synchronization：Time synchronization message distribution is subjected to time synchronization to each unit.
Preferably, it is described select the detailed process of clock synchronisation source for：Clock synchronous reference source is from synchronous with GPS time
The clock synchronous reference source that device generates, based on the instruction information that each road clock synchronous reference source is sent out, while with hardware
Performance statistic is assisted, that optimal road clock synchronous reference source of final choice is clock synchronisation source.
Preferably, the generation time synchronization message process includes the following steps：Using constant-temperature crystal oscillator (OCXO,
Oven Controlled Crystal Oscillator) follow the reference PP1S signals of selected clock synchronisation source output；With ginseng
It on the basis of examining PP1S signal rising edges, is counted using 61.44MHz clocks, and measures 61.44MHz clocks and generate locally
PP1S signals and the phase count with reference to PP1S signal rising edges are poor；Being filtered by sliding window algorithm makes local PP1S signals
It is locked with the dynamic of phase is realized with reference to PP1S signals；Generate by the clock that is uniformly used for each unit in system with it is synchronous
The time synchronization message of composition.
Preferably, the progress time synchronization process includes the following steps：Star will be used between each unit and system MCU
Type structure connects, and each unit designs one group of synchronization code stream and synchronised clock and connects the active and standby MCU of system simultaneously, active and standby
The synchronization code stream and synchronised clock of MCU outputs determine main output MCU in the enterprising line of System Backplane and logical process, only main defeated
Synchronous code stream and synchronised clock could be exported by going out MCU, another MCU forbids exporting；Main output MCU is by clock after synthesis and same
Step generates synchronous code stream and system clock and is distributed together to each unit in system, and it is same that each unit in system carries out the time
Step.
Preferably, active and standby MCU determines main output MCU by the way of competition into line and logical process.
Further, which further includes the delay compensation process of clock synchronisation source, to clock synchronization
The circuit delay of Zhong Tongbucankaoyuan compensates.
Preferably, clock synchronous reference source includes the IRIG-B codes source that GPS time synchronizer generates；The clock is same
The delay compensation process in step source includes the delay compensation process to GPS antenna feeders, and the delay compensation process to GPS antenna feeders passes through
Configuration receiver realizes that specific offset is calculated or is set as default factory value 180ns according to antenna feeder length scene.
Preferably, clock synchronous reference source includes IEEE 1588V2 band internal clocks source；The clock synchronisation source when
It includes IEE 1588V2 with the circuit delay compensation process under internal synchronization mode to prolong compensation process；To IEE 1588V2 with interior synchronization
Circuit delay compensation under mode is compensated using 1588 adjustment algorithms.
Preferably, the delay compensation process of the clock synchronisation source includes the delay compensation process of external sync cap, right
The offset of the delay compensation of external sync cap is determined according to live synchronizing cable length, is passed through after setting compensation value and is configured
CPLD realizes delay compensation.
Beneficial effects of the present invention are as follows：
The present invention first determine clock synchronous reference source, and to clock synchronous reference source carry out quality evaluation therefrom select when
Clock synchronisation source not only can select suitable clock synchronous reference source, and ensure that the accuracy for obtaining clock source；So
Time synchronization source information and generation time synchronization message are obtained afterwards, make full use of that the steady characteristic of the length in time synchronization source and OCXO's is short
Steady characteristic, the available high steady clock of generation system with it is synchronous, used for each unit in device systems is unified；It is finally that the time is same
It walks message distribution and carries out time synchronization to each unit.The present invention is realized to being emulated using two mainboard structure intelligent substations
With the time synchronization of regulating and measuring system, solves time synchronization problem existing for existing double mainboard dual-system devices.
In order to obtain more accurate time synchronization source information, the present invention also carries out the circuit delay in clock synchronous reference source
Compensation, it is ensured that the reference PP1S signals absolute synchronization as far as possible of clock synchronisation source output is avoided because of originals such as circuit delay
Because generating excessive simultaneous bias, precision is kept to reach higher clock by more precisely compensating for.
Description of the drawings
The following further describes the present invention with reference to the drawings：
Fig. 1 is the structure diagram of substation simulation and regulating and measuring system；
Fig. 2 is flow chart of the method for the present invention；
Fig. 3 is the signal topological diagram of substation simulation code stream synchronous with regulating and measuring system and synchronised clock；
Fig. 4 is the structure chart that star-like connection is used between MCU and the TPI interfaces of each unit.
Fig. 5 is the method flow diagram when present invention carries out clock synchronisation source delay compensation.
Specific implementation mode
In order to clarify the technical characteristics of the invention, below by specific implementation mode, and its attached drawing is combined, to this hair
It is bright to be described in detail.Following disclosure provides many different embodiments or example is used for realizing the different knots of the present invention
Structure.In order to simplify disclosure of the invention, hereinafter the component of specific examples and setting are described.In addition, the present invention can be with
Repeat reference numerals and/or letter in different examples.This repetition is that for purposes of simplicity and clarity, itself is not indicated
Relationship between various embodiments and/or setting is discussed.It should be noted that illustrated component is not necessarily to scale in the accompanying drawings
It draws.Present invention omits the descriptions to known assemblies and treatment technology and process to avoid the present invention is unnecessarily limiting.
As shown in Figures 1 to 4, the time synchronization of a kind of double mainboard structure intelligent substation emulation regulating and measuring systems of the invention
Method, the intelligent substation emulation regulating and measuring system include the intelligent substation for being tested/emulating, primary emulation mainboard and commissioning
Mainboard, intelligent substation, primary emulation mainboard and commissioning mainboard two are two interconnected.It the described method comprises the following steps：
Select clock synchronisation source：Clock synchronous reference source from the clock synchronous reference source generated with GPS time synchronizer,
It based on the instruction information that each road clock synchronous reference source is sent out, while being assisted with the performance statistic of hardware, most
It is clock synchronisation source to select that optimal road clock synchronous reference source eventually.It not only can select suitable clock synchronous reference
Source, and ensure that the accuracy for obtaining clock source, the present invention is in specific implementation process, clock synchronous reference under default situations
Source uses IRIG-B codes source.
Generation time synchronization message：Utilize constant-temperature crystal oscillator (OCXO, Oven Controlled Crystal
Oscillator the reference PP1S signals of selected clock synchronisation source output) are followed；With reference on the basis of PP1S signal rising edges, to adopt
It is counted with 61.44MHz clocks, and measures 61.44MHz clocks and generate local PP1S signals and refer to PP1S signal rising edges
Phase count it is poor；The dynamic for making local PP1S signals with realizing phase with reference to PP1S signals is filtered by sliding window algorithm
Locking；Generate by the clock that is uniformly used for each unit in system with synchronize the time synchronization message that forms.It makes full use of
The steady characteristic of length in time synchronization source and the short steady characteristic of OCXO, the available high steady clock of generation system with it is synchronous, for equipment system
The unified use of each unit in system.
Carry out time synchronization：By TPI (the Time Processing Interface Unit, markers processing of each unit
And interface unit) connect using hub-and-spoke configuration between the active and standby MCU of system, each TPI design one group of synchronization code stream with it is synchronous
Clock and the active and standby MCU for connecting system simultaneously, the synchronization code stream and synchronised clock of active and standby MCU outputs are in the enterprising line of System Backplane
Determine that main output MCU, only main output MCU could export synchronous code stream and synchronised clock with logical process, another MCU forbids
Output；Main output MCU by after synthesis clock and the synchronous synchronization code stream that generates be distributed together to each in system with system clock
A unit, each unit in system carry out time synchronization.Active and standby MCU is determined by the way of competition into line and logical process
Go out main output MCU.It realizes to the time synchronization using two mainboard structure intelligent substation emulation and regulating and measuring system, solves
Time synchronization problem existing for existing double mainboard dual-system devices.
As shown in figure 5, in order to obtain more accurate time synchronization source information, line of the present invention also to clock synchronous reference source
Road delay is compensated.Include the following steps using to the method for synchronizing time after clock synchronisation source progress delay compensation：
Select clock synchronisation source：Clock synchronous reference source from the clock synchronous reference source generated with GPS time synchronizer,
It based on the instruction information that each road clock synchronous reference source is sent out, while being assisted with the performance statistic of hardware, most
It is clock synchronisation source to select that optimal road clock synchronous reference source eventually.It not only can select suitable clock synchronous reference
Source, and ensure that the accuracy for obtaining clock source, the present invention is in specific implementation process, clock synchronous reference under default situations
Source uses IRIG-B codes source.
The delay compensation of clock synchronisation source：It is compensated to the circuit delay to clock synchronous reference source.
Generation time synchronization message：Utilize constant-temperature crystal oscillator (OCXO, Oven Controlled Crystal
Oscillator the reference PP1S signals of selected clock synchronisation source output) are followed；With reference on the basis of PP1S signal rising edges, to adopt
It is counted with 61.44MHz clocks, and measures 61.44MHz clocks and generate local PP1S signals and refer to PP1S signal rising edges
Phase count it is poor；The dynamic for making local PP1S signals with realizing phase with reference to PP1S signals is filtered by sliding window algorithm
Locking；Generate by the clock that is uniformly used for each unit in system with synchronize the time synchronization message that forms.It makes full use of
The steady characteristic of length in time synchronization source and the short steady characteristic of OCXO, the available high steady clock of generation system with it is synchronous, for equipment system
The unified use of each unit in system.
Carry out time synchronization：Hub-and-spoke configuration will be used to connect between each unit and system MCU, each unit designs one
The synchronous code stream of group and synchronised clock and the active and standby MCU for connecting system simultaneously, the synchronization code stream and synchronised clock of active and standby MCU outputs exist
The enterprising line of System Backplane and logical process determine main output MCU, only main output MCU could export synchronous code stream with it is synchronous when
Clock, another MCU forbid exporting；Main output MCU by after synthesis clock and the synchronous synchronization code stream that generates together with system clock
The each unit being distributed in system, each unit in system carry out time synchronization.Active and standby MCU is carried out by the way of competition
Line determines main output MCU with logical process.It realizes to using two mainboard structure intelligent substation emulation and regulating and measuring system
Time synchronization, solve time synchronization problem existing for existing double mainboard dual-system devices.
Preferably, the IRIG-B codes source of GPS time synchronizer generation may be used in clock synchronous reference source.If adopted
The IRIG-B codes source generated with GPS time synchronizer, then carry out delay compensation to GPS antenna feeders, and the time delay to GPS antenna feeders is mended
Process is repaid by configuration receiver to realize, specific offset is calculated or is set as giving tacit consent to according to antenna feeder length scene
Factory value 180ns.
Preferably, clock synchronous reference source can also use IEEE 1588V2 band internal clocks source.If using IEEE
1588V2 band internal clocks source, then using 1588 adjustment algorithms come to carrying out IEE 1588V2 with the circuit time delay under internal synchronization mode
Compensation.
Preferably, the delay compensation process of the clock synchronisation source includes the delay compensation process of external sync cap, right
The offset of the delay compensation of external sync cap is determined according to live synchronizing cable length, is passed through after setting compensation value and is configured
CPLD realizes delay compensation.
It is compensated by the circuit delay to clock synchronisation source, it is ensured that the reference PP1S signals of clock synchronisation source output
Absolute synchronization as far as possible is avoided because the reasons such as circuit delay generate excessive simultaneous bias, by more precisely compensating for reach
Precision is kept to higher clock.
The above is the preferred embodiment of the present invention, for those skilled in the art,
Without departing from the principles of the invention, several improvements and modifications can also be made, these improvements and modifications are also regarded as this hair
Bright protection domain.
Claims (7)
1. a kind of method for synchronizing time of double mainboard structure intelligent substation emulation regulating and measuring systems, characterized in that including following step
Suddenly：
Select clock synchronisation source：It determines clock synchronous reference source, and selects clock synchronisation source from clock synchronous reference source；
Generation time synchronization message：Obtain time synchronization source information and generation time synchronization message；
Carry out time synchronization：Time synchronization message distribution is subjected to time synchronization to each unit；
The progress time synchronization process includes the following steps：Hub-and-spoke configuration will be used to connect between each unit and system MCU,
Each unit designs one group of synchronization code stream and synchronised clock and connects the active and standby MCU of system simultaneously, the synchronization of active and standby MCU outputs
Code stream and synchronised clock determine that main output MCU, only main output MCU could be exported in the enterprising line of System Backplane and logical process
Synchronous code stream and synchronised clock, another MCU forbid exporting；It is main output MCU by after synthesis synchronization code stream and synchronised clock with
System clock is distributed together to each unit in system, and each unit in system carries out time synchronization；Active and standby MCU is using competing
The mode striven determines main output MCU into line and logical process.
2. a kind of method for synchronizing time of double mainboard structure intelligent substation emulation regulating and measuring systems according to claim 1,
It is characterized in that it is described select the detailed process of clock synchronisation source for：Clock synchronous reference source comes from the generation of GPS time synchronizer
Clock synchronous reference source, based on the instruction information that each road clock synchronous reference source is sent out, at the same with the performance of hardware unite
It counts and is assisted, that optimal road clock synchronous reference source of final choice is clock synchronisation source.
3. a kind of method for synchronizing time of double mainboard structure intelligent substation emulation regulating and measuring systems according to claim 1,
It is characterized in that the generation time synchronization message process includes the following steps：Selected clock is followed using constant-temperature crystal oscillator
The reference PP1S signals of synchronisation source output；With reference on the basis of PP1S signal rising edges, to be counted using 61.44MHz clocks,
And the phase count for measuring 61.44MHz clocks generation local PP1S signals and reference PP1S signal rising edges is poor；It is calculated by sliding window
Method, which is filtered, makes local PP1S signals be locked with the dynamic of phase is realized with reference to PP1S signals；It generates for each in system
The time synchronization message for synchronization code stream and the synchronised clock composition that unit uniformly uses.
4. a kind of double mainboard structure intelligent substations emulation regulating and measuring systems according to claims 1 to 3 any one when
Between synchronous method, characterized in that further include the delay compensation process of clock synchronisation source, to the circuit to clock synchronous reference source
Delay compensates.
5. a kind of method for synchronizing time of double mainboard structure intelligent substation emulation regulating and measuring systems according to claim 4,
It is characterized in that clock synchronous reference source includes the IRIG-B codes source that GPS time synchronizer generates；The clock synchronisation source
Delay compensation process includes the delay compensation process to GPS antenna feeders, and the delay compensation process to GPS antenna feeders is connect by configuring
Receipts machine realizes that specific offset is calculated or is set as default factory value according to antenna feeder length scene.
6. a kind of method for synchronizing time of double mainboard structure intelligent substation emulation regulating and measuring systems according to claim 4,
It is characterized in that clock synchronous reference source includes IEEE 1588V2 band internal clocks source；The delay compensation of the clock synchronisation source
Process includes IEEE 1588V2 with the circuit delay compensation process under internal synchronization mode；To IEEE 1588V2 band internal synchronization modes
Under circuit delay compensation compensated using 1588 adjustment algorithms.
7. a kind of method for synchronizing time of double mainboard structure intelligent substation emulation regulating and measuring systems according to claim 5,
It is characterized in that the delay compensation process of the clock synchronisation source includes the delay compensation process of external sync cap, to external same
The offset of delay compensation for walking interface determines according to live synchronizing cable length, after setting compensation value by configure CPLD come
Realize delay compensation.
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| CN112650719A (en) * | 2019-10-12 | 2021-04-13 | 中国石油化工股份有限公司 | Method and system for synchronous acquisition and data recording of earthquake |
| CN115347970B (en) * | 2022-08-17 | 2023-12-01 | 南方电网科学研究院有限责任公司 | Clock synchronization method, device and equipment of electric power real-time simulation system |
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| CN1794619A (en) * | 2004-12-23 | 2006-06-28 | 阿尔卡特公司 | Redundant synchronous clock distribution system |
| CN101848076A (en) * | 2010-05-10 | 2010-09-29 | 新邮通信设备有限公司 | Clock signal holding method and device |
| CN103513569A (en) * | 2013-09-17 | 2014-01-15 | 国家电网公司 | Method for synchronizing redundant time of intelligent substation |
| EP2709298A1 (en) * | 2012-09-18 | 2014-03-19 | Omicron electronics GmbH | Synchronization method and electronic apparatus using redundant links |
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| CN101197650B (en) * | 2007-11-21 | 2012-11-07 | 上海华为技术有限公司 | Clock synchronization device and method |
| CN103248445B (en) * | 2012-02-09 | 2018-01-05 | 中兴通讯股份有限公司 | A kind of clock synchronizing method and device |
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| CN1794619A (en) * | 2004-12-23 | 2006-06-28 | 阿尔卡特公司 | Redundant synchronous clock distribution system |
| CN101848076A (en) * | 2010-05-10 | 2010-09-29 | 新邮通信设备有限公司 | Clock signal holding method and device |
| EP2709298A1 (en) * | 2012-09-18 | 2014-03-19 | Omicron electronics GmbH | Synchronization method and electronic apparatus using redundant links |
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Denomination of invention: A time synchronization method of a dual-board structure intelligent substation simulation commissioning system Effective date of registration: 20220812 Granted publication date: 20181023 Pledgee: Industrial and Commercial Bank of China Co., Ltd. Jinan High-tech Sub-branch Pledgor: Shandong Wangcong Information Technology Co.,Ltd. Registration number: Y2022980012403 |
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Date of cancellation: 20231204 Granted publication date: 20181023 Pledgee: Industrial and Commercial Bank of China Co.,Ltd. Jinan High tech Sub branch Pledgor: Shandong Wangcong Information Technology Co.,Ltd. Registration number: Y2022980012403 |