CN208985151U - One kind being based on the cascade SSI data acquisition circuit of shift register - Google Patents
One kind being based on the cascade SSI data acquisition circuit of shift register Download PDFInfo
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- CN208985151U CN208985151U CN201821452606.9U CN201821452606U CN208985151U CN 208985151 U CN208985151 U CN 208985151U CN 201821452606 U CN201821452606 U CN 201821452606U CN 208985151 U CN208985151 U CN 208985151U
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
- Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management
Abstract
The utility model relates to data acquisition technology fields, it is especially a kind of to be based on the cascade SSI data acquisition circuit of shift register, it is single-ended with differential conversion chips, m piece n bit shift register chip, master controller, SSI module including 2, wherein it is a piece of it is single-ended the single-ended clock signal of master controller is converted into SSI module with differential conversion chip needed for differential clock signal；Another single-ended the differential data signals of SSI module are converted into shift register with differential conversion chip needed for single ended signal；The m piece n bit shift register chip cascade forms m*n bit shift register circuit, and m*n SSI serial datas are converted into m*n bit parallel data.The utility model has the advantages that solving, SSI data acquisition occupancy cpu resource is more, execution cycle is long, speed is slow, power consumption is big, control logic is complicated, required component is not easy the problems such as obtaining, is at high cost, control circuit is designed using general-purpose device, realizes the acquisition of SSI data in simple, efficient, economic, reliable method.
Description
Technical field
The utility model relates to data acquisition technology fields, especially a kind of to be based on the cascade SSI data of shift register
Acquisition Circuit.
Background technique
The one kind of encoder as sensor is mainly used to detect speed, position, angle, distance or the meter of mechanical movement
Number, has obtained widely answering in all kinds of automation control areas such as radar, robot, numerically-controlled machine tool and high accuracy servo system
With.High Precision Absolute Encoder that is domestic at present and producing in the world mostly uses Serial output, and the most commonly used is SSI
Interface.SSI interface has the advantages that transmission speed is fast, installation cost is few, route is simplified, it only pass through two signals (clock and
Data) serial mode transmit, and clock and data-signal are all made of differential mode transmission, and signal transmission is accurate, resists dry
It is strong to disturb ability, is suitble to long distance transmission, thus is more and more widely used on the encoder.
Since encoder is to the commonly used of SSI interface, there have been SSI data collection problems, currently, single-chip microcontroller,
The common controller of the industrial control fields such as DSP, PC104, industrial personal computer does not provide SSI interface generally, in the market common SSI converter
Traffic rate is low, price is high, not easy to install, this outer encoder producer does not provide interface convertor generally, these factors are certain
The application of SSI encoder is limited in degree.Currently used SSI collecting method is mainly include the following types: one, serial letter
Number directly acquisition: implementation method is after SSI differential signal to be converted to single-ended signal or asynchronous serial signal, to be conveyed directly to
CPU, CPU are using the SSI interface or asynchronous serial port serial received data simulated, and real-time operation is handled, and this acquisition method accounts for
More with cpu resource, execution cycle is long, and speed is slow, causes CPU power consumption big；Two, parallel port module is turned using SSI interface: domestic at present
Common a module is SSI208P, which exports SSI data conversion at 8 bit parallel datas, is conveyed directly to CPU, most
Height can acquire 32 data, and point 4 output, timing transmission to CPU, CPU receives data for 4 times again and merges processing, this
Component needed for kind acquisition method is not easy to obtain, and higher cost, and the palpus Time-sharing control when acquisition digit is more occupies CPU money
Source is more, and control logic is complicated, and execution cycle is long, and speed is slow, causes CPU power consumption big；Three, using CPLD chip self-developing
SSI interface turns parallel port circuit: implementation method is based on CPLD chip, and design SSI interface turns parallel port circuit, by SSI data
8 bit parallel datas are converted into, are then handled by the reception mode of method two, or are converted into the identical digit of encoder
Parallel data is directly passed in parallel to CPU and handles immediately, and this acquisition method is at high cost, and the development cycle is long, and development difficulty is big, wind
Danger is high.
Utility model content
Technical problem to be solved by the utility model is: in order to solve SSI data acquisition following problems, one, directly string
Row acquisition occupancy cpu resource is more, and execution cycle is long, and speed is slow, causes CPU power consumption big；Two, needed for SSI interface string turns and acquires
Component is not easy to obtain, and higher cost, and the palpus Time-sharing control when acquisition digit is more, occupancy cpu resource is more, control logic
Complexity, execution cycle is long, and speed is slow, causes CPU power consumption big；Three, self-developing SSI converting interface is at high cost, and the development cycle is long, opens
Degree of raising difficult questions is big, and risk is high；The utility model provides a kind of based on the cascade SSI data acquisition circuit of shift register, including 2
Piece is single-ended with differential conversion chip, m piece n bit shift register chip, master controller and SSI module, it is one it is single-ended with
Differential clock signal CLOCK+ needed for the single-ended clock signal SCK of master controller is converted into SSI module by differential conversion chip,
CLOCK- is sent to SSI module clock pin；It is described another it is single-ended with differential conversion chip by the differential data signals of SSI module
Single ended signal needed for DATA+, DATA- are converted into shift register is sent to the serial input terminal of shift register chip；
The m piece n bit shift register chip cascade forms m*n bit shift register circuit, and m*n SSI serial datas are converted into
M*n bit parallel data uses common general-purpose device directly by the m*n I/O mouthfuls of technical solutions read parallel of master controller
Control circuit is designed, solves SSI data collection problems in simple, efficient, economic, reliable method.
The technical scheme adopted by the utility model to solve the technical problem is as follows: a kind of cascade based on shift register
SSI data acquisition circuit, including 2 it is single-ended with differential conversion chip, m piece n bit shift register chip, master controller and
The single-ended clock signal of master controller is converted into needed for SSI module by SSI module, one single-ended and differential conversion chip
Differential clock signal is sent to SSI module clock pin；It is described another it is single-ended with differential conversion chip by the difference number of SSI module
It is believed that single ended signal needed for number being converted into shift register is sent to the serial input terminal of shift register chip；The m
Piece n bit shift register chip cascade forms m*n bit shift register circuit, and m*n SSI serial datas are converted into m*n
Parallel data is directly read by m*n I/O mouthfuls of master controller parallel.
Specifically, the shift register chip is 8 bit shift register chips, cascade quantity is 4.Such design,
The component for being easy to obtain can be used, the circuit of simple economy realizes the highly effective gathering to 32 SSI data.I/O mouthfuls after extension
Quantity determined by actual demand, be not limited to 32.
Specifically, described single-ended and differential conversion chip model is SN65176, wherein a piece of single-ended and differential conversion chip
Pin 4 connects master controller and simulates clock out pin, and pin 6,7 is connected respectively to the clock pins 1,2 of SSI module；It is another
The single-ended data signal port pin 3,4 that SSI module is connected respectively to differential conversion chip pin 6,7 of piece, pin 1 is connected to
The serial data input pin 14 of first shift register chip.SN65176 can be by meeting this circuit design requirements
Other model congenerous chips substitution.
Specifically, four shift register chip models are 74HC595, shift clock pin 11 is connected to master control
Device clock pins processed, resetting pin 10 are connected to master controller and reset port pinout, and latch clock pin 12 is connected to main control
The latch clock of device passes through cascade data output pin 9 and serial data input pin 14 between four shift registers
It connects two-by-two, pin 15,1,2,3,4,5,6,7 is parallel data delivery outlet, 32 parallel-by-bit numbers of four shift register chips
The I/O mouth of master controller is consecutively connected to according to output.The selection of shift register chip according to practical I/O mouthfuls of extension demand and
It is fixed, appropriate model congenerous chip can be used.
Specifically, the model C8051F020 or C8051F022 of master controller.Master controller selection is converted with SSI serial ports
The quantity of parallel port is related afterwards, and model, type are unlimited, it may include all with certain amount, (of the present invention 32 be this typical case
The typical usage of circuit) I/O mouthfuls single-chip microcontroller, the microprocessors such as ARM, DSP, FPGA.
Specifically, 2 single-ended are positive with differential conversion chip, 48 bit shift register chip power supply voltages
5V.Depending on the selection of this voltage is required according to chip, it is not limited only to positive 5V.
Specifically, the SSI module is that encoder often uses synchronous serial interface.
The beneficial effects of the utility model are: the utility model provides one kind based on the cascade SSI number of shift register
According to Acquisition Circuit, including 2 single-ended and differential conversion chip, m piece n bit shift register chip, master controller and SSI moulds
Block, difference needed for the single-ended clock signal of master controller is converted into SSI module by one single-ended and differential conversion chip
Clock signal is sent to SSI module clock pin；Another described single-ended and differential conversion chip believes the differential data of SSI module
Single ended signal needed for number being converted into shift register is sent to the serial input terminal of shift register chip；M piece n
Shift register chip cascade forms m*n bit shift register circuit, and m*n SSI serial datas are converted into m*n parallel-by-bit number
According to solving the acquisition of SSI data direct serial and occupy directly by the m*n I/O mouthfuls of technical solutions read parallel of master controller
Cpu resource is more, and execution cycle is long, and speed is slow, causes CPU power consumption big；SSI interface string turns and acquires required component to be not easy to obtain
It takes, and higher cost, the palpus Time-sharing control when acquisition digit is more, occupancy cpu resource is more, and control logic is complicated, operation week
Phase is long, and speed is slow, causes CPU power consumption big；Self-developing SSI converting interface is at high cost, and the development cycle is long, and development difficulty is big, risk
High technical problem designs control circuit using common general-purpose device, with the realization of simple, efficient, economic, reliable method
The acquisition of SSI data reaches and occupies that cpu resource is few, and execution cycle is short, and speed is fast, can be improved CPU operational efficiency, reduce CPU function
Consumption, required program code amount is few, and control is simple, and implementation is simple, and the development cycle is short, and required component is easy to obtain, hardware
Lower-cost technical effect.
Detailed description of the invention
The present invention will be further described with reference to the accompanying drawings and examples.
Fig. 1 is the circuit connection diagram of the utility model；
Fig. 2 is the main controller circuit connection schematic diagram of the utility model；
Fig. 3 is the SSI signal period timing diagram of the utility model；
Fig. 4 is the SSI signal timing diagram of the utility model；
In figure: U1. master controller；U2~U3. is single-ended with differential conversion chip；U4~U7. shift register chip.
Explanation of nouns:
1. shift register: Shift Register, be it is a kind of work under several same time pulses with trigger
Based on device, data are input in the device in a manner of concurrently or sequentially, then each time pulse successively to the left or
Move right a bit, is exported in output end.
2. cascade: referred to herein as the output using backing system as the input of rear class system, several systems successively being connected
It is connected together, to achieve the purpose that dilatation.System refers to 8 bit shift register chips herein.
3.SSI:Synchronous Serial Interface, synchronous serial interface are a kind of common industrial communications
Interface.
Specific embodiment
The utility model is described in further detail presently in connection with attached drawing.These attached drawings are simplified schematic diagram,
Only illustrate the basic structure of the utility model in a schematic way, therefore it only shows composition related with the utility model.
Embodiment 1:
As shown in Figure 1 and Figure 2, a kind of to be based on the cascade SSI data acquisition circuit of shift register, including 2 models
Single-ended and differential conversion chip U2, U3 of SN65176BDR, 8 bit shift register chip U4, U5 of 4 model 74HC595,
U6, U7, master controller U1 and the SSI encoder of a piece of model C8051F020 or C8051F022, single-ended and differential conversion
The pin 4 of chip U3 is connected to the simulation clock out pin of master controller U1, and pin 6,7 is connected respectively to SSI encoder
Clock pins 1,2, thus differential clock signal needed for master controller single-ended clock signal SCK is converted into SSI encoder
CLOCK+, CLOCK- are sent to SSI encoder clock pin；It is single-ended to be connected respectively to SSI with differential conversion chip U2 pin 6,7
The data signal port pin 3,4 of encoder, pin 1 are connected to the serial data input of first shift register chip U4
Pin 14, thus single ended input needed for differential data signals DATA+, DATA- of SSI encoder are converted into shift register
Signal is sent to the serial input terminal of shift register chip；The shift clock pin 11 of 48 bit shift register chips is connected to
Master controller clock pins, resetting pin 10 are connected to master controller and reset port pinout, and latch clock pin 12 is connected to master
The latch clock of controller passes through cascade data output pin 9 and serial data input pin between 4 shift registers
14 connect two-by-two, and pin 15,1,2,3,4,5,6,7 is parallel data delivery outlet, 32 parallel-by-bit numbers of 4 shift register chips
The I/O mouth of master controller is consecutively connected to according to output, so that 32 SSI serial datas are converted into 32 bit parallel datas, directly
It is read parallel by 32 I/O mouthfuls of master controller.
This circuit operation principle:
1, as shown in Figure 3, Figure 4, in a collection period tBInterior, master controller U1 generates one group according to SSI signal sequence
Clock pulses SCK, wherein including a commencing signal tDFC, a termination signal tMAnd 32 data clock signal tCL.The group
Clock pulses is divided into two-way, is sent all the way to the pin 4 of the single-ended and differential conversion chip U3 of model SN65176, is converted through U3
At differential clock signal CLOCK+ and CLOCK-, it is then sent to encoder clock pin, the synchronised clock as SSI signal makes
With；In addition it is fed directly to the pin 11 of shift register U4~U7 of model 74HC595, the shifting as shift register all the way
Digit pulse.
2, encoder receives synchronizing clock signals, starts SSI interface in the commencing signal stage, begins preparing data,
In the data clock stage, SSI data Serial output by turn from high to low, in the termination signal stage, the transmission of SSI data stops, and waits
Next collection period.
3, the differential data signals DATA+ and DATA- of encoder output send the single-ended and difference to model SN65176 to turn
The pin 7 and 6 for changing chip is converted into single ended data signal SER1 through U2, is then sent to the serial of first shift register U4
Encoder data is successively moved into shift register under shift pulse triggering by input pin 14, shift register group U4~U7
Group, until shift pulse terminates.
4, after a collection period clock pulses, encoder data has been moved fully into shift register group, at this time
Master controller U1 will generate a latch pulse RCK, be fed directly to the pin 12 of U4~U7, by the data in shift register group
Locking, then master controller reads the numerical value for the port I/O being connected with shift register group to get the code value of encoder is arrived.
The acquisition of one group of SSI data is completed at this time.
It is enlightenment, through the above description, related work people with the above-mentioned desirable embodiment according to the utility model
Member can carry out various changes and amendments in the range of without departing from this item utility model technical idea completely.This item is real
It is not limited to the contents of the specification with novel technical scope, it is necessary to its technology is determined according to scope of the claims
Property range.
Claims (7)
1. one kind is based on the cascade SSI data acquisition circuit of shift register, it is characterised in that: including 2 single-ended and difference turn
Change chip U2, U3, m piece n bit shift register chip U4, U5 ... Um+3, master controller U1 and SSI module, it is described it is single-ended with
Differential clock signal needed for the single-ended clock signal of master controller U1 is converted into SSI module by differential conversion chip U3 send to
SSI module clock pin；The differential data signals of SSI module are converted into shift LD by described single-ended and differential conversion chip U2
Single ended signal needed for device is sent to the serial input terminal of shift register chip；The m piece n bit shift register chip-scale
M*n SSI serial datas are converted into m*n bit parallel data, directly by main control by connection composition m*n bit shift register circuit
M*n I/O mouthfuls of device U1 are parallel to be read.
2. a kind of as described in claim 1 be based on the cascade SSI data acquisition circuit of shift register, it is characterised in that: described
Shift register chip is 8 bit shift register chips, and cascade quantity is 4.
3. a kind of as claimed in claim 2 be based on the cascade SSI data acquisition circuit of shift register, it is characterised in that: described
Single-ended and differential conversion chip U2, U3 model SN65176, it is single-ended to connect master controller U1 with differential conversion chip U3 pin 4
Clock out pin is simulated, pin 6,7 is connected respectively to the clock pins 1,2 of SSI module；It is single-ended to draw with differential conversion chip U2
Foot 6,7 is connected respectively to the data signal port pin 3,4 of SSI module, and pin 1 is connected to first shift register chip U4
Serial data input pin 14.
4. a kind of as claimed in claim 2 be based on the cascade SSI data acquisition circuit of shift register, it is characterised in that: described
Shift register chip U4, U5, U6, U7 model is 74HC595, when shift clock pin 11 is connected to master controller U1 simulation
Clock output pin, resetting pin 10 are connected to master controller U1 and reset port pinout, and latch clock pin 12 is connected to main control
The latch clock of device U1 passes through cascade data output pin 9 and serial data input pin between four shift registers
14 connect two-by-two, and pin 15,1,2,3,4,5,6,7 is parallel data delivery outlet, 32 parallel-by-bits of four shift register chips
Data export the I/O mouth for being consecutively connected to master controller U1.
5. a kind of as claimed in claim 1 or 2 be based on the cascade SSI data acquisition circuit of shift register, it is characterised in that: main
The model C8051F020 or C8051F022 of controller U1.
6. a kind of as claimed in claim 2 be based on the cascade SSI data acquisition circuit of shift register, it is characterised in that: described 2
The single-ended 5V that is positive with differential conversion chip U2, U3,48 bit shift register chip U4, U5, U6, U7 power supply voltages of piece.
7. a kind of as described in claim 1 be based on the cascade SSI data acquisition circuit of shift register, it is characterised in that: described
SSI module is that encoder often uses synchronous serial interface.
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| CN201821452606.9U CN208985151U (en) | 2018-09-06 | 2018-09-06 | One kind being based on the cascade SSI data acquisition circuit of shift register |
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| CN201821452606.9U CN208985151U (en) | 2018-09-06 | 2018-09-06 | One kind being based on the cascade SSI data acquisition circuit of shift register |
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Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111123800A (en) * | 2019-12-31 | 2020-05-08 | 武汉卓目科技有限公司 | Serial multi-channel power distribution switch control circuit |
| CN111290787A (en) * | 2019-06-19 | 2020-06-16 | 锐迪科（重庆）微电子科技有限公司 | Arithmetic device and arithmetic method |
| CN111983270A (en) * | 2020-07-30 | 2020-11-24 | 华润赛美科微电子(深圳)有限公司 | Expansion circuit, tester and test method |
| CN112600807A (en) * | 2020-12-03 | 2021-04-02 | 航宇救生装备有限公司 | Wireless acquisition method of synchronous serial interface encoder |
| CN115065131A (en) * | 2022-08-15 | 2022-09-16 | 深圳市百千成电子有限公司 | BMS management control system for energy storage product battery |
-
2018
- 2018-09-06 CN CN201821452606.9U patent/CN208985151U/en active Active
Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111290787A (en) * | 2019-06-19 | 2020-06-16 | 锐迪科（重庆）微电子科技有限公司 | Arithmetic device and arithmetic method |
| CN111290787B (en) * | 2019-06-19 | 2022-11-08 | 锐迪科（重庆）微电子科技有限公司 | Arithmetic device and arithmetic method |
| CN111123800A (en) * | 2019-12-31 | 2020-05-08 | 武汉卓目科技有限公司 | Serial multi-channel power distribution switch control circuit |
| CN111983270A (en) * | 2020-07-30 | 2020-11-24 | 华润赛美科微电子(深圳)有限公司 | Expansion circuit, tester and test method |
| CN112600807A (en) * | 2020-12-03 | 2021-04-02 | 航宇救生装备有限公司 | Wireless acquisition method of synchronous serial interface encoder |
| CN115065131A (en) * | 2022-08-15 | 2022-09-16 | 深圳市百千成电子有限公司 | BMS management control system for energy storage product battery |
| CN115065131B (en) * | 2022-08-15 | 2022-11-29 | 马瑶 | BMS management control system for energy storage product battery |
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