CN208955998U - A kind of flow control relaxation oscillator - Google Patents
A kind of flow control relaxation oscillator Download PDFInfo
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- CN208955998U CN208955998U CN201821748787.XU CN201821748787U CN208955998U CN 208955998 U CN208955998 U CN 208955998U CN 201821748787 U CN201821748787 U CN 201821748787U CN 208955998 U CN208955998 U CN 208955998U
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Abstract
The utility model relates to technical field of integrated circuits, and in particular to a kind of flow control relaxation oscillator, including reference current source, delay unit and shaping circuit.The reference current source is threshold reference circuit, can produce size and is the electric current of Vgs/R, and provides bias voltage VBP and VBN；The VBP and VBN of the delay unit corresponding port and reference current source are connected as delay unit and provide biasing, and the input of delay unit is connect with the output VOUT of flow control relaxation oscillator, and the output of delay unit and the input of shaping circuit connect；Shaping circuit carries out shaping, and the output VOUT as flow control relaxation oscillator to the signal exported from delay unit.Flow control relaxation oscillator described in the utility model has the characteristic of super low-power consumption, while output frequency does not influence active device by technique, supply voltage and temperature.
Description
Technical field
The utility model relates to technical field of integrated circuits, and in particular to a kind of flow control relaxation oscillator.
Background technique
In standard CMOS process, the implementation of oscillator mainly has ring oscillator, LC oscillator and relaxation oscillation
Device.The delay Td of ring oscillator and the usual delay unit of relaxation oscillator designs the frequency of oscillator, if ring oscillation
The number of device delay cell is N, then ring oscillator output frequency is F=1/ (2*N*Td).And flow control relaxation oscillator is just
It is that control delay unit input current changes delay Td, to achieve the purpose that control relaxation oscillator output frequency.
Frequency of oscillation is influenced very big by temperature and technological parameter drift, is made a big impact to the stability of circuit.Vibration
Influence of the performance of device by technological parameter, temperature and supply voltage is swung, the performance for being mostly derived from metal-oxide-semiconductor is joined with temperature, technique
Number changes and changes.When temperature, changes in process parameters, the mobility and threshold voltage of carrier can be changed correspondingly, thus shadow
The performance of oscillator is rung.Current some technical solutions use the modes such as compensation technique, latch cicuit, digital calibration techniques,
There are circuit structures it is complicated, circuit power consumption is big the problems such as.Therefore, it is discrete small that a kind of simple circuit structure, low-power consumption, technique are studied
And temperature drift it is small oscillator it is significant.
Utility model content
In view of the deficiencies of the prior art, the utility model discloses a kind of flow control relaxation oscillator, the streams of the utility model
It is simple to control relaxation oscillator structure, is influenced by process deviation, temperature change, mains voltage variations small.
The utility model is achieved by the following technical programs:
A kind of flow control relaxation oscillator, including reference current source, delay unit and shaping circuit；The reference current source is
Threshold reference circuit provides bias voltage VBP and VBN, and the VBP and VBN of the reference current source are connected with the delay unit
It connects；The input of the delay unit is connect with the output VOUT of flow control relaxation oscillator, and output and the input of shaping circuit connect
It connects；Output VOUT of the output of the shaping circuit as flow control relaxation oscillator, the shaping circuit is to the delay unit
The signal of output carries out shaping.
Preferably, it is Vgs/R, the threshold reference that the reference current source, which generates size of current by threshold reference circuit,
Circuit provides biasing for the delay unit, and Vgs is gate source voltage, and R is resistance needed for threshold reference circuit generates reference current
Resistance value.
Preferably, the source electrode of the PMOS transistor M1 of the reference current source meets power supply, grid and PMOS transistor M2
Grid and drain electrode connection to provide bias voltage VBP；
The source electrode of the M2 connects power supply, the drain electrode of M1 and the grid of NMOS transistor M3 and the drain electrode of NMOS transistor M4 connects
It connects；
The drain electrode of the M3 is connect with the drain electrode of the grid of M1 and M2 and M2, the grid and resistance R1 of source electrode and M4
One end is connected to provide bias voltage VBN；
The other end of the resistance R1 is grounded, the source electrode ground connection of the M4.
Preferably, the delay unit includes PMOS transistor MP1, MP2, MP3, MP4, MP5 and MP6；NMOS transistor
MN1, MN2, MN3, MN4 and MN5；And capacitor C1.
Preferably, the source electrode of the MP1 connects power supply, and grid meets VBP, and drain electrode is connect with the source electrode of the MP5；
The source electrode of the MP2 connects power supply, and grid meets VBP, and drain electrode is connect with the source electrode of the MP6；
The source electrode of the MP3 connects power supply, and grid is connect with the drain electrode of the MP6 and MN2, drain electrode with the MN3 and
The drain electrode of MN4 and the grid connection of MN5；
The source electrode of the MP4 connects power supply, and grid meets VBP, and drain electrode and the drain electrode of the MN5 are connected to delay unit
Output；
The output VOUT connection of the grid of the MP5 and the grid of MN1 and flow control relaxation oscillator, drain electrode is with MN1's
Drain electrode, MN2 are connected with the anode of the grid of MP6 and capacitor C1；
The grid of the MP6 and the grid of MN2 connect, and drain electrode is connect with the drain electrode of MN2.
Preferably, the output VOUT connection of the grid of the MN1 and the grid of MP5 and flow control relaxation oscillator, source
Pole ground connection；
The drain electrode of the grid and MN1 of the MN2 and the anode connection of capacitor C1, source electrode ground connection；The grid of the MN3 connects
VBN, source electrode ground connection；
The output VOUT connection of the grid of the MN4 and the grid of MN1 and flow control relaxation oscillator, source electrode ground connection；
The grid of the MN5 is connect with the drain electrode of MN3 and MN4, source electrode ground connection.
Preferably, the grid of the drain electrode of the anode and MN1 of the C1 and MP6 connect, negativing ending grounding.
Preferably, described MP2, MP6 and MN2 constitute the comparator of flow control relaxation oscillator.
Preferably, reference current source combination delay unit charges to capacitor C1 with the k times of electric current of size Vgs/R, works as charging
When voltage reaches the threshold value of the comparator, output will be overturn from high to low, and output delay at this time is (C1*Vgs)/(k*Vgs/
R)=R*C1/k, wherein k is current mirror coefficient, the voltage when threshold value of the comparator is comparator overturning, when flowing through MP2
Electric current when being Vgs/R its value be Vgs.
Preferably, the shaping circuit includes phase inverter, and carries out shaping, input terminal and the delay to input signal
The output of unit connects, and exports the output VOUT as flow control relaxation oscillator.
The utility model has the following beneficial effects:
1) the utility model is made of reference current source, delay unit and shaping circuit, wherein threshold reference quiescent dissipation
It is small, and delay unit and shaping circuit do not have quiescent dissipation；Therefore the flow control relaxation oscillator of the utility model has ultralow
The characteristics of power consumption；
2) electric current that the reference current source generation size of the utility model is Vgs/R is with size in conjunction with delay unit
K (k is current mirror coefficient) times electric current of Vgs/R charges to capacitor C1, when charging voltage reaches what MP2, MP6 and MN2 were constituted
The threshold value (when the electric current for flowing through MP2 is Vgs/R, the threshold value of comparator is Vgs) of comparator, output will be overturn, and be exported at this time
Delay is (C1*Vgs)/(k*Vgs/R)=R*C1/k, it is seen that delay is not straight with the technological parameter and supply voltage of MOS device
Association is connect, reduces MOS device process deviation, mains fluctuations and temperature drift to the shadow of flow control relaxation oscillator performance
It rings；
3) in order to reduce delay of other MOS transistors in transmission process in the utility model, by the grid of MN4 transistor
Pole is directly connected to the output VOUT of flow control relaxation oscillator, eliminates NMOS transistor MN1 to discharge time of capacitor C1
It influences, and can ignore for the delay relative capacity C1 charging time of other logical devices, to further reduce MOS
The influence of device technology deviation, mains fluctuations and temperature drift to flow control relaxation oscillator performance；
4) flow control relaxation oscillator circuit structure is simple in the utility model, if cooperated again to resistance in reference current source
R and current mirror coefficient k trim, and the flow control relaxation oscillator of the utility model can be simply and easily to flow control relaxation oscillation
Device output frequency is trimmed, and realizes that output frequency is not influenced by process deviation, mains fluctuations and temperature drift.
Detailed description of the invention
In order to illustrate the embodiment of the utility model or the technical proposal in the existing technology more clearly, below will be to embodiment
Or attached drawing needed to be used in the description of the prior art is briefly described, it should be apparent that, the accompanying drawings in the following description is only
It is some embodiments of the utility model, for those of ordinary skill in the art, in the premise not made the creative labor
Under, it is also possible to obtain other drawings based on these drawings.
Fig. 1 is a kind of flow control relaxation oscillator schematic diagram disclosed in the utility model embodiment；
Fig. 2 is reference current source schematic diagram disclosed in the utility model embodiment.
Specific embodiment
It is practical new below in conjunction with this to keep the objectives, technical solutions, and advantages of the embodiments of the present invention clearer
Attached drawing in type embodiment, the technical scheme in the utility model embodiment is clearly and completely described, it is clear that is retouched
The embodiment stated is the utility model a part of the embodiment, instead of all the embodiments.Based on the implementation in the utility model
Example, every other embodiment obtained by those of ordinary skill in the art without making creative efforts belong to
The range of the utility model protection.
In one embodiment of the utility model, a kind of flow control relaxation oscillator as shown in Figure 1, including reference current
Source, delay unit and shaping circuit；The reference current source provides bias voltage VBP and VBN, the ginseng for threshold reference circuit
The VBP and VBN for examining current source are connected with the delay unit；The input of the delay unit is defeated with flow control relaxation oscillator
VOUT connection out, output are connect with the input of shaping circuit；The output of the shaping circuit is as flow control relaxation oscillator
VOUT is exported, the shaping circuit carries out shaping to the signal that the delay unit exports.
Delay unit includes PMOS transistor MP1, MP2, MP3, MP4, MP5 and MP6；NMOS transistor MN1, MN2, MN3,
MN4 and MN5；And capacitor C1.
Wherein the source electrode of MP1 connects power supply, and grid meets VBP, and drain electrode is connect with the source electrode of the MP5；
The source electrode of MP2 connects power supply, and grid meets VBP, and drain electrode is connect with the source electrode of the MP6；
The source electrode of MP3 connects power supply, and grid is connect with the drain electrode of the MP6 and MN2, and drain electrode is with the MN3's and MN4
The connection of the grid of drain electrode and MN5；
The source electrode of MP4 connects power supply, and grid meets VBP, and the drain electrode with the MN5 that drains is connected to the defeated of delay unit
Out；
The output VOUT connection of the grid of MP5 and the grid of MN1 and flow control relaxation oscillator, drain electrode and the drain electrode of MN1,
MN2 is connected with the anode of the grid of MP6 and capacitor C1；
The grid of MP6 and the grid of MN2 connect, and drain electrode is connect with the drain electrode of MN2.
The output VOUT connection of the grid of MN1 and the grid of MP5 and flow control relaxation oscillator, source electrode ground connection；
The drain electrode of the grid and MN1 of MN2 and the anode connection of capacitor C1, source electrode ground connection；The grid of the MN3 meets VBN,
Its source electrode ground connection；
The output VOUT connection of the grid of MN4 and the grid of MN1 and flow control relaxation oscillator, source electrode ground connection；
The grid of MN5 is connect with the drain electrode of MN3 and MN4, source electrode ground connection.
The drain electrode of the anode and MN1 of C1 and the grid connection of MP6, negativing ending grounding.
In one embodiment of the utility model, as shown in Fig. 2, the reference current source, wherein PMOS transistor M1
Source electrode connect power supply, the grid and drain electrode of grid and PMOS transistor M2 are connected to provide bias voltage VBP；
The source electrode of the M2 connects power supply, the drain electrode of M1 and the grid of NMOS transistor M3 and the drain electrode of NMOS transistor M4 connects
It connects；
The drain electrode of the M3 is connect with the drain electrode of the grid of M1 and M2 and M2, the grid and resistance R1 of source electrode and M4
One end is connected to provide bias voltage VBN；
The other end of the resistance R1 is grounded, the source electrode ground connection of the M4.
As shown in Figure 1, the shaping circuit includes phase inverter, and shaping carried out to input signal, input terminal with it is described
The output of delay unit connects, and exports the output VOUT as controlled oscillator.
Fig. 1 and reference current source shown in Fig. 2 it is practical be threshold reference, producing electric current that size is Vgs/R1, (Vgs is
The gate source voltage of NMOS transistor M4, R1 are the resistance value of resistance needed for threshold reference circuit generates reference current), and by biasing
Voltage VBP and VBN mirror image to delay unit, when current mirror using size be the electric current pair of k*Vgs/R1 (k is current mirror coefficient)
When capacitor C1 charges, if the voltage of capacitor C1 is charged to the threshold value of the comparator of MP2, MP6 and MN2 composition (when the electricity for flowing through MP2
When stream is Vgs/R, the threshold value of comparator is Vgs), high to Low turn over will occur for the output for the comparator that MP2, MP6 and MN2 are constituted
Turn, the charging time of capacitor C1 is (C1*Vgs)/(k*Vgs/R1)=R1*C1/k at this time.Further, NMOS transistor MN2
It is matched in domain with NMOS transistor M4, can reduce the influence of process deviation and temperature drift to MOS transistor Vgs.
On the other hand, the grid of MN4 transistor is directly connected to the output VOUT of flow control relaxation oscillator in time-delay unit circuit
Shield the contribution that NMOS transistor MN1 is always delayed to the discharge time of capacitor C1 to loop；And other logic devices in the loop
The transmission delay of part can ignore the influence that loop is always delayed since parasitic capacitance is small；That is flow control relaxation oscillation
Total delay of device loop is almost determined that output delay Td is approximately equal to (C1*Vgs)/(k* by charging time of the current source to capacitor C1
Vgs/R1)=R1*C1/k.
So it can be seen that the output frequency of flow control relaxation oscillator is not by MOS device work in the utility model embodiment
Skill deviation, mains fluctuations and the influence of temperature drift.For process deviation in R1 and delay unit in reference current source
The influence of capacitor C1 can be solved by trimming resistance R1 and current mirror coefficient k.
Threshold reference quiescent dissipation is small in the utility model embodiment, and delay unit and shaping circuit are without static function
Consumption；Therefore the flow control relaxation oscillator of the utility model embodiment has the characteristics that super low-power consumption.
Above embodiments are only to illustrate the technical solution of the utility model, rather than its limitations；Although referring to aforementioned reality
Example is applied the utility model is described in detail, those skilled in the art should understand that: it still can be to preceding
Technical solution documented by each embodiment is stated to modify or equivalent replacement of some of the technical features；And these
It modifies or replaces, the spirit and model of various embodiments of the utility model technical solution that it does not separate the essence of the corresponding technical solution
It encloses.
Claims (10)
1. a kind of flow control relaxation oscillator, it is characterised in that: including reference current source, delay unit and shaping circuit；The ginseng
It examines current source and provides bias voltage VBP and VBN, the VBP and VBN of the reference current source and the delay for threshold reference circuit
Unit is connected；The input of the delay unit is connect with the output VOUT of flow control relaxation oscillator, output and shaping circuit
Input connection；Output VOUT of the output of the shaping circuit as flow control relaxation oscillator, the shaping circuit is to described
The signal of delay unit output carries out shaping.
2. flow control relaxation oscillator according to claim 1, which is characterized in that the reference current source passes through threshold reference
It is Vgs/R that circuit, which generates size of current, and the threshold reference circuit provides biasing for the delay unit, and Vgs is gate source voltage,
R is the resistance value of resistance needed for threshold reference circuit generates reference current.
3. flow control relaxation oscillator according to claim 1, which is characterized in that the PMOS transistor of the reference current source
The source electrode of M1 connects power supply, and the grid and drain electrode connection of grid and PMOS transistor M2 are to provide bias voltage VBP；
The source electrode of the M2 connects power supply, and the drain electrode of M1 is connect with the drain electrode of the grid of NMOS transistor M3 and NMOS transistor M4；
The drain electrode of the M3 is connect with the drain electrode of the grid of M1 and M2 and M2, one end of the grid and resistance R1 of source electrode and M4
Connection is to provide bias voltage VBN；
The other end of the resistance R1 is grounded, the source electrode ground connection of the M4.
4. flow control relaxation oscillator according to claim 1, which is characterized in that the delay unit includes PMOS transistor
MP1, MP2, MP3, MP4, MP5 and MP6；NMOS transistor MN1, MN2, MN3, MN4 and MN5；And capacitor C1.
5. flow control relaxation oscillator according to claim 4, which is characterized in that the source electrode of the MP1 connects power supply, grid
VBP is met, drain electrode is connect with the source electrode of the MP5；
The source electrode of the MP2 connects power supply, and grid meets VBP, and drain electrode is connect with the source electrode of the MP6；
The source electrode of the MP3 connects power supply, and grid is connect with the drain electrode of the MP6 and MN2, and drain electrode is with the MN3's and MN4
The connection of the grid of drain electrode and MN5；
The source electrode of the MP4 connects power supply, and grid meets VBP, and the drain electrode with the MN5 that drains is connected to the defeated of delay unit
Out；
The output VOUT connection of the grid of the MP5 and the grid of MN1 and flow control relaxation oscillator, drain electrode and the drain electrode of MN1,
MN2 is connected with the anode of the grid of MP6 and capacitor C1；
The grid of the MP6 and the grid of MN2 connect, and drain electrode is connect with the drain electrode of MN2.
6. flow control relaxation oscillator according to claim 4, which is characterized in that the grid of the grid of the MN1 and MP5 with
And the output VOUT connection of flow control relaxation oscillator, source electrode ground connection；
The drain electrode of the grid and MN1 of the MN2 and the anode connection of capacitor C1, source electrode ground connection；
The grid of the MN3 connects VBN, source electrode ground connection；
The output VOUT connection of the grid of the MN4 and the grid of MN1 and flow control relaxation oscillator, source electrode ground connection；
The grid of the MN5 is connect with the drain electrode of MN3 and MN4, source electrode ground connection.
7. flow control relaxation oscillator according to claim 4, which is characterized in that the drain electrode of the anode and MN1 of the C1 with
And the grid connection of MP6, negativing ending grounding.
8. flow control relaxation oscillator according to claim 4, which is characterized in that described MP2, MP6 and MN2 constitute flow control pine
The comparator of relaxation oscillator.
9. flow control relaxation oscillator according to claim 8, which is characterized in that reference current source combination delay unit, with
The k times of electric current that size is Vgs/R charges to capacitor C1, and when charging voltage reaches the threshold value of the comparator, output will be by height
To low overturning, output delay at this time is (C1*Vgs)/(k*Vgs/R)=R*C1/k, and wherein k is current mirror coefficient, the ratio
Voltage when threshold value compared with device is comparator overturning, when the electric current for flowing through MP2 is Vgs/R, its value is Vgs.
10. flow control relaxation oscillator according to claim 1, which is characterized in that the shaping circuit includes phase inverter, and
Shaping is carried out to input signal, input terminal is connect with the output of the delay unit, exports the output as controlled oscillator
VOUT。
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| CN201821748787.XU CN208955998U (en) | 2018-10-26 | 2018-10-26 | A kind of flow control relaxation oscillator |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109104155A (en) * | 2018-10-26 | 2018-12-28 | 上海海栎创微电子有限公司 | A kind of flow control relaxation oscillator |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109104155A (en) * | 2018-10-26 | 2018-12-28 | 上海海栎创微电子有限公司 | A kind of flow control relaxation oscillator |
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Address after: Room 411, 4th floor, main building, No. 835 and 937, Dangui Road, China (Shanghai) pilot Free Trade Zone, Pudong New Area, Shanghai, 200131 Patentee after: Shanghai hailichuang Technology Co.,Ltd. Address before: 201203 Room 411, 4th Floor, Main Building (1 Building) of Zhangjiang Guochuang Center, 899 Dangui Road, Pudong New Area, Shanghai Patentee before: SHANGHAI HYNITRON MICROELECTRONIC Co.,Ltd. |
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