CN208953667U - Chip and chip test system - Google Patents
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- CN208953667U CN208953667U CN201821631053.3U CN201821631053U CN208953667U CN 208953667 U CN208953667 U CN 208953667U CN 201821631053 U CN201821631053 U CN 201821631053U CN 208953667 U CN208953667 U CN 208953667U
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Abstract
The disclosure provides a kind of chip and chip test system.Chip has decoder module and test pattern control module, judges that the input signal then responds follow-up test signal for preactivate signal after being decoded to input signal, is otherwise not responding to follow-up test signal.The chip and chip detecting method that the disclosure provides can make test equipment disposably connect more chips by setting preactivate signal under conditions of saving I/O interface as far as possible, and can be realized the independent test to each chip.
Description
Technical field
This disclosure relates to technical field of semiconductors, in particular to a kind of chip and can to multiple chips into
The test macro that row is individually tested.
Background technique
In the related art, it when testing multiple chips, in order to realize the independent test to each chip, often needs
Chip select line is separately configured for each chip.
Fig. 1 is a kind of schematic diagram of multi-chip test scene in the related technology.With reference to Fig. 1, in Fig. 1, five tested cores
The chip select line of piece respectively occupies an I/O interface.In the available limited situation of I/O interface of test equipment, occupies I/O interface and match
The testing efficiency of test equipment can be reduced by setting chip select line, reduce the number of chips that test equipment can test.
Therefore, it is necessary to the test modes to multiple chips to improve, and improve the chip that test equipment can connect simultaneously
Quantity, and then promote chip testing efficiency.
It should be noted that information is only used for reinforcing the reason to the background of the disclosure disclosed in above-mentioned background technology part
Solution, therefore may include the information not constituted to the prior art known to persons of ordinary skill in the art.
Utility model content
The disclosure is designed to provide a kind of chip and chip test system, for overcoming at least to a certain extent
Due to the relevant technologies limitation and defect caused by the insufficient problem of number of chips that connects of test equipment.
According to the first aspect of the embodiments of the present disclosure, a kind of chip is provided, physical signal line and data signal line coupling are passed through
It is connected to test equipment, comprising:
Decoder module is coupled to the physical signal line, for believing the first input on the physical signal line
It number is decoded and exports test mode signal or test command signal, the test mode signal is prior to test instruction letter
Number occur；
Test pattern control module is coupled to the decoder module and the data signal line, for according to the test
Test pattern is arranged in the second input signal on mode signal and the data signal line.
In a kind of exemplary embodiment of the disclosure, the decoder module includes:
Design for Measurability decoding unit, input terminal are coupled to the physical signal line, and output end includes n group enable signal
Line, for the test mode signal to be decoded and exported to first input signal, the test mode signal includes
N group enable signal corresponding to n test pattern；
Command signal decoding unit is tested, input terminal is coupled to the physical signal line, for believing first input
It number is decoded and exports the test command signal.
In a kind of exemplary embodiment of the disclosure, enable signal described in every group includes that the first enable signal and second makes
Energy signal, enable signal line described in every group include the first enable signal line and the second enable signal line, the test pattern control
Module includes:
N test pattern enabling unit corresponds respectively to the n test pattern, wherein each test pattern makes
Can unit include:
Latch cicuit, input terminal are coupled to the first enable signal line and the data signal line, for according to
First enable signal and second input signal export preactivate signal；
With door, input terminal is coupled to the output end of the second enable signal line and the latch cicuit, for according to institute
It states the second enable signal and preactivate signal output corresponds to the third enable signal of the test pattern.
In a kind of exemplary embodiment of the disclosure, the latch cicuit includes:
Transmission gate, the first control terminal are coupled to the first enable signal line, and the second control terminal passes through the first reverser coupling
It is connected to the first enable signal line, input terminal is coupled to the data signal line, for being pre- in first enable signal
If exporting second input signal when level；
Second reverser, input terminal are coupled to the output end of the transmission gate, and output end is defeated as the latch cicuit
Outlet, for exporting the reverse signal of second input signal as the preactivate signal.
In a kind of exemplary embodiment of the disclosure, the input terminal of the latch cicuit is further coupled to reseting signal line,
The latch cicuit is also used to export the preactivate signal according to default reset signal.
In a kind of exemplary embodiment of the disclosure, the latch cicuit further include:
Nor gate, input terminal are coupled to the output end of the reseting signal line and the latch cicuit, and output end is coupled to
The input terminal of second reverser.
In a kind of exemplary embodiment of the disclosure, the test pattern control module is coupled to a plurality of data letter
One in number line.
In a kind of exemplary embodiment of the disclosure, the test pattern control module is according to corresponding to each survey
The test pattern is arranged in the third enable signal of die trial formula.
In a kind of exemplary embodiment of the disclosure, the test instruction execution module responds the test command signal
Including by being operated to the data signal line.
In a kind of exemplary embodiment of the disclosure, the physical signal line include control signal wire, chip selection signal line,
The address signal line.
According to another aspect of the disclosure, a kind of chip test system is provided, comprising:
Test equipment has a plurality of physical signal line and data signal line, for swashing to chip under test output with pre-
Output test signal after the signal of function living；
Multiple chip testing positions, share the physical signal line of the test equipment, and each chip testing position is logical
It crosses different data signal lines to connect with the test equipment, each chip testing position connects one such as above-mentioned any one
The chip.
In a kind of exemplary embodiment of the disclosure, the physical signal line include control signal wire, chip selection signal line,
Address signal line.
In a kind of exemplary embodiment of the disclosure, the test equipment is also used to exporting institute to the chip under test
Chip output lock signal is had connected to other in addition to chip under test while stating the signal of preactivate function.
The chip that the embodiment of the present disclosure provides has decoder module and test pattern control module, carries out to input signal
Judge that the input signal then responds follow-up test signal for preactivate signal after decoding, is otherwise not responding to follow-up test signal.It is logical
Setting preactivate signal is crossed, test equipment can be allow disposably to connect more multicore under conditions of saving I/O interface as far as possible
Piece, and can be realized the independent test to each chip.
It should be understood that above general description and following detailed description be only it is exemplary and explanatory, not
The disclosure can be limited.
Detailed description of the invention
The drawings herein are incorporated into the specification and forms part of this specification, and shows the implementation for meeting the disclosure
Example, and together with specification for explaining the principles of this disclosure.It should be evident that the accompanying drawings in the following description is only the disclosure
Some embodiments for those of ordinary skill in the art without creative efforts, can also basis
These attached drawings obtain other attached drawings.
Fig. 1 is the schematic diagram of multi-chip test scene in the related technology.
Fig. 2 is the schematic diagram of chip aerial lug in the embodiment of the present disclosure.
Fig. 3 is the block diagram of chip in the embodiment of the present disclosure.
Fig. 4 is the schematic diagram of decoder module in an embodiment of the present disclosure.
Fig. 5 is the schematic diagram of test pattern control module in an embodiment of the present disclosure.
Fig. 6 is the schematic diagram of latch cicuit shown in Fig. 5.
Fig. 7 is another schematic diagram of test pattern control module in an embodiment of the present disclosure.
Fig. 8 is the schematic diagram of latch cicuit shown in Fig. 7.
Fig. 9 is the control logic schematic diagram of Fig. 7 and latch cicuit shown in Fig. 8.
Figure 10 is the schematic diagram of chip test system in the embodiment of the present disclosure.
Figure 11 is the control sequential figure of chip test system in the embodiment of the present disclosure.
Specific embodiment
Example embodiment is described more fully with reference to the drawings.However, example embodiment can be with a variety of shapes
Formula is implemented, and is not understood as limited to example set forth herein；On the contrary, thesing embodiments are provided so that the disclosure will more
Fully and completely, and by the design of example embodiment comprehensively it is communicated to those skilled in the art.Described feature, knot
Structure or characteristic can be incorporated in any suitable manner in one or more embodiments.In the following description, it provides perhaps
More details fully understand embodiment of the present disclosure to provide.It will be appreciated, however, by one skilled in the art that can
It is omitted with technical solution of the disclosure one or more in the specific detail, or others side can be used
Method, constituent element, device, step etc..In other cases, be not shown in detail or describe known solution to avoid a presumptuous guest usurps the role of the host and
So that all aspects of this disclosure thicken.
In addition, attached drawing is only the schematic illustrations of the disclosure, identical appended drawing reference indicates same or similar portion in figure
Point, thus repetition thereof will be omitted.Some block diagrams shown in the drawings are functional entitys, not necessarily necessary and object
The entity managed or be logically independent is corresponding.These functional entitys can be realized using software form, or in one or more
These functional entitys are realized in hardware module or integrated circuit, or in heterogeneous networks and/or processor device and/or microcontroller
These functional entitys are realized in device.
Disclosure example embodiment is described in detail with reference to the accompanying drawing.
Fig. 2 is the schematic diagram of chip aerial lug in the embodiment of the present disclosure.
With reference to Fig. 2, chip 1 that the disclosure provides by control signal wire, chip selection signal line, address signal line sum number it is believed that
Number line is coupled to test equipment 2.
Fig. 3 is the block diagram of chip in the embodiment of the present disclosure.
With reference to Fig. 3, in one embodiment, chip 1 may include:
Decoder module 11 is coupled to physical signal line, for the first input signal IN1 on physical signal line into
Row decodes and exports test mode signal MOD or test command signal COM, test mode signal go out prior to test command signal
It is existing；
Test pattern control module 12 is coupled to decoder module 11 and data signal line DQ, for being believed according to test pattern
Test pattern is arranged in the second input signal IN2 on number MOD and data signal line；
Instruction execution module 13 is tested, decoder module 11, test pattern control module 12 and data signal line DQ are coupled to,
For being arranged to always response test command signal according to test pattern response test command signal COM or in test pattern
COM。
In the embodiment shown in fig. 3, physical signal line includes control signal wire CMD, chip selection signal line CS, address signal
Line ADD, in other embodiments, the setting of physical signal line can also have other modes.
In the embodiments of the present disclosure, the first input signal can be divided into two kinds, respectively include test pattern setting signal and
Test command signal.Decoder module 11 is firstly received the first input signal that can decode test mode signal, then connects
Receive the first input signal that can decode test command signal.
It is corresponding, when the first input signal IN1 can be decoded test mode signal, with the first input signal IN1
The the second input signal IN2 on data signal line occurred simultaneously can be considered as enabling the chip test mode setting function
Preactivate signal or the lock signal for disabling the chip test mode setting function；When the first input signal IN1 can be decoded
When testing command signal COM, the second input signal IN2 on data signal line occurred simultaneously with the first input signal IN1 can
Think normal data signal under test.
In one embodiment, test pattern control module is coupled to one in a plurality of data signal line, such as headed by
Item.At this point, the first place of the second input signal corresponding data signal wire.It can be set when the second input signal is 1, test pattern
Test pattern can be arranged in control module according to test mode signal, and responds subsequent test instruction letter according to test pattern
Number；When the second input signal is 0, test pattern cannot be arranged according to test mode signal in test pattern control module, also not
Subsequent test command signal can be responded.It is above-mentioned merely illustrative to the set-up mode of the second input signal, those skilled in the art
The digit and meaning setting, the disclosure that the second input signal can voluntarily be adjusted according to the actual situation are not particularly limited this.
Testing instruction execution module 13 can be according to the test pattern response decoding mould that test pattern control module 12 is arranged
The test command signal COM that block 11 is sent.If test pattern control module 12 can not be set by the control of the second input signal IN2
When setting test pattern, test pattern is nothing, tests instruction execution module 13 at this time and does not respond to test command signal COM.
In some embodiments, test 13 response test command signal COM of instruction execution module includes according to COM pairs of command signal of test
Data signal line DQ carries out read or write.Test instruction execution module 13 may include multiple submodule, response test instruction
The mode of signal can also there are many, the disclosure is not particularly limited this.
In addition to above-mentioned module, chip 1 can also include multiple functional modules such as power module, memory module, due to it
It is not related to the utility model main points of the disclosure, therefore is repeated no more in this, it is also unmarked in figure.
By being decoded in advance to the first input signal, to identify test mode signal, and according to second occurred simultaneously
Input wire size determines whether to be arranged test pattern and whether responds follow-up test command signal, may be implemented same in multiple chips
When tested and chip when not being chip under test, which does not respond test command signal, it is possible thereby to save test
The wiring quantity of equipment.
Fig. 4 is the schematic diagram of decoder module in an embodiment of the present disclosure.
With reference to Fig. 4, in a kind of exemplary embodiment of the disclosure, decoder module 11 includes:
Design for Measurability decoding unit 111, input terminal are coupled to control signal wire CMD, chip selection signal line CS, address signal
Line ADD, output end includes n group enable signal line, for being decoded to the first input signal IN1 and exporting test mode signal
MOD, test mode signal MOD include the n group enable signal corresponding to n test pattern；
Command signal decoding unit 112 is tested, input terminal is coupled to control signal wire CMD, chip selection signal line CS, address letter
Number line ADD, for test command signal COM to be decoded and exported to the first input signal IN1.
Design for Measurability decoding unit 111 is identical with the test input terminal line of command signal decoding unit 112, Ke Yitong
When receive the first input signal from control signal wire, chip selection signal line, address signal line, and simultaneously to the first input signal
It is decoded.Since the function in the first input signal of different phase is different, therefore design for Measurability decoding unit 111 and test refer to
Enable in signal decoding unit 112 may only one can decode valid data and export, another can not be decoded effectively
It can be set to export in vain when data.To the decoded method of the first input signal can there are many, the disclosure does not make spy to this
Different limitation.
By the way that two decoding units are arranged to the first input signal, the purpose of the first input signal can be accurately identified, is permitted
Perhaps more complicated control is carried out to chip, and then may be implemented individually to control the chip of multiple multiplexed signals lines.
Fig. 5 is the schematic diagram of test pattern control module in an embodiment of the present disclosure.
With reference to Fig. 4 and Fig. 5, in a kind of exemplary embodiment of the disclosure, every group of enable signal includes the first enabled letter
Number DFT_n_En1 and the second enable signal DFT_n_En2, every group of enable signal line include that the first enable signal line and second are enabled
Signal wire, test pattern control module 12 include:
N test pattern enabling unit 121, corresponds respectively to n test pattern, wherein each test pattern enabling unit
21 include:
Latch cicuit 211, input terminal are coupled to the first enable signal line and data signal line DQ, for enabled according to first
Signal DFT_n_En1 and the second input signal IN2 exports preactivate signal Pre_Act；
With door 212, input terminal is coupled to the output end of the second enable signal line and latch cicuit 211, for according to second
Enable signal DFT_n_En2 and preactivate signal Pre_Act output corresponds to the third enable signal DFT_n_ of test pattern
En3。
In the embodiment shown in fig. 5, correspond to a test pattern, can be controlled with two enable signals.First
Enable signal enables the ability that the second input signal controls the setting of test pattern, and the second enable signal is to test mould
Formula carries out enabled signal.Test pattern control module is coupled to one in a plurality of data signal line, the data signal wire
It is coupled to whole n test pattern enabling units.
When the first enable signal is enabled state, the second input signal cannot be by latch signal, to test mould
The control of formula is only with the second enable signal.Since all chips of test equipment connection at this time receive same second
Enable signal, so the test pattern of all chips of test equipment connection is enabled if the second enable signal is enabled state
Unit enables the corresponding test pattern of the second enable signal according to the control output third enable signal of the second enable signal, and
Follow-up test signal is responded.
When the first enable signal is enabled state, the second input signal and the second enable signal determine test pattern together
Control.If the second input signal is not enabled state at this time, each test pattern enabling unit of chip can not be exported
Third enable signal.It is surveyed since test pattern control module 12 is arranged according to the third enable signal for corresponding to each test pattern
Die trial formula, the test pattern of chip is arranged to nothing at this time, is not responding to subsequent test command signal.
In some embodiments, the first enable signal and the second enable signal can be solved from same first input signal
Code comes out, but in further embodiments, can also first decode the first enable signal, then from subsequent first input signal
In decode the second enable signal.
By the way that two enable signals are arranged to a test pattern enabling unit, can shield if necessary to the pre- of chip
Activation is directly arranged test pattern to all chips of test equipment connection simultaneously and response follow-up test instruction letter is arranged
Number, reduce the step of needing to carry out additional all data lines output enable signal when testing each chip at the same time, improves
Control efficiency.
Fig. 6 is the schematic diagram of latch cicuit shown in Fig. 5.
With reference to Fig. 6, in a kind of exemplary embodiment of the disclosure, latch cicuit 211 may include:
Transmission gate 2111, the first control terminal are coupled to the first enable signal line, and the second control terminal passes through the first reverser coupling
It is connected to the first enable signal line, input terminal is coupled to data signal line, for exporting when the first enable signal is predetermined level
Second input signal IN2；
Second reverser 2112, input terminal are coupled to the output end of transmission gate, output end of the output end as latch cicuit,
For exporting the reverse signal of the second input signal IN2.
In the embodiment shown in fig. 6, predetermined level can be high level, and in other embodiments, predetermined level can also be with
It is low level.
Control of first enable signal to the validity of the second input signal may be implemented in control circuit shown in fig. 6.Though
So, reverser is added in the latch cicuit to realize to the reversed of the second input signal, but those skilled in the art can be with
Each signal of requirement self-setting according to each module to enable signal is 1 or 0 in other embodiments, is determined according to the actual situation
Reverser or not in fixed addition.In addition, realize the function latch cicuit hardware connection can also there are many, art technology
Personnel can be not particularly limited this with self-setting, the disclosure.
Fig. 7 is another schematic diagram of test pattern control module in an embodiment of the present disclosure.
Fig. 8 is the schematic diagram of latch cicuit shown in Fig. 7.
With reference to Fig. 7, in a kind of exemplary embodiment of the disclosure, the input terminal of latch cicuit 211 is further coupled to reset
Signal wire, control of the latch cicuit 211 also by reset signal Reset, latch cicuit 211 are also used to according to default reset signal
Reset exports preactivate signal Pre_Act.When reset signal Reset is high, no matter which kind of state is the second input signal be,
Export preactivate signal Pre_Act.The setting of test pattern is only controlled by the second enable signal in chip at this time.
With reference to Fig. 8, in the embodiment shown in fig. 7, latch cicuit 211 further includes nor gate 2113 on the basis of Fig. 6,
The input terminal of the NAND gate is coupled to output end (the i.e. output of the second reverser 2112 of reseting signal line and latch cicuit 211
End), output end is coupled to the input terminal of the second reverser 2112.
All chips are controlled by using reset signal and are only controlled by the second enable signal, can be enabled omitting to first
Whole chips are controlled under signal and the facilities of the second input signal and are only controlled by the second enable signal, improve control effect
Rate.
Fig. 9 is the control logic schematic diagram of Fig. 7 and latch cicuit shown in Fig. 8.
In the embodiment shown in fig. 9, effective enabled state of reset signal 1, the first enable signal DFT_n_En1 is
1, preactivate signal Pre_Act are defaulted as 1, and the second input signal IN2 is 1, and effective enabled state is 0.
With reference to Fig. 9, after reset signal Reset appearance, preactivate signal Pre_Act output is 1.
When the first input signal can be decoded as test mode signal, the first enable signal is decoded as enabled shape
State.The second input signal IN2 is disabled state 1 at this time, and latch cicuit exports the disabled state, i.e. preactivate signal Pre_Act
Become 0, each test pattern enabling unit is not enabled, and the test pattern of chip is arranged to nothing, not to test command signal
It is responded.
When next the first input signal that can be decoded as test mode signal arrives, the first enable signal is solved
Code is enabled state.The second input signal IN2 is enabled state 0, the preactivate signal that latch cicuit output state is 1 at this time
Pre_Act allows each test pattern enabling unit of the chip to be controlled by corresponding second enable signal DFT_n_En2 and carries out
Setting, the chip respond subsequent test command signal according to the setting of test pattern.
It should be noted that although being referred to several modules or list for acting the equipment executed in the above detailed description
Member, but this division is not enforceable.In fact, according to embodiment of the present disclosure, it is above-described two or more
Module or the feature and function of unit can embody in a module or unit.Conversely, an above-described mould
The feature and function of block or unit can be to be embodied by multiple modules or unit with further division.
Figure 10 is the schematic diagram of chip test system in the embodiment of the present disclosure.
With reference to Figure 10, in one embodiment of the present disclosure, chip test system may include:
Test equipment 2, have a plurality of physical signal line and data signal line, for corresponded respectively to by multiple groups it is multiple
The data signal line output of chip is corresponding to output test signal after the preactivate signal of chip under test；
Multiple chip testing positions 3, share the physical signal line of test equipment 2, and each chip testing position 3 passes through different numbers
It is connect according to signal wire with test equipment 2, each chip testing position 3 connects one such as Fig. 2~chip shown in Fig. 91.
In a kind of exemplary embodiment of the disclosure, physical signal line includes control signal wire CMD, chip selection signal line
CS, address signal line ADD.
In a kind of exemplary embodiment of the disclosure, test equipment 2 is also used to exporting preactivate function to chip under test
Can signal while chip output lock signal is had connected to other in addition to chip under test.
Figure 11 is the control sequential figure of chip test system in the embodiment of the present disclosure.
With reference to Figure 11, according to the line graph of Figure 10, test equipment 1 needs simultaneously when sending control signal to all cores
The chip selection signal line CS of piece sends chip selection signal, and is sent to all chips by control signal wire CMD and address signal line ADD
Signal.
In Figure 11, when first stage T1, go out on chip selection signal line CS, control signal wire CMD and address signal line ADD
Existing signal, the signal can be decoded the first enable signal DFT_n_ corresponding to test pattern n by the decoder module of chip
En1.Synchronization, the second input signal IN2 occurred on the data line corresponding to chip DUT0 and DUT3 are enabled state, can
To be identified as preactivate function, chip DUT0 and DUT3 latch preactivate signal Pre_Act, respond the signal of second stage；
Chip DUT1, DUT2, DUT4 can not export preactivate signal, not respond to follow-up signal, unless in follow-up signal
Second input signal of one enable signal and enabled state occurs simultaneously.
When second stage T2, each chip decodes the second enable signal DFT_n_En2 according to the first input signal, due to this
When chip DUT0 and DUT3 on latch circuit latches before preactivate signal, exported under the action of the second enable signal
The third enable signal of enabled test pattern n, makes chip set test pattern n for test pattern.At this time chip DUT0 and
DUT3 responds follow-up test command signal, and is carried out according to test command signal to the data-signal on data signal line
Operation.
When phase III T3, the signal occurred on chip selection signal line CS, control signal wire CMD and address signal line ADD can
To be decoded the first enable signal DFT_n_En1 corresponding to test pattern n by the decoder module of chip.Synchronization, it is corresponding
It is enabled state in the second input signal IN2 occurred on the data line of all chips, preactivate function can be identified as, respectively
Chip latches preactivate signal Pre_Act, responds the signal of second stage.
When fourth stage T4, each chip decodes the second enable signal DFT_n_En2 according to the first input signal, due to this
When each chip latch cicuit latched preactivate signal Pre_Act, therefore can be the second enable signal DFT_n_En2's
The lower third enable signal DFT_n_En3 for exporting enabled test pattern n of effect, makes each chip set test mould for test pattern
Formula n.Each chip responds follow-up test command signal, and is believed according to test command signal the data on data signal line
It number is operated.
In some embodiments, the timing of phase III T3 and fourth stage T4 can occur to power on or restart in chip
When.
The embodiment of the present disclosure corresponds to quilt by send between individually operated in the chip to multiple multiplexed signals lines
The preactivate signal for surveying chip makes chip under test respond or be not responding to follow-up test instruction according to preactivate signal, can be to the greatest extent
So that test equipment is connected more chips in the case where the I/O interface that test equipment may be saved, improves chip testing efficiency.
Person of ordinary skill in the field is it is understood that the various aspects of the utility model can be implemented as system, side
Method or program product.Therefore, the various aspects of the utility model can be with specific implementation is as follows, it may be assumed that complete hardware is real
The embodiment combined in terms of applying mode, complete Software Implementation (including firmware, microcode etc.) or hardware and software,
Here it may be collectively referred to as circuit, " module " or " system ".
In addition, above-mentioned attached drawing is only the schematic of the processing according to included by the method for the utility model exemplary embodiment
Illustrate, rather than limits purpose.It can be readily appreciated that the time that above-mentioned processing shown in the drawings did not indicated or limited these processing is suitable
Sequence.In addition, be also easy to understand, these processing, which can be, for example either synchronously or asynchronously to be executed in multiple modules.
Those skilled in the art will readily occur to the disclosure after considering specification and practicing utility model disclosed herein
Other embodiments.This application is intended to cover any variations, uses, or adaptations of the disclosure, these modifications are used
Way or adaptive change follow the general principles of this disclosure and including the disclosure it is undocumented in the art known in
Common sense or conventional techniques.The description and examples are only to be considered as illustrative, and the true scope of the disclosure and design are by weighing
Benefit requires to point out.
Claims (13)
1. a kind of chip is coupled to test equipment by physical signal line and data signal line characterized by comprising
Decoder module is coupled to the physical signal line, for the first input signal on the physical signal line into
Row decodes and exports test mode signal or test command signal, the test mode signal go out prior to the test command signal
It is existing；
Test pattern control module is coupled to the decoder module and the data signal line, for according to the test pattern
Test pattern is arranged in the second input signal on signal and the data signal line；
Instruction execution module is tested, the decoder module, the test pattern control module and the data signal line are coupled to,
For responding the test command signal according to the test pattern or being arranged to always respond institute in the test pattern
State test command signal.
2. chip as described in claim 1, which is characterized in that the decoder module includes:
Design for Measurability decoding unit, input terminal are coupled to the physical signal line, and output end includes n group enable signal line, use
In the test mode signal is decoded and exported to first input signal, the test mode signal includes corresponding to
The n group enable signal of n test pattern；
Test command signal decoding unit, input terminal is coupled to the physical signal line, for first input signal into
Row decodes and exports the test command signal.
3. chip as claimed in claim 2, which is characterized in that enable signal described in every group includes the first enable signal and second
Enable signal, enable signal line described in every group include the first enable signal line and the second enable signal line, the test pattern control
Molding block includes:
N test pattern enabling unit corresponds respectively to the n test pattern, wherein each test pattern is enabled single
Member includes:
Latch cicuit, input terminal are coupled to the first enable signal line and the data signal line, for according to described first
Enable signal and second input signal export preactivate signal；
With door, input terminal is coupled to the output end of the second enable signal line and the latch cicuit, for according to described the
Two enable signals and preactivate signal output correspond to the third enable signal of the test pattern.
4. chip as claimed in claim 3, which is characterized in that the latch cicuit includes:
Transmission gate, the first control terminal are coupled to the first enable signal line, and the second control terminal is coupled to by the first reverser
The first enable signal line, input terminal are coupled to the data signal line, for being default electricity in first enable signal
Usually export second input signal；
Second reverser, input terminal are coupled to the output end of the transmission gate, output end of the output end as the latch cicuit,
For exporting the reverse signal of second input signal as the preactivate signal.
5. chip as claimed in claim 4, which is characterized in that the input terminal of the latch cicuit is further coupled to reset signal
Line, the latch cicuit are also used to export the preactivate signal according to default reset signal.
6. chip as claimed in claim 5, which is characterized in that the latch cicuit further include:
Nor gate, input terminal are coupled to the output end of the reseting signal line and the latch cicuit, and output end is coupled to described
The input terminal of second reverser.
7. chip as described in any one of claims 1 to 6, which is characterized in that the test pattern control module is coupled to more
One in data signal line described in item.
8. such as the described in any item chips of claim 3~6, which is characterized in that the test pattern control module is according to correspondence
In the third enable signal of each test pattern, the test pattern is set.
9. chip as described in claim 1, which is characterized in that the test instruction execution module responds the test instruction letter
It number include by being operated to the data signal line.
10. chip as described in claim 1, which is characterized in that the physical signal line includes control signal wire, chip selection signal
Line, address signal line.
11. a kind of chip test system characterized by comprising
Test equipment has a plurality of physical signal line and data signal line, for having preactivate function to chip under test output
Output test signal after the signal of energy；
Multiple chip testing positions share the physical signal line of the test equipment, and each chip testing position is not by
Same data signal line is connect with the test equipment, and each chip testing position connects one as described in claim 1~9
Chip.
12. chip test system as claimed in claim 11, which is characterized in that the physical signal line includes control signal
Line, chip selection signal line, address signal line.
13. chip test system as claimed in claim 11, which is characterized in that the test equipment is also used to the quilt
It surveys chip and chip output lock letter is had connected to other in addition to chip under test while export the signal of the preactivate function
Number.
Priority Applications (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201821631053.3U CN208953667U (en) | 2018-09-28 | 2018-09-28 | Chip and chip test system |
| PCT/CN2019/106358 WO2020063413A1 (en) | 2018-09-28 | 2019-09-18 | Chip and chip test system |
| US17/211,366 US20210208196A1 (en) | 2018-09-28 | 2021-03-24 | Chip and chip test system |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201821631053.3U CN208953667U (en) | 2018-09-28 | 2018-09-28 | Chip and chip test system |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN208953667U true CN208953667U (en) | 2019-06-07 |
Family
ID=66740714
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201821631053.3U Withdrawn - After Issue CN208953667U (en) | 2018-09-28 | 2018-09-28 | Chip and chip test system |
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| Country | Link |
|---|---|
| CN (1) | CN208953667U (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109164374A (en) * | 2018-09-28 | 2019-01-08 | 长鑫存储技术有限公司 | Chip and chip test system |
| WO2020063413A1 (en) * | 2018-09-28 | 2020-04-02 | Changxin Memory Technologies, Inc. | Chip and chip test system |
-
2018
- 2018-09-28 CN CN201821631053.3U patent/CN208953667U/en not_active Withdrawn - After Issue
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109164374A (en) * | 2018-09-28 | 2019-01-08 | 长鑫存储技术有限公司 | Chip and chip test system |
| WO2020063413A1 (en) * | 2018-09-28 | 2020-04-02 | Changxin Memory Technologies, Inc. | Chip and chip test system |
| CN109164374B (en) * | 2018-09-28 | 2024-03-29 | 长鑫存储技术有限公司 | Chip and chip test system |
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