CN208938997U

CN208938997U - Flipped light emitting chip

Info

Publication number: CN208938997U
Application number: CN201821256392.8U
Authority: CN
Inventors: 刘英策; 刘兆; 李俊贤; 魏振东; 邬新根
Original assignee: Xiamen Changelight Co Ltd
Current assignee: Xiamen Changelight Co Ltd
Priority date: 2018-08-06
Filing date: 2018-08-06
Publication date: 2019-06-04
Anticipated expiration: 2028-08-06

Abstract

The utility model discloses a flipped light emitting chips, wherein the flipped light emitting chip includes a substrate and the n type semiconductor layer that successively grows from the substrate, one active area, one p type semiconductor layer, one reflecting layer, one barrier layer, one first insulating layer, one expansion electrode layer, one second insulating layer, one N-type electrode and a P-type electrode, wherein first insulating layer has an at least first passage and an at least second channel, the one first expansion electrode portion and one second expansion electrode portion of the expansion electrode layer are respectively laminated on first insulating layer, and the n type semiconductor layer is extended to through the first passage respectively and extends to the barrier layer through the second channel, wherein the second insulating layer has an at least third channel and an at least fourth lane, wherein the N-type electrode extends to described through the third channel First expansion electrode portion, the P-type electrode extend to second expansion electrode portion through the fourth lane.

Description

Flipped light emitting chip

Technical field

The utility model relates to semiconductor light-emitting-diodes, in particular to a flipped light emitting chip.

Background technique

In recent years, the flip-chip of light emitting diode and its relevant technologies have obtained advancing by leaps and bounds the development of formula, wherein root According to the difference of the reflecting material of flip-chip, flip-chip can be divided into the flip-chip and gold of ITO+DBR catoptric arrangement Belong to the flip-chip of catoptric arrangement (such as Ag/Al), wherein because metallic reflection structure (especially Ag metallic reflection structure) exists Visible-range has higher reflectivity, and therefore, metallic reflection structure is widely used in flip-chip.Also, root According to the difference of the logarithm of the insulating layer of flip-chip, flip-chip can be divided into falling for single ISO (insulation barrier) structure The flip-chip of cartridge chip and double ISO structures, for the flip-chip of single ISO structure, the flip-chip of double ISO structures Electric current can be extended more evenly, light efficiency is higher, is widely used in automotive lighting.

Fig. 1 shows the schematic cross-sectional view of the flip-chip of double ISO structures of the prior art, and wherein the flip-chip is by nine The production of road lithographic process.Specifically, the flip-chip includes a substrate 10P, an extension lamination 20P, a reflecting layer 30P, one Barrier layer 40P, a N ohmic contact layer 50P, one first insulating layer 60P, an expansion electrode layer 70P, a second insulating layer 80P with An and electrode group 90P.The extension lamination 20P includes a n type semiconductor layer 21P, an active area 22P and a P-type semiconductor Layer 23P, wherein the substrate 10P, the n type semiconductor layer 21P, the active area 22P and the p type semiconductor layer 23P It stacks gradually.The extension lamination 20P further comprises the exposed portion 24P of an at least N-type, wherein the exposed portion 24P of the N-type is certainly The p type semiconductor layer 23P extends to the n type semiconductor layer 21P through the active area 22P, with the exposure N-type semiconductor A part of surface of layer 21P.The reflecting layer 30P is laminated in the p type semiconductor layer 23P, and the barrier layer 40P is to coat The mode for stating reflecting layer 30P is laminated in the p type semiconductor layer 23P.The N ohmic contact layer 50P is to be maintained at the N-type The mode of exposed portion 24P is laminated in the n type semiconductor layer 21P.The first insulating layer 60P is laminated in the extension lamination 20P, the barrier layer 40P and the N ohmic contact layer 50P, wherein the first insulating layer 60P has an at least first passage 61P and at least a second channel 62P, wherein the first passage 61P of the first insulating layer 60P extend to it is N ohm described Contact layer 50P, the second channel 62P of the first insulating layer 60P extend to the barrier layer 40P.The expansion electrode Layer 70P includes at least one first expansion electrode portion 71P and at least one second expansion electrode portion 72P, wherein the first extension electricity Pole portion 71P is laminated in the first insulating layer 60P, and first expansion electrode portion 71P is through the first insulating layer 60P The first passage 61P extend to and be electrically connected to the N ohmic contact layer, wherein portion 72P layers of second expansion electrode Be laminated on the first insulating layer 60P, and second expansion electrode portion 72P through the first insulating layer 60P described second Channel 62P extends to and is electrically connected to the barrier layer 40P.The second insulating layer 80P is laminated in first expansion electrode Portion 71P and second expansion electrode portion 72P, and the second insulating layer 80P is filled in and is formed in the first extension electricity Gap between pole portion 71P and second expansion electrode portion 72P.The second insulating layer 80P has an at least third channel 81P and at least a fourth lane 82P expand wherein the third channel 81P of the second insulating layer 80P extends to described first Electrode portion 71P is opened up, the fourth lane 82P of the second insulating layer 80P extends to second expansion electrode portion 72P.Institute Stating electrode group 90P includes an a N-type electrode 91P and P-type electrode 92P, wherein the N-type electrode 91P is laminated in described second absolutely Edge layer 80P, and the N-type electrode 91P is extended to and is electrically connected through the third channel 81P of the second insulating layer 80P Prolong in first expansion electrode portion 71P, the P-type electrode 92P through the fourth lane 82P of the second insulating layer 80P Extend to and be electrically connected to second expansion electrode portion 72P.

The processing procedure for making the attached flip-chip shown in fig. 1 is complex comprising Mesa processing procedure, DE processing procedure, Mirror Processing procedure, Barrier processing procedure, N contact electrode processing procedure, the first insulating layer processing procedure, expansion electrode processing procedure, second insulating layer processing procedure, electricity Pole processing procedure totally nine lithographic process, this does not only result in flip-chip production cost with higher and lower production efficiency, And during making the flip-chip, the much easier stability for influencing the flip-chip and reliable of lithographic process Property.

Utility model content

One of the utility model is designed to provide a flipped light emitting chip, wherein the processing procedure of the flipped light emitting chip It can be simplified, to be conducive to improve the production efficiency of the flipped light emitting chip and reduce the manufacture of the flipped light emitting chip Cost.

One of the utility model is designed to provide a flipped light emitting chip, wherein the processing procedure of the flipped light emitting chip It can be simplified, to be conducive to improve the product yield of the flipped light emitting chip and guarantee the reliable of the flipped light emitting chip Property.

One of the utility model is designed to provide a flipped light emitting chip, wherein the flipped light emitting chip provides one One first expansion electrode portion of extension lamination and an expansion electrode layer, the expansion electrode layer directly contacts the extension lamination One n type semiconductor layer so that the first electrode extension can not only play the role of expansion electrode, but also can play Contact action, this make the flipped light emitting chip do not need setting N type ohmic contact layer be conducive in this way Simplify the processing procedure of the flipped light emitting chip.

One of the utility model is designed to provide a flipped light emitting chip, wherein the flipped light emitting chip provides one First insulating materials base, wherein first dielectric matrix material is laminated on the extension lamination layer by layer, wherein described in production During filling luminescence chip, a first passage is formed in described in such a way that segmentation etches first insulating materials base First insulating materials base, so that a part of surface of the n type semiconductor layer is exposed on the first passage, in this way Mode, can guarantee the reliability of the electric connecting relation of first expansion electrode portion and the n type semiconductor layer.

One of the utility model is designed to provide a flipped light emitting chip, wherein manufacturing the flipped light emitting chip During, first insulating materials base is etched first, secondly mistake of the etching in etching first insulating materials base The boundary layer of the n type semiconductor layer is formed in journey, in this way, a part of surface of the N type semiconductor layer It can be exposed on the first passage, to guarantee that first expansion electrode portion connects with the electrical of the n type semiconductor layer Connect the reliability of relationship.

One of the utility model is designed to provide a flipped light emitting chip, wherein manufacturing the flipped light emitting chip During, a second channel is formed in first insulation material in such a way that segmentation etches first insulating materials base Base is expected, so that a part of surface on the barrier layer of the flipped light emitting chip is exposed to the second channel, in this way Mode, can guarantee one second expansion electrode portion of the expansion electrode layer in the barrier layer electric connecting relation it is reliable Property.

One of the utility model is designed to provide a flipped light emitting chip, wherein manufacturing the flipped light emitting chip During, first insulating materials base is etched first, secondly mistake of the etching in etching first insulating materials base The boundary layer on the barrier layer is formed in journey, in this way, a part of surface on the barrier layer can be exposed In the second channel, to guarantee second expansion electrode portion in the reliability of the electric connecting relation on the barrier layer.

One of the utility model is designed to provide a flipped light emitting chip, wherein the flipped light emitting chip provides one Reflecting layer, wherein the reflective layer is laminated on a p type semiconductor layer of the extension lamination, and the reflecting layer is multilayer layer Stack structure can guarantee the reliability of the flipped light emitting chip in this way.

One of the utility model is designed to provide a flipped light emitting chip, wherein your chip of the upside-down mounting provides a resistance Barrier, wherein the barrier layer is laminated in the p type semiconductor layer, and the barrier layer in a manner of coating the reflecting layer For multilayer laminate constructions, in this way, the barrier layer can be effectively prevented the diffusion and migration in the reflecting layer, To guarantee the reliability of the flipped light emitting chip.

According to the one aspect of the utility model, the utility model provides a flipped light emitting chip comprising:

One substrate；

One extension lamination comprising a n type semiconductor layer, an active area and a p type semiconductor layer, wherein the lining Bottom, the n type semiconductor layer, the active area and the p type semiconductor layer stack gradually；

One reflecting layer, wherein the reflective layer is laminated on the p type semiconductor layer；

One barrier layer is laminated in the p type semiconductor layer in a manner of coating the reflecting layer；

One first insulating layer, is laminated in the barrier layer, wherein first insulating layer has an at least first passage An at least second channel, the first passage extend to the n type semiconductor layer, and the second channel extends to the blocking Layer；

One expansion electrode layer comprising one first expansion electrode portion and one second expansion electrode portion, wherein described first expands Opening up electrode portion has at least one first expansion electrode needle, when first expansion electrode portion is laminated in first insulating layer, The first expansion electrode needle is formed in the first passage and is electrically connected to the n type semiconductor layer, wherein described second expands Opening up electrode portion has at least one second expansion electrode needle, when second expansion electrode portion is laminated in first insulating layer, The second expansion electrode needle is formed in the second channel and is electrically connected to the barrier layer；And

One electrode group a comprising N-type electrode and a P-type electrode expand wherein the N-type electrode is electrically connected to described first Electrode portion is opened up, the P-type electrode is electrically connected to second expansion electrode portion.

One embodiment according to the present utility model, the extension lamination has at least exposed portion of semiconductor, from institute It states p type semiconductor layer and extends to the n type semiconductor layer through the active area, wherein the barrier layer has an at least barrier layer Perforation, wherein the semiconductor bare portion of the extension lamination is connected with the perforation of the barrier layer on the barrier layer, institute The semiconductor bare portion for stating barrier layer perforation and the extension lamination of first insulating layer through the barrier layer extends To the n type semiconductor layer.

One embodiment according to the present utility model, the reflecting layer are perforated with an at least reflecting layer, wherein described outer The semiconductor bare portion for prolonging lamination corresponds to the reflecting layer perforation in the reflecting layer, and the institute of the extension lamination The size for stating semiconductor bare portion is less than the size of reflecting layer perforation, so that a part of surface of the P type semiconductor layer It is exposed on the reflecting layer perforation, so that it is described to allow the barrier layer to be laminated on being exposed on for the p type semiconductor layer The surface of reflecting layer perforation.

The length and width dimensions of one embodiment according to the present utility model, the reflecting layer are less than the p type semiconductor layer Length and width dimensions are partly led so that the periphery of the p type semiconductor layer is exposed so that the barrier layer be allowed to be laminated on the p-type The periphery of body layer being exposed.

One embodiment according to the present utility model, the extension lamination has the exposed portion of an at least substrate, from the P Type semiconductor layer extends to the substrate through the active area and the n type semiconductor layer, wherein first insulating layer is with quilt The mode for being maintained at the exposed portion of the substrate is laminated in the substrate.

One embodiment according to the present utility model, surrounding of the exposed portion of substrate around the extension lamination.

One embodiment according to the present utility model, the reflecting layer are the reflecting layer of a multilayer laminate constructions.

One embodiment according to the present utility model, the reflecting layer include one first reflective metal material layer and one second Reflective metal material layer, first reflective metal material are laminated on the p type semiconductor layer, the second reflective metals material layer by layer The bed of material is laminated in the first reflective metal material layer, wherein the material of the first reflective metal material layer is selected from: aluminium (Al), The material group of silver-colored (Ag), platinum (Pt) and golden (Au) composition, wherein the material of the second reflective metal material layer is selected from: platinum (Pt), the material group of titanium (Ti), tungsten (W), nickel (Ni) composition.

One embodiment according to the present utility model, the barrier layer are the barrier layers of a multilayer laminate constructions.

One embodiment according to the present utility model, the barrier layer include one first barrier metal material layer and one second Barrier metal material layer, the first barrier metal material layer are laminated in the p-type in a manner of coating the reflecting layer and partly lead Body layer, the second barrier metal material layers are laminated on the first barrier metal material layer, wherein first barrier metal The material of material layer is selected from: the material group of nickel (Ni), titanium (Ti) and chromium (Cr) composition, the material of the second barrier metal material layer Material is selected from: the material group of platinum (Pt), titanium (Ti), tungsten (W), nickel (Ni) composition.

One embodiment according to the present utility model, the thickness range in the reflecting layer are 100nm-1000nm.

One embodiment according to the present utility model, the minimum thickness size range on the barrier layer are 0.1 μm -3 μm.

One embodiment according to the present utility model, the flipped light emitting chip further comprise a second insulating layer, It is laminated in first expansion electrode portion, second expansion electrode portion and first insulating layer, wherein second insulation Layer has an at least third channel and an at least fourth lane, and the third channel extends to first expansion electrode portion, institute It states fourth lane and extends to second expansion electrode portion, wherein there is the N type electrode an at least N-type electrode to connect needle, When the N-type electrode is laminated in the second insulating layer, the N-type electrode connection needle is formed in the third channel and electrical connection In first expansion electrode portion, wherein there is the P-type electrode an at least P-type electrode to connect needle, it is laminated in the P-type electrode When the second insulating layer, the P-type electrode connection needle is formed in the fourth lane and is electrically connected to second extension Electrode portion.

According to the other side of the utility model, the utility model further provides for the manufacturer of a flipped light emitting chip Method, wherein the manufacturing method includes the following steps:

(a) one extension lamination of stacking is in the substrate；

(b) one reflecting layer of stacking is in a p type semiconductor layer of the extension lamination；

(c) barrier layer is laminated in a manner of coating the reflecting layer in the p type semiconductor layer；

(d) stacking has one first insulating layer of an at least first passage and an at least second channel in the barrier layer, Wherein the first passage extends to a n type semiconductor layer of the extension lamination, and the second channel extends to the blocking Layer；

(e) first expansion electrode portion is formed when first insulating layer in the one first expansion electrode portion that is laminated One first expansion electrode needle is in the first passage of first insulating layer, and the first expansion electrode needle is electrically connected to The n type semiconductor layer correspondingly in the one second expansion electrode portion that is laminated when first insulating layer, forms described second The one second expansion electrode needle in expansion electrode portion is in the second channel of first insulating layer, and second extension is electric Pole needle is connected to the barrier layer；And

(f) N-type electrode is electrically connected in first expansion electrode portion and one P-type electrode of electrical connection in described second Expansion electrode portion, the flipped light emitting chip is made.

One embodiment according to the present utility model further comprises step in the step (d):

(d.1) one first insulating materials base of stacking is in the barrier layer；With

(d.2) first insulating materials base is etched, there is the first passage and the second channel to be formed First insulating layer.

One embodiment according to the present utility model, in the step (d.2), segmentation etches first insulating materials Base, to form the first passage.

One embodiment according to the present utility model, in the step (d.2), segmentation etches first insulating materials Base, to form the second channel.

One embodiment according to the present utility model etches first insulating materials base in the above-mentioned methods first, Secondly etching is formed in the boundary layer of the n type semiconductor layer when etching the first insulating materials base, is extended with being formed To the first passage of the n type semiconductor layer.

One embodiment according to the present utility model etches first insulating materials base in the above-mentioned methods first, Secondly etching is formed in the boundary layer on the barrier layer when etching the first insulating materials base, is extended to formation described The second channel on barrier layer.

One embodiment according to the present utility model uses argon gas (Ar), fluoroform in the above-mentioned methods first (CHF3) and the mixed gas of oxygen (O2) etches first insulating materials base, secondly uses argon gas (Ar), chlorine (Cl2) The boundary layer is etched with the mixed gas of any the two or three in boron chloride (BCl3).

One embodiment according to the present utility model etches the extension lamination in the step (a) to be formed from institute At least semiconductor that the p type semiconductor layer for stating extension lamination extends to the n type semiconductor layer through an active area is exposed Portion, and in the step (c) makes the barrier layer form the barrier layer perforation for being connected to the semiconductor bare portion, with In the step (d), first insulating layer extends to the N-type half through barrier layer perforation and the semiconductor bare portion Conductor layer.

One embodiment according to the present utility model etches the extension lamination in the step (a) to be formed from institute The p type semiconductor layer for stating extension lamination extends to a lining of the substrate through the active area and the n type semiconductor layer The exposed portion in bottom, in the step (d), first insulating layer is laminated in institute in a manner of being maintained at the exposed portion of the substrate State substrate.

One embodiment according to the present utility model etches in the step (a) along the surrounding of the extension lamination The extension lamination, so that first insulating layer is coated described in a manner of being laminated in the substrate in the step (d) The surrounding of extension lamination.

One embodiment according to the present utility model, in the step (b), one of the exposure p type semiconductor layer Divide surface in the reflecting layer perforation in the reflecting layer and the week of the exposure p type semiconductor layer because of the four of the reflecting layer Week, in the step (c), the barrier layer is perforated with the reflecting layer that is exposed to for being laminated in the p type semiconductor layer A part of surface and the mode of periphery of the p type semiconductor layer coat the reflecting layer.

One embodiment according to the present utility model, before the step (f), the manufacturing method further comprises step It is rapid: be laminated have a second insulating layer of an at least third channel and an at least fourth lane in first expansion electrode portion, Second expansion electrode portion and first insulating layer, wherein the third channel extends to first expansion electrode portion, The fourth lane extends to second expansion electrode portion, the N-type electrode is being laminated in institute in the step (f) When stating second insulating layer, the N-type electrode connection needle of the N-type electrode is formed in the third channel, and the N-type is electric Pole connection needle is electrically connected to first expansion electrode portion, correspondingly, the P-type electrode is being laminated in the second insulating layer When, the P-type electrode connection needle of the P type electrode is formed in the fourth lane, and P-type electrode connection needle is electrically connected It is connected to second expansion electrode portion.

Detailed description of the invention

Fig. 1 is the schematic cross-sectional view of a flip-chip of the prior art.

Fig. 2 is shown according to the section view of one of the manufacturing process of a flipped light emitting chip of a preferred embodiment of the utility model It is intended to.

Fig. 3 two is cutd open according to the manufacturing process of the flipped light emitting chip of the above-mentioned preferred embodiment of the utility model Depending on schematic diagram.

Fig. 4 A be according to the flipped light emitting chip of the above-mentioned preferred embodiment of the utility model manufacturing process three Schematic cross-sectional view.

Fig. 4 B be according to the flipped light emitting chip of the above-mentioned preferred embodiment of the utility model manufacturing process three Schematic top plan view.

Fig. 5 A be according to the flipped light emitting chip of the above-mentioned preferred embodiment of the utility model manufacturing process four Schematic cross-sectional view.

Fig. 5 B be according to the flipped light emitting chip of the above-mentioned preferred embodiment of the utility model manufacturing process four Schematic top plan view.

Fig. 6 A be according to the flipped light emitting chip of the above-mentioned preferred embodiment of the utility model manufacturing process five Schematic cross-sectional view.

Fig. 6 B be according to the flipped light emitting chip of the above-mentioned preferred embodiment of the utility model manufacturing process five Schematic top plan view.

Fig. 7 A be according to the flipped light emitting chip of the above-mentioned preferred embodiment of the utility model manufacturing process six Schematic cross-sectional view.

Fig. 7 B be according to the flipped light emitting chip of the above-mentioned preferred embodiment of the utility model manufacturing process six Schematic top plan view.

Fig. 8 A be according to the flipped light emitting chip of the above-mentioned preferred embodiment of the utility model manufacturing process seven Schematic cross-sectional view.

Fig. 8 B be according to the flipped light emitting chip of the above-mentioned preferred embodiment of the utility model manufacturing process seven Schematic top plan view.

Fig. 9 A be according to the flipped light emitting chip of the above-mentioned preferred embodiment of the utility model manufacturing process eight Schematic cross-sectional view.

Fig. 9 B be according to the flipped light emitting chip of the above-mentioned preferred embodiment of the utility model manufacturing process eight Schematic top plan view.

Figure 10 A be according to the flipped light emitting chip of the above-mentioned preferred embodiment of the utility model manufacturing process nine Schematic cross-sectional view.

Figure 10 B be according to the flipped light emitting chip of the above-mentioned preferred embodiment of the utility model manufacturing process nine Schematic top plan view.

Figure 11 A be according to the flipped light emitting chip of the above-mentioned preferred embodiment of the utility model manufacturing process ten Schematic cross-sectional view, it illustrates the overlooking states of the flipped light emitting chip.

Figure 11 B be according to the flipped light emitting chip of the above-mentioned preferred embodiment of the utility model manufacturing process ten Schematic top plan view, it illustrates the section view states of the flipped light emitting chip.

Specific embodiment

It is described below for disclosing the utility model so that those skilled in the art can be realized the utility model.It retouches below Preferred embodiment in stating is only used as illustrating, it may occur to persons skilled in the art that other obvious modifications.It is retouched following The basic principle of the utility model defined in stating can be applied to other embodiments, deformation scheme, improvement project, etc. Tongfangs The other technologies scheme of case and the spirit and scope without departing from the utility model.

It will be understood by those skilled in the art that in the exposure of the utility model, term " longitudinal direction ", " transverse direction ", "upper", The orientation of the instructions such as "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom" "inner", "outside" or position are closed System is to be based on the orientation or positional relationship shown in the drawings, and is merely for convenience of describing the present invention and simplifying the description, without It is that the device of indication or suggestion meaning or element must have a particular orientation, be constructed and operated in a specific orientation, therefore on Stating term should not be understood as limiting the present invention.

It is understood that term " one " is interpreted as " at least one " or " one or more ", i.e., in one embodiment, The quantity of one element can be one, and in a further embodiment, the quantity of the element can be it is multiple, term " one " is no It can be interpreted as the limitation to quantity.

With reference to attached drawing 11A and Figure 11 B of the Figure of description of the utility model, according to a preferred embodiment of the utility model A flipped light emitting chip be disclosed for and be set forth in following description, wherein the flipped light emitting chip include a substrate 10, an extension lamination 20, a reflecting layer 30, a barrier layer 40, one first insulating layer 50, an expansion electrode layer 60, one second are exhausted Edge layer 70 and an electrode group 80.

Attached drawing 2 further illustrates the manufacturing process of the flipped light emitting chip to Figure 11 B, in following description, By further describe and disclose in conjunction with the manufacturing process of the flipped light emitting chip flipped light emitting chip the substrate 10, The extension lamination 20, the reflecting layer 30, the barrier layer 40, first insulating layer 50, the expansion electrode layer 60, institute State the relationship between second insulating layer 70 and the electrode group 80.

The section view state of the substrate 10 is shown with reference to attached drawing 2.Institute of the type of the substrate 10 in the utility model State unrestricted in flipped light emitting chip, such as the substrate 10 can be but not limited to aluminium oxide (Al2O3) substrate, carbonization Silicon (SiC) substrate, silicon (Si) substrate, gallium nitride (GaN) substrate, GaAs (GaAs) substrate and gallium phosphide (GaP) substrate.

With reference to attached drawing 3, the extension lamination 20 further comprises a n type semiconductor layer 21, an active area 22 and a P Type semiconductor layer 23, wherein the n type semiconductor layer 21 is grown on the substrate 10, so that the n type semiconductor layer 21 is laminated In the substrate 10, wherein the active area 22 is grown on the n type semiconductor layer 21, so that the active area 22 is laminated in institute N type semiconductor layer 21 is stated, wherein the p type semiconductor layer 23 is grown on the active area 22, so that the p type semiconductor layer 23 It is laminated in the active area 22.

It is noted that in the flipped light emitting chip of the utility model, on the substrate 10 described in stacking The mode of extension lamination 20 is unrestricted, such as in this preferable examples of the flipped light emitting chip shown in attached drawing 11B, It can use metallo-organic compound chemical gaseous phase deposition equipment (Metal-organic Chemical Vapor Deposition, MOCVD) from the substrate 10 grow the N type semiconductor layer 21, from the n type semiconductor layer 21 grow institute It states active area 22, grow the p type semiconductor layer 23 from the active area 22.

With reference to attached drawing 4A and Fig. 4 B, the extension lamination 20 further has at least exposed portion 24 of semiconductor, wherein institute It states semiconductor bare portion 24 and extends to the n type semiconductor layer 21 through the active area 22 from the p type semiconductor layer 23, with A part of surface of the n type semiconductor layer 21 is set to be exposed on the semiconductor bare portion 24.

It preferably, can be by etching the extension lamination after the extension lamination 20 is laminated in the substrate 10 20 mode forms the semiconductor bare portion 24.Specifically, inductively coupled plasma (Inductively can be used Coupled Plasma, ICP) successively the p type semiconductor layer 12 to the extension lamination 20 and the active area 13 carry out Dry etching is extended to described in the n type semiconductor layer 21 from the p type semiconductor layer 23 through the active area 22 with being formed Semiconductor bare portion 24.

In this preferable examples of the flipped light emitting chip shown in attached drawing 11A and Figure 11 B, the N type semiconductor A part of layer 21 is also etched, so that the semiconductor bare portion 24 is from the p type semiconductor layer 23 through the active area 22 The middle part of the n type semiconductor layer 21 is extended to, so that the n type semiconductor layer 21 corresponds to the semiconductor bare The thickness in portion 24 is less than the thickness of the other parts of the n type semiconductor layer 21.

Preferably, with reference to attached drawing 5A and Fig. 5 B, the extension lamination 20 further has the exposed portion 25 of a substrate, wherein The exposed portion 25 of substrate is at the edge of the extension lamination 20 from the p type semiconductor layer 23 through the active area 22 and institute It states n type semiconductor layer 21 and extends to the substrate 10, with the edge of the exposure substrate 10.Preferably, the exposed portion of the substrate 25 are looped around one week of the extension lamination 20, so that the periphery of the substrate 10 is exposed on the exposed portion of the substrate 25。

In a preferable examples of the flipped light emitting chip of the utility model, it is folded that the extension can be etched first The middle part of layer 20 is to form the semiconductor bare portion 24, and secondly the periphery of the etching extension lamination 20 is to form the substrate Exposed portion 25.In another preferable examples of the flipped light emitting chip of the utility model, it can etch first described outer Prolong the periphery of lamination 20 to form the exposed portion 25 of the substrate, secondly the middle part of the etching extension lamination 20 is to form described half The exposed portion 24 of conductor.Preferably, the semiconductor bare portion 24 of the extension lamination 20 and the exposed portion 25 of the substrate can be with It is formed the middle part for etching the extension lamination 20 simultaneously and by way of periphery.

It is noted that although the flipped light emitting chip shown in attached drawing 2 to Figure 11 B this preferable examples In, the semiconductor bare portion 24 of the extension lamination 20 is formed in the middle part of the extension lamination 20, and practical new at this In other possible examples of the flipped light emitting chip of type, the semiconductor bare portion 24 can also be formed in the extension The edge of lamination 20.That is, the flipped light emitting of the specific location in the semiconductor bare portion 24 in the utility model It is unrestricted in chip.

With reference to attached drawing 6A and Fig. 6 B, the reflecting layer 30 is grown from the p type semiconductor layer 23 of the extension lamination 20, So that the reflecting layer 30 is laminated in the p type semiconductor layer 23 of the extension lamination 20.The reflecting layer 30 has at least One reflecting layer perforation 31, wherein the semiconductor bare portion 24 of the extension lamination 20 corresponds to the described of the reflecting layer 30 Reflecting layer perforation 31, so that the semiconductor bare portion 24 of the extension lamination 20 and the reflection in the reflecting layer 30 Layer perforation 31 is interconnected.Preferably, the shape and the extension lamination 20 of the reflecting layer perforation 31 in the reflecting layer 30 The semiconductor bare portion 24 shape it is consistent, and the reflecting layer 30 the reflecting layer perforation 31 size be greater than institute The size in the semiconductor bare portion 24 of extension lamination 20 is stated, in this way, is laminated in institute in the reflecting layer 30 After the p type semiconductor layer 23 for stating extension lamination 20, a part of surface of the p type semiconductor layer 23 is exposed on described The reflecting layer perforation 31 in reflecting layer 30.

It is noted that although the flipped light emitting chip shown in attached drawing 5A to Fig. 6 B this preferable example Described in extension lamination 20 the semiconductor bare portion 24 shape and the reflecting layer 30 reflecting layer perforation 31 Shape is circle, but art technology it should be understood that the extension lamination 20 shown in attached drawing 5A to Fig. 6 B institute The shape for stating the shape in semiconductor bare portion 24 and the reflecting layer perforation 31 in the reflecting layer 30 is only citing, to be used for It discloses and illustrates the content and feature of the flipped light emitting chip of the utility model, and be not construed as to the utility model The flipped light emitting chip content and range limitation.

Preferably, with reference to attached drawing 6A and Fig. 6 B, the length and width dimensions in the reflecting layer 30 are less than the institute of the extension lamination 20 The length and width dimensions of p type semiconductor layer 23 are stated, in this way, being laminated in the p-type half of the extension lamination 20 in the reflecting layer 30 After conductor layer 23, the periphery of the extension lamination 20 can not covered by the reflecting layer 30, with described in the subsequent permission Barrier layer 40 coats the reflecting layer 30.

It is noted that in other examples of the flipped light emitting chip of the utility model, the reflecting layer 30 Length and width dimensions can also be identical with the length and width dimensions of the p type semiconductor layer 23 of the extension lamination 20, it is described subsequent Barrier layer 40 can coat the reflecting layer 30 by way of being grown on the substrate 10.

Further, the reflecting layer 30 is a multilayer laminate constructions, wherein the reflecting layer 30 includes one first anti- Metal material layer and one second reflective metal material layer are penetrated, wherein the first reflective metal material layer in the reflecting layer 30 is raw It is longer than the p type semiconductor layer 23 of the extension lamination 20, and forms the material choosing of the first reflective metal material layer From: the material group of aluminium (Al), silver-colored (Ag), platinum (Pt) and golden (Au) composition, so that the first reflective metal material layer has There is good reflection characteristic, wherein the second reflective metal material layer in the reflecting layer 30 is grown on the first reflection gold Belong to material layer, and the material for forming the second reflective metal material layer is selected from: platinum (Pt), titanium (Ti), tungsten (W), nickel (Ni) The material group of composition, so that the second reflective metal material layer has good blocking feature, so that second reflection Metal material layer prevents the first reflective metal material layer from occurring in a manner of being laminated in the first reflective metal material layer The bad phenomenon of diffusion and migration, this is especially important for the stability for guaranteeing the reflecting layer 30.

The thickness range in the reflecting layer 30 is 100nm-1000nm (including 100nm and 1000nm), to avoid because described in The thickness in reflecting layer 30 is excessively thin and influences the reflecting properties in the reflecting layer 30, and avoids the thickness because of the reflecting layer 30 blocked up And generate the larger stress for causing the reflecting layer 30 to be peeled off.Preferably, the thickness range in the reflecting layer 30 is 100nm- 200nm.Specifically, the thickness in the reflecting layer 30 is 150nm.

It is raw from the p type semiconductor layer 23 of the extension lamination 20 and the reflecting layer 30 with reference to attached drawing 7A and Fig. 7 B The long barrier layer 40, to make the barrier layer 40 be laminated in the extension lamination 20 in a manner of coating the reflecting layer 30 The p type semiconductor layer 23.The barrier layer 40 is electrically connected to the p type semiconductor layer 23 of the extension lamination 20.It is described Barrier layer 40 has at least barrier layer perforation 41, wherein the semiconductor bare portion 24 of the extension lamination 20 corresponds to institute The barrier layer perforation 41 for stating barrier layer 40, so that the semiconductor bare portion 24 of the extension lamination 20 and the blocking The barrier layer perforation 41 of layer 40 is interconnected.Preferably, the barrier layer 40 the barrier layer perforation 41 shape with The shape in the semiconductor bare portion 24 of the extension lamination 20 is consistent.

Because the size of the reflecting layer perforation 31 in the reflecting layer 30 is greater than the described of extension lamination 20 and partly leads The size in the exposed portion 24 of body, so that a part of surface of the p type semiconductor layer 23 of the extension lamination 20 is exposed Reflecting layer perforation 31 in the reflecting layer 30, and then the barrier layer 40 can be laminated in the extension lamination 20 The surface of the reflecting layer perforation 31 for being exposed on the reflecting layer 30 of the p type semiconductor layer 23.In addition, because institute State reflecting layer 30 length and width dimensions be less than the extension lamination 20 the p type semiconductor layer 23 length and width dimensions so that The peripheral edge surface of the p type semiconductor layer 23 of the extension lamination 20 is exposed on the outside in the reflecting layer 30, Jin Ersuo The peripheral edge surface of the p type semiconductor layer 23 of the extension lamination 20 can be laminated in by stating barrier layer 40.Therefore, in this reality In this preferable examples with the novel flipped light emitting chip, because the barrier layer 40 can be laminated in the extension and fold Layer 20 the p type semiconductor layer 23 be exposed on the reflecting layer 30 the reflecting layer perforation 31 surface and be laminated in The peripheral edge surface of the p type semiconductor layer 23 of the extension lamination 20 being exposed on outside the reflecting layer 30, therefore, institute State the p type semiconductor layer that barrier layer 40 can be laminated in the extension lamination 20 in a manner of coating the reflecting layer 30 23。

Further, the barrier layer 40 is a multilayer laminate constructions, wherein the barrier layer 40 includes one first resistance Keep off metal material layer and one second barrier metal material layer, wherein the first barrier metal material layer on the barrier layer 40 with The mode for coating the reflecting layer 30 is laminated in the P type semiconductor layer 23 of the extension lamination 20, and forms described The material of one barrier metal material layer is selected from: the material group of nickel (Ni), titanium (Ti) and chromium (Cr) composition, so that described first Barrier metal material layer has good adhesion characteristics, wherein the second barrier metal material layer on the barrier layer 40 is grown In the first barrier metal material layer, and the material for forming the second barrier metal material layer is selected from: platinum (Pt), titanium (Ti), the material group of tungsten (W), nickel (Ni) composition, so that the second barrier metal material layer has good barrier properties, To prevent the reflecting layer 30 from the bad phenomenon for spreading or migrating occur, this is for guaranteeing that the stability in the reflecting layer 30 is come Say it is especially important.

That is, the barrier layer 40 coats the reflecting layer 20 completely, wherein the minimum thickness on the barrier layer 40 Size range is 0.1 μm -3 μm (including 0.1 μm and 3 μm), is unable to fully to avoid because the thickness on the barrier layer 40 is too small Cladding, and avoid causing the barrier layer 40 bad phenomenon of extinction occur because the thickness on the barrier layer 40 is excessive.In addition, The thickness on the barrier layer 40 is 3 μm -15 μm thicker than the thickness in the reflecting layer 20.Preferably, the barrier layer 40 Thickness it is 5 μm -12 μm thicker than the thickness in the reflecting layer 20.Specifically, the thickness on the barrier layer 40 It is 8 μm thicker than the thickness in the reflecting layer 20.

It is noted that under normal conditions, the minimum thickness on the barrier layer 40 is coated having a size of the barrier layer 40 The part of the side wall in the reflecting layer 30, wherein the side wall in the reflecting layer 30 can be the reflecting layer 30 be used to form it is described The inner wall of reflecting layer perforation 31, is also possible to the periphery wall in the reflecting layer 30.

With reference to attached drawing 8A and Fig. 8 B, first insulating layer 50 is laminated in the barrier layer 40, and described first insulate The semiconductor bare portion 24 of barrier layer perforation 41 and the extension lamination 20 of the layer 50 through the barrier layer 40 extends To the n type semiconductor layer 21 of the extension lamination 20.Preferably, first insulating layer 50 is further folded through the extension The exposed portion 25 of the substrate of layer 20 extends to the substrate 10, to coat the extension lamination 20 by first insulating layer 50 With the barrier layer 40.First insulating layer 50 has an at least first passage 51 and an at least second channel 52, wherein institute The mode for stating first passage 51 and the second channel 52 is formed, wherein the first passage 51 of first insulating layer 50 The n type semiconductor layer 21 of the extension lamination 20 is extended to, so that a part of surface of the n type semiconductor layer 21 is sudden and violent It is exposed at the first passage 51, wherein the second channel 52 of first insulating layer 50 extends to the barrier layer 40, with A part of surface on the barrier layer 40 is set to be exposed on the second channel 52.

Specifically, firstly, in the substrate 10, the n type semiconductor layer 21 of the extension lamination 20 and the resistance Barrier 40 grows one first insulating materials base.Preferably, the material for forming first insulating materials base is selected from: titanium dioxide The material that silicon (SiO2), silicon nitride (SiN), titanium dioxide (TiO2), tantalum pentoxide (Ta2O5) and magnesium fluoride (MgF) form Group.Secondly, etching first insulating materials base, so that first insulating materials base forms first insulating layer 50, and form the first passage 51 and the second channel 52 of first insulating layer 50.That is, forming described the The material of one insulating layer 50 is selected from: silica (SiO2), silicon nitride (SiN), titanium dioxide (TiO2), tantalum pentoxide (Ta2O5) and magnesium fluoride (MgF) composition material group.

Preferably, in a preferable examples of the flipped light emitting chip of the utility model, to be segmented the side of etching Formula etches first insulating materials base, to form the first passage 51 of first insulating layer 50.Specifically, Firstly, the mixed gas using argon gas (Ar), fluoroform (CHF3) and oxygen (O2) etches first insulating materials base. It is understood that etching the mistake of the first insulating materials base in the mixed gas using argon gas, fluoroform and oxygen It, can be in the surface shape of the n type semiconductor layer 21 when the N type semiconductor layer 21 contact of extension lamination 20 described in Cheng Zhongyu At boundary layer.Secondly, using the mixing of any the two or three in argon gas (Ar), chlorine (Cl2) and boron chloride (BCl3) Boundary layer described in gas etching, to form the first passage 51, and in this way, the institute of the extension lamination 20 A part of surface for stating n type semiconductor layer 21 can be exposed on the first passage 51.

Correspondingly, first insulating materials base is etched in a manner of being segmented etching, to form first insulating layer 50 second channel 52.Specifically, firstly, using argon gas (Ar), fluoroform (CHF3) and oxygen (O2) mixing First insulating materials base described in gas etching.It is understood that in the mixed gas using argon gas, fluoroform and oxygen It, can be in the surface shape on the barrier layer 40 when being contacted during etching first insulating materials base with the barrier layer 40 At boundary layer.Secondly, using the mixing of any the two or three in argon gas (Ar), chlorine (Cl2) and boron chloride (BCl3) Boundary layer described in gas etching, to form the second channel 52, and in this way, one of the barrier layer 40 Point surface can be exposed on the second channel 52.

With reference to attached drawing 9A and Fig. 9 B, the expansion electrode layer 60 includes one first expansion electrode portion 61 and one second extension electricity Pole portion 62, wherein first expansion electrode portion 61 and second expansion electrode portion 62 are laminated respectively in a manner of being spaced apart from each other In first insulating layer 50, and the first passage 51 of first expansion electrode portion 61 through first insulating layer 50 The n type semiconductor layer 21 of the extension lamination 20 is extended to and is electrically connected to, second expansion electrode portion 62 is through institute The second channel 52 for stating the first insulating layer 50 extends to and is electrically connected to the barrier layer 40.

Specifically, first expansion electrode portion 61 has at least one first expansion electrode needle 611, wherein described the When one expansion electrode portion 61 is laminated in first insulating layer 50, the first expansion electrode needle 611 is formed in and is maintained at The first passage 51 of first insulating layer 50, at this point, the first expansion electrode needle 611 directly with the extension lamination 20 n type semiconductor layer 21 contacts so that first expansion electrode portion 61 through first insulating layer 50 described the One channel 51 extends to and is electrically connected to the n type semiconductor layer 21 of the extension lamination 20.Correspondingly, described second expands Opening up electrode portion 62 has at least one second expansion electrode needle 621, wherein being laminated in described the in second expansion electrode portion 62 When one insulating layer 50, the second expansion electrode needle 621 is formed in and is maintained at described the second of first insulating layer 50 Channel 52, at this point, the second expansion electrode needle 621 is directly contacted with the barrier layer 40, so that second expansion electrode Portion 62 extends to and is electrically connected to the barrier layer 40 through the second channel 52 of first insulating layer 50.

It is noted that first expansion electrode portion 61 and second expansion electrode of the expansion electrode layer 60 The material in portion 62 is metal material, so that first expansion electrode portion 61 and second expansion electrode portion 62 have well Characteristics of electrical conductivity.For example, forming the material in first expansion electrode portion 61 and second expansion electrode portion 62 can select From: the material group of golden (Au), aluminium (Al), cobalt (Cu), platinum (Pt), titanium (Ti) and chromium (Cr) composition.

With reference to attached drawing 10A and Figure 10 B, second insulating layer 70 described in lamination expands in described the first of the expansion electrode layer 60 Electrode portion 61 and second expansion electrode portion 62 and first insulating layer 50 are opened up, to be isolated by the second insulating layer 70 First expansion electrode portion 61 and second expansion electrode portion 62.The second insulating layer 70 has an at least third channel 71 and at least one fourth lane 72, wherein the third channel 71 of the second insulating layer 70 extends to the expansion electrode layer 60 first expansion electrode portion 61, so that a part of surface in first expansion electrode portion 61 is exposed on described second The third channel 71 of insulating layer 70, wherein the fourth lane 72 of the second insulating layer 72 extends to the extension Second expansion electrode portion 62 of electrode layer 60, so that a part of surface in second expansion electrode portion 62 is exposed on institute State the fourth lane 72 of second insulating layer 70.

Preferably, the material for forming the second insulating layer 70 is consistent with the material for forming first insulating layer 50, that is, The material for forming the second insulating layer 70 is selected from: silica (SiO2), silicon nitride (SiN), titanium dioxide (TiO2), five oxygen Change the material group of two tantalums (Ta2O5) and magnesium fluoride (MgF) composition.

With reference to attached drawing 11A and Figure 11 B, the electrode group 80 includes a N-type electrode 81 and a P-type electrode 82, wherein described N-type electrode 81 and the P-type electrode 82 are respectively laminated on the second insulating layer 70, and the N-type electrode 81 is through described The third channel 71 of two insulating layers 70 extends to and is electrically connected to the first extension electricity of the expansion electrode layer 60 Pole portion 61, the P-type electrode 82 extend to and are electrically connected to through the fourth lane 72 of the second insulating layer 70 described Second expansion electrode portion 62 of expansion electrode layer 60.

Specifically, there is the N-type electrode 81 an at least N-type electrode to connect needle 811, wherein in the N-type electrode 81 When being laminated in the second insulating layer 70, the N-type electrode connection needle 811 is formed in and is maintained at the second insulating layer 70 The third channel 71, at this point, the N-type electrode connection needle 811 directly contacted with first expansion electrode portion 61, with Make the N-type electrode 81 extend to and be electrically connected to described first through the third channel 71 of the second insulating layer 70 to expand Open up electrode portion 61.Correspondingly, there is the P-type electrode 82 an at least P-type electrode to connect needle 821, wherein in the P-type electrode 82 When being laminated in the second insulating layer 70, the P-type electrode connection needle 821 is formed in and is maintained at the second insulating layer 70 The fourth lane 72, at this point, the P-type electrode connection needle 821 directly contacted with second expansion electrode portion 62 so that The P-type electrode 82 extends to and is electrically connected to second extension through the fourth lane 72 of the second insulating layer 70 Electrode portion 62.

It is noted that the material for forming the N-type electrode 81 and the P-type electrode 82 is metal material, so that institute Stating N-type electrode 81 and the P-type electrode 82 has good characteristics of electrical conductivity.For example, forming the N-type electrode 81 and the P The material of type electrode 82 can be selected from: the material that golden (Au), aluminium (Al), cobalt (Cu), platinum (Pt), titanium (Ti) and chromium (Cr) form Group.

According to the other side of the utility model, the utility model further provides for the manufacturer of the flipped light emitting chip Method, wherein the manufacturing method includes the following steps:

(a) extension lamination 20 is laminated in the substrate 10；

(b) reflecting layer 30 is laminated in the p type semiconductor layer 23 of the extension lamination 20；

(c) barrier layer 40 is laminated in a manner of coating the reflecting layer 30 in the p type semiconductor layer 23；

(d) stacking described first at least one described first passage 51 and at least one second channel 52 is exhausted Edge layer 50 is in the barrier layer 40, wherein the first passage 51 extends to the n type semiconductor layer of the extension lamination 20 21, the second channel 52 extends to the barrier layer 40；

(e) in stacking first expansion electrode portion 61 when first insulating layer 50, the first extension electricity is formed The first expansion electrode needle 611 in pole portion 61 is in the first passage 51 of first insulating layer 50, and described first Expansion electrode needle 611 is electrically connected to the n type semiconductor layer 21, correspondingly, in stacking second expansion electrode portion 62 in institute When stating the first insulating layer 50, the second expansion electrode needle 621 for forming second expansion electrode portion 62 is exhausted in described first The second channel 52 of edge layer 50, and the second expansion electrode needle 621 is connected to the barrier layer 50；And

(f) N-type electrode 81 is electrically connected in first expansion electrode portion 61 and is electrically connected the P type electrode 82 in second expansion electrode portion 62, the flipped light emitting chip is made.

Further, further comprise step in the step (d):

(d.1) stacking first insulating materials base is in the barrier layer 40；With

(d.2) first insulating materials base is etched, there is the first passage 51 and the second channel to be formed 52 first insulating layer 50.

Further, in the step (d.2), segmentation etching first insulating materials base, described in being formed First passage 51.In the step (d.2), segmentation etching first insulating materials base, to form the second channel 52。

In the above-mentioned methods, first insulating materials base is etched first, and secondly etching is etching first insulation It is formed in the boundary layer of the n type semiconductor layer 21 when material base layer, is extended to described in the n type semiconductor layer 21 with being formed First passage 51.In the above-mentioned methods, first insulating materials base is etched first, and secondly etching is etching described first absolutely The boundary layer on the barrier layer 40 is formed in when edge material base layer, to form the second channel for extending to the barrier layer 40 52.Preferably, in the above-mentioned methods, it is carved first using the mixed gas of argon gas (Ar), fluoroform (CHF3) and oxygen (O2) First insulating materials base is lost, secondly using any the two in argon gas (Ar), chlorine (Cl2) and boron chloride (BCl3) Or the mixed gas of three etches the boundary layer.

Further, in the step (a), the extension lamination 20 is etched to form the institute from the extension lamination 20 State at least one described semiconductor bare that p type semiconductor layer 23 extends to the n type semiconductor layer 21 through the active area 22 Portion 24, and in the step (c), the barrier layer for making the barrier layer 40 form the connection semiconductor bare portion 24 is worn Hole 41, in the step (d), first insulating layer 50 is through barrier layer perforation 41 and the semiconductor bare portion 24 Extend to the n type semiconductor layer 21.

Further, in the step (a), the extension lamination 20 is etched to form the institute from the extension lamination 20 It is naked to state the substrate that p type semiconductor layer 23 extends to the substrate 10 through the active area 22 and the n type semiconductor layer 21 Dew portion 25, in the step (d), first insulating layer 50 is laminated in a manner of being maintained at the exposed portion 25 of the substrate In the substrate 10.Preferably, in the step (a), the extension lamination is etched along the surrounding of the extension lamination 20 20, so that first insulating layer 50 coats the extension in a manner of being laminated in the substrate 10 in the step (d) The surrounding of lamination 20.

Further, in the step (b), a part of surface of the exposure p type semiconductor layer 23 is in the reflection The week of the reflecting layer perforation 31 of layer 30 and the exposure p type semiconductor layer 23 because of the reflecting layer 30 surrounding, with In the step (c), the barrier layer 40 is exposed to reflecting layer perforation 31 be laminated in the p type semiconductor layer 23 The mode of the periphery of a part of surface and the p type semiconductor layer 23 coats the reflecting layer 30.

Further, before the step (f), the manufacturing method further comprises step: stacking has at least one The second insulating layer 70 of a third channel 71 and at least one fourth lane 72 is in first expansion electrode Portion 61, second expansion electrode portion 62 and first insulating layer 50, wherein the third channel 71 extends to described first Expansion electrode portion 61, the fourth lane 72 extend to second expansion electrode portion 62, in the step (f), in layer The N-type electrode 81 is folded when the second insulating layer 70, formed the N-type electrode 81 the N-type electrode connection needle 811 in The third channel 71, and N-type electrode connection needle 811 is electrically connected to first expansion electrode portion 61, correspondingly, The P-type electrode 82 is laminated when the second insulating layer 70, forms the P-type electrode connection needle of the P-type electrode 82 821 in the fourth lane 72, and P-type electrode connection needle 821 is electrically connected to second expansion electrode portion 62.

It is worth noting that, the flipped light emitting chip shown in the accompanying drawings of the utility model the substrate 10, The n type semiconductor layer 21, the active area 22, the p type semiconductor layer 23, the reflecting layer 30, the barrier layer 40, First insulating layer 50, first expansion electrode portion 61, second expansion electrode portion 62, the second insulating layer 70, The thickness of the N-type electrode 81 and the P-type electrode 82 is merely illustrative, is not offered as the substrate 10, the N-type semiconductor Layer 21, the active area 22, the p type semiconductor layer 23, the reflecting layer 30, the barrier layer 40, first insulating layer 50, first expansion electrode portion 61, second expansion electrode portion 62, the second insulating layer 70,81 and of the N-type electrode The actual thickness of the P-type electrode 82.Also, the substrate 10, the n type semiconductor layer 21, the active area 22, the P Type semiconductor layer 23, the reflecting layer 30, the barrier layer 40, first insulating layer 50, first expansion electrode portion 61, It is true between second expansion electrode portion 62, the second insulating layer 70, the N-type electrode 81 and the P-type electrode 82 Ratio is also unlike shown in the accompanying drawings.In addition, the size of the N-type electrode 81 and the P-type electrode 82 and it is described fall The dimension scale of other layers of dress luminescence chip is also not limited to shown in the accompanying drawings such.

It will be appreciated by those skilled in the art that above embodiments are only for example, wherein the feature of different embodiments It can be combined with each other, do not explicitly pointed out in the accompanying drawings with obtaining being readily conceivable that according to the content that the utility model discloses Embodiment.

It should be understood by those skilled in the art that foregoing description and the embodiments of the present invention shown in the drawings are only used as It illustrates and is not intended to limit the utility model.The purpose of this utility model completely and effectively realizes.The function of the utility model Energy and structural principle show and illustrate in embodiment, under without departing from the principle, the embodiments of the present invention Can there are any deformation or modification.

Claims

1. flipped light emitting chip characterized by comprising

One substrate；

One extension lamination comprising a n type semiconductor layer, an active area and a p type semiconductor layer, wherein the substrate, institute N type semiconductor layer, the active area and the p type semiconductor layer is stated to stack gradually；

One first insulating layer, is laminated in the barrier layer, wherein first insulating layer is with an at least first passage and extremely A few second channel, the first passage extend to the n type semiconductor layer, and the second channel extends to the barrier layer；

One expansion electrode layer comprising one first expansion electrode portion and one second expansion electrode portion, wherein the first extension electricity Pole portion has at least one first expansion electrode needle, described when first expansion electrode portion is laminated in first insulating layer First expansion electrode needle is formed in the first passage and is electrically connected to the n type semiconductor layer, wherein the second extension electricity Pole portion has at least one second expansion electrode needle, described when second expansion electrode portion is laminated in first insulating layer Second expansion electrode needle is formed in the second channel and is electrically connected to the barrier layer；And

One electrode group comprising a N-type electrode and a P-type electrode, wherein the N-type electrode is electrically connected to the first extension electricity Pole portion, the P-type electrode are electrically connected to second expansion electrode portion.

2. flipped light emitting chip according to claim 1, wherein the extension lamination has at least exposed portion of semiconductor, It extends to the n type semiconductor layer through the active area from the p type semiconductor layer, wherein the barrier layer has at least one Barrier layer perforation, wherein the semiconductor bare portion of the extension lamination is connected with the perforation of the barrier layer on the barrier layer It is logical, the semiconductor bare portion of the barrier layer perforation and the extension lamination of first insulating layer through the barrier layer Extend to the n type semiconductor layer.

3. flipped light emitting chip according to claim 2, wherein the reflecting layer is perforated with an at least reflecting layer, wherein The reflecting layer that the semiconductor bare portion of the extension lamination corresponds to the reflecting layer is perforated, and the extension is folded The size in the semiconductor bare portion of layer is less than the size of reflecting layer perforation, so that one of the p type semiconductor layer Point surface is exposed on the reflecting layer perforation, so that the barrier layer be allowed to be laminated on being exposed for the p type semiconductor layer On the surface of reflecting layer perforation.

4. flipped light emitting chip according to claim 3 is partly led wherein the length and width dimensions in the reflecting layer are less than the p-type The length and width dimensions of body layer, so that the periphery of the p type semiconductor layer is exposed, so that the barrier layer be allowed to be laminated on the P The periphery of type semiconductor layer being exposed.

5. flipped light emitting chip according to claim 1, wherein the extension lamination has the exposed portion of an at least substrate, The substrate is extended to through the active area and the n type semiconductor layer from the p type semiconductor layer, wherein first insulation Layer is laminated in the substrate in a manner of being maintained at the exposed portion of the substrate.

6. flipped light emitting chip according to claim 2, wherein the extension lamination has the exposed portion of an at least substrate, The substrate is extended to through the active area and the n type semiconductor layer from the p type semiconductor layer, wherein first insulation Layer is laminated in the substrate in a manner of being maintained at the exposed portion of the substrate.

7. flipped light emitting chip according to claim 3, wherein the extension lamination has the exposed portion of an at least substrate, The substrate is extended to through the active area and the n type semiconductor layer from the p type semiconductor layer, wherein first insulation Layer is laminated in the substrate in a manner of being maintained at the exposed portion of the substrate.

8. flipped light emitting chip according to claim 4, wherein the extension lamination has the exposed portion of an at least substrate, The substrate is extended to through the active area and the n type semiconductor layer from the p type semiconductor layer, wherein first insulation Layer is laminated in the substrate in a manner of being maintained at the exposed portion of the substrate.

9. flipped light emitting chip according to claim 5, wherein the exposed portion of the substrate is around the four of the extension lamination Week.

10. flipped light emitting chip according to claim 6, wherein the exposed portion of the substrate is around the four of the extension lamination Week.

11. flipped light emitting chip according to claim 7, wherein the exposed portion of the substrate is around the four of the extension lamination Week.

12. flipped light emitting chip according to claim 8, wherein the exposed portion of the substrate is around the four of the extension lamination Week.

13. flipped light emitting chip according to any one of claim 1 to 12, wherein the reflecting layer is a multilayer layer The reflecting layer of stack structure.

14. flipped light emitting chip according to any one of claim 1 to 12, wherein the barrier layer is a multilayer layer The barrier layer of stack structure.

15. flipped light emitting chip according to claim 13, wherein the barrier layer is the resistance of a multilayer laminate constructions Barrier.

16. flipped light emitting chip according to any one of claim 1 to 12, wherein the thickness model in the reflecting layer It encloses for 100nm-1000nm.

17. flipped light emitting chip according to any one of claim 1 to 12, wherein the minimum thickness ruler on the barrier layer Very little range is 0.1 μm -3 μm.

18. flipped light emitting chip according to any one of claim 1 to 12, the flipped light emitting chip further comprise One second insulating layer is laminated in first expansion electrode portion, second expansion electrode portion and first insulating layer, Described in second insulating layer there is an at least third channel and an at least fourth lane, the third channel to extend to described first Expansion electrode portion, the fourth lane extend to second expansion electrode portion, wherein the N-type electrode has an at least N-type Electrode connects needle, and when the N-type electrode is laminated in the second insulating layer, N-type electrode connection needle is formed in described the Triple channel and it is electrically connected to first expansion electrode portion, wherein there is the P-type electrode an at least P-type electrode to connect needle, When the P-type electrode is laminated in the second insulating layer, the P-type electrode connection needle is formed in the fourth lane and electrical connection In second expansion electrode portion.

19. flipped light emitting chip according to claim 13, the flipped light emitting chip further comprises one second insulation Layer, is laminated in first expansion electrode portion, second expansion electrode portion and first insulating layer, wherein described second Insulating layer has an at least third channel and an at least fourth lane, and the third channel extends to first expansion electrode Portion, the fourth lane extend to second expansion electrode portion, wherein the N-type electrode is connected with an at least N-type electrode Needle, when the N-type electrode is laminated in the second insulating layer, N-type electrode connection needle be formed in the third channel and It is electrically connected to first expansion electrode portion, wherein there is the P-type electrode an at least P-type electrode to connect needle, in the p-type electricity When pole is laminated in the second insulating layer, P-type electrode connection needle is formed in the fourth lane and is electrically connected to described the Two expansion electrode portions.

20. flipped light emitting chip according to claim 14, the flipped light emitting chip further comprises one second insulation Layer, is laminated in first expansion electrode portion, second expansion electrode portion and first insulating layer, wherein described second Insulating layer has an at least third channel and an at least fourth lane, and the third channel extends to first expansion electrode Portion, the fourth lane extend to second expansion electrode portion, wherein the N-type electrode is connected with an at least N-type electrode Needle, when the N-type electrode is laminated in the second insulating layer, N-type electrode connection needle be formed in the third channel and It is electrically connected to first expansion electrode portion, wherein there is the P-type electrode an at least P-type electrode to connect needle, in the p-type electricity When pole is laminated in the second insulating layer, P-type electrode connection needle is formed in the fourth lane and is electrically connected to described the Two expansion electrode portions.

21. flipped light emitting chip according to claim 15, the flipped light emitting chip further comprises one second insulation Layer, is laminated in first expansion electrode portion, second expansion electrode portion and first insulating layer, wherein described second Insulating layer has an at least third channel and an at least fourth lane, and the third channel extends to first expansion electrode Portion, the fourth lane extend to second expansion electrode portion, wherein the N-type electrode is connected with an at least N-type electrode Needle, when the N-type electrode is laminated in the second insulating layer, N-type electrode connection needle be formed in the third channel and It is electrically connected to first expansion electrode portion, wherein there is the P-type electrode an at least P-type electrode to connect needle, in the p-type electricity When pole is laminated in the second insulating layer, P-type electrode connection needle is formed in the fourth lane and is electrically connected to described the Two expansion electrode portions.

22. flipped light emitting chip according to claim 16, the flipped light emitting chip further comprises one second insulation Layer, is laminated in first expansion electrode portion, second expansion electrode portion and first insulating layer, wherein described second Insulating layer has an at least third channel and an at least fourth lane, and the third channel extends to first expansion electrode Portion, the fourth lane extend to second expansion electrode portion, wherein the N-type electrode is connected with an at least N-type electrode Needle, when the N-type electrode is laminated in the second insulating layer, N-type electrode connection needle be formed in the third channel and It is electrically connected to first expansion electrode portion, wherein there is the P-type electrode an at least P-type electrode to connect needle, in the p-type electricity When pole is laminated in the second insulating layer, P-type electrode connection needle is formed in the fourth lane and is electrically connected to described the Two expansion electrode portions.

23. flipped light emitting chip according to claim 17, the flipped light emitting chip further comprises one second insulation Layer, is laminated in first expansion electrode portion, second expansion electrode portion and first insulating layer, wherein described second Insulating layer has an at least third channel and an at least fourth lane, and the third channel extends to first expansion electrode Portion, the fourth lane extend to second expansion electrode portion, wherein the N-type electrode is connected with an at least N-type electrode Needle, when the N-type electrode is laminated in the second insulating layer, N-type electrode connection needle be formed in the third channel and It is electrically connected to first expansion electrode portion, wherein there is the P-type electrode an at least P-type electrode to connect needle, in the p-type electricity When pole is laminated in the second insulating layer, P-type electrode connection needle is formed in the fourth lane and is electrically connected to described the Two expansion electrode portions.