CN208903048U - Array substrate and liquid crystal display - Google Patents
Array substrate and liquid crystal display Download PDFInfo
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- CN208903048U CN208903048U CN201821469220.9U CN201821469220U CN208903048U CN 208903048 U CN208903048 U CN 208903048U CN 201821469220 U CN201821469220 U CN 201821469220U CN 208903048 U CN208903048 U CN 208903048U
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Abstract
The utility model relates to a kind of array substrate, the pixel unit including array distribution, the pixel unit includes: first electrode layer, is set on glass substrate；Dielectric layer is set to the first electrode layer surface；And the second electrode lay, it is set to the dielectric layer surface, the second electrode lay includes patterned electrode pattern；Wherein, the electrode pattern includes main-body electrode pattern, with the auxiliary electrode pattern for being located at the main-body electrode pattern at least side, the auxiliary electrode pattern and the first electrode layer are electrically connected by via hole, and the parallel electric field to drive liquid crystal deflection is formed between the auxiliary electrode pattern and the main-body electrode pattern；The utility model has the beneficial effects that achieving the purpose that reduce the pixel unit charging time by reducing capacitor between first electrode layer and the second electrode lay.
Description
Technical field
The utility model relates to field of display technology more particularly to a kind of array substrates, and the liquid with the array substrate
Crystal display.
Background technique
Currently, liquid crystal display device has been widely used in various electronic products as the display unit of electronic equipment
In, and thin film transistor-liquid crystal display (Thin Film Transistor-Liquid Crystal Display, referred to as
TFT-LCD) it is then an important component in liquid crystal display device.
As described in Figure of description Fig. 1, the array substrate of the prior art, including thin film transistor (TFT), mainly by backlight, polarisation
Plate, array substrate, colour film plate base and liquid crystal are constituted.As shown in Figure 1, each pixel unit is hidden by glass substrate 101
Barrier 102 and buffer layer 103 are constituted, and polysilicon 104, layer insulation are wherein clipped between buffer layer 103 and gate insulating layer 105
Layer 106 is placed on right above polysilicon 104, and source-drain electrode 109 is inlayed with U-shaped structure to be set and interlayer insulating film 107 and flatness layer 108
Between.First electrode layer 110 and the second electrode lay 111 are overlapped by dielectric layer 112.The grid 106 is switch electrode, absolutely
Edge layer 105 is for separating grid 106 and source-drain electrode 109 and signal wire.Scan line is connected with the grid 106 of thin film transistor (TFT), control
The switch of a line film transistor device processed.The source-drain electrode 109 of thin film transistor (TFT) is connected with signal wire, source-drain electrode 109 and film
Transistor pixels electrode is connected.When thin film transistor switch conducting, signal and drain electrode 109 on signal wire, by film crystalline substance
Body pipe switch passes on source electrode 109, is added on the liquid crystal molecule of pixel electrode, controls the distortion of liquid crystal molecule.Lead electrode with
The edge of array substrate is connected with modular assemblies such as driving circuits.
Thin film transistor base plate is array substrate, under control of the clock signal to the second electrode lay 110 in pixel unit
The capacitor constituted with first electrode layer 111 charges.
The charging modes of the prior art, there is no by changing the electricity between the second electrode lay 110 and first electrode layer 111
Field can control the direction of rotation of liquid crystal between thin film transistor base plate and colour film plate base, thus change the polarization direction of light,
The amount of appearing of light in different pixels lattice is controlled, and then reaches different display effects.
In conclusion the Thin Film Transistor-LCD of the prior art has that the charging time is shorter.
Utility model content
The utility model provides a kind of thin film transistor (TFT), by newly increasing layer of transparent electricity beside top transparent electrode
Pole, and it is overlapped with bottom transparent electrodes by passivation layer hole, reduce top transparent electrode and the transparent electricity in bottom to realize
Capacitor between pole is taken a long time, the low technical problem of charge efficiency with solving the thin film transistor (TFT) charging of the prior art.
To solve the above problems, the technical scheme that the utility model is provided is as follows:
A kind of array substrate, the array substrate include the pixel unit of array distribution, and the pixel unit includes: first
Electrode layer is set on glass substrate；Dielectric layer is set to the first electrode layer surface；And the second electrode lay, setting
In the dielectric layer surface, the second electrode lay includes patterned electrode pattern；Wherein, the electrode pattern includes main body
Electrode pattern, and the auxiliary electrode pattern positioned at the main-body electrode pattern at least side, the auxiliary electrode pattern with it is described
First electrode layer is electrically connected by via hole, is formed between the auxiliary electrode pattern and the main-body electrode pattern to drive
The parallel electric field of liquid crystal deflection.
According to one preferred embodiment of the utility model, the main-body electrode pattern and the first electrode layer form overlay region
Domain and Non-overlapping Domain, the auxiliary electrode pattern corresponds to the Non-overlapping Domain and the main-body electrode pattern spacing is arranged.
According to one preferred embodiment of the utility model, the array substrate further includes the thin film transistor (TFT) of array distribution, institute
It gives an account of and is formed with the first via hole in electric layer, the auxiliary electrode pattern is connected by first via hole and the first electrode layer
It connects；The main-body electrode pattern is connect by first via hole with the drain electrode of the thin film transistor (TFT).
According to one preferred embodiment of the utility model, the auxiliary electrode pattern corresponds to the Non-overlapping Domain in interval point
Cloth, at least corresponding first via hole of an auxiliary electrode pattern.
According to one preferred embodiment of the utility model, the second via hole, second mistake are formed in the first electrode layer
The aperture in hole is greater than the aperture of first via hole, and second via hole corresponds to the overlapping region and is nested in first mistake
Kong Shang, so that the main-body electrode pattern in corresponding first via hole is exhausted by the dielectric layer and the first electrode layer
Edge.
According to one preferred embodiment of the utility model, the auxiliary electrode pattern is equidistantly set with the main-body electrode pattern
It sets.
According to one preferred embodiment of the utility model, the main-body electrode pattern and the first electrode layer respectively with it is described
The plain conductor of thin film transistor (TFT) connects, and forms the voltage difference to drive liquid crystal deflection.
According to one preferred embodiment of the utility model, at least corresponding first via hole of setting in the dielectric layer.
According to one preferred embodiment of the utility model, the auxiliary electrode pattern and the main-body electrode pattern are via same
Road manufacture craft is formed, and ingredient is tin indium oxide.
The utility model has the following beneficial effects: the electrode pattern includes main-body electrode pattern, and it is located at the main body electricity
The auxiliary electrode pattern of pole figure case at least side, the auxiliary electrode pattern are electrically connected with the first electrode layer by via hole
It connects, to realize the capacitor reduced between auxiliary electrode pattern and main-body electrode pattern, reduces the pixel unit charging time, thus
Improve working efficiency.
Detailed description of the invention
It, below will be to required in embodiment description in order to illustrate more clearly of the technical scheme in the embodiment of the utility model
Attached drawing to be used is briefly described, it should be apparent that, the accompanying drawings in the following description is only some realities of the utility model
Example is applied, for those skilled in the art, without creative efforts, can also be obtained according to these attached drawings
Other attached drawings.
Fig. 1 is the schematic diagram of substrate structure of the array substrate of the prior art.
Fig. 2 is the schematic diagram of substrate structure of array substrate embodiment one provided by the utility model；
Fig. 3 is the substrate cross section structure schematic diagram of array substrate embodiment one provided by the utility model；
Fig. 4 is one single pixel unit top planes structure chart of array substrate embodiment provided by the utility model.
Specific embodiment
The following will be combined with the drawings in the embodiments of the present invention, carries out the technical scheme in the embodiment of the utility model
Clearly and completely describe.Obviously, the described embodiments are only a part of the embodiments of the utility model, rather than whole
Embodiment.Based on the embodiments of the present invention, those skilled in the art are obtained without creative efforts
The every other embodiment obtained, fall within the protection scope of the utility model.
In the present invention unless specifically defined or limited otherwise, fisrt feature the "upper" of second feature or it
"lower" may include that the first and second features directly contact, and also may include that the first and second features are not direct contacts but lead to
Cross the other characterisation contact between them.Moreover, fisrt feature includes above the second feature " above ", " above " and " above "
One feature is right above second feature and oblique upper, or is merely representative of first feature horizontal height higher than second feature.First is special
Sign is directly below and diagonally below the second feature including fisrt feature under the second feature " below ", " below " and " below ", or only
Indicate that first feature horizontal height is less than second feature.
Following disclosure provides many different embodiments or example is used to realize the different structure of the utility model.
In order to simplify the disclosure of the utility model, hereinafter the component of specific examples and setting are described.Certainly, they are only
Example, and purpose does not lie in limitation the utility model.In addition, the utility model can in different examples repeat reference numerals
And/or reference letter, this repetition are for purposes of simplicity and clarity, itself not indicate discussed various embodiments
And/or the relationship between setting.In addition, the example of various specific techniques and material that the utility model provides, but this
Field those of ordinary skill can be appreciated that the application of other techniques and/or the use of other materials.
The electricity that the length and the second electrode lay and first electrode layer in array substrate each pixel unit charging time are constituted
Have a pass, in resistance R and capacitor C series circuit, capacitor charging time calculation formula: charging time T=R*C*ln ((E-V)/
E), in formula: R is the equivalent resistance of the circuit, and C is capacitance；The applied voltage value of RC series circuit, T are the time of charging,
Voltage to be achieved, ln are natural logrithm on V-- capacitor.Capacitor C is bigger, and the charging time is longer, the capacitor C smaller charging time
It is then shorter, and capacitance C or resistance value R are smaller, time constant R*C is also smaller, and the charging and discharging speed of capacitor is just faster, instead
?.Capacitor is almost present in all electronic circuits, it can be used as " fast battery " use.
Array substrate is a kind of isolated gate FET, is equivalent to a transistor circuit.Grid is connected with grid line, source electrode
It is connected with signal wire, drain electrode is connected with pixel electrode.Liquid crystal material belongs to insulator, and conductivity is very low under normal conditions.Array
Common electrode on pixel electrode and color membrane substrates on substrate forms the electrode at liquid crystal material both ends.Therefore, the picture of liquid crystal display
Plain electrode section is equivalent to a capacitor.Meanwhile the interval of storage capacitor electrode that pixel electrode and grid are made simultaneously
Insulating film constitute storage capacitance, it is in parallel with liquid crystal capacitance.Therefore, a unit pixel etc. for active matrix liquid crystal display
Effect is a transistor switch, connects the equivalent circuit of two liquid crystal capacitances and storage capacitance in parallel, and wherein liquid crystal capacitance includes
The second electrode lay and first electrode layer, the second electrode lay and first electrode layer carry the capacitor of pixel unit 80%-90%, because
It is the charging time that pixel unit can be improved that this, which improves first electrode layer and the capacitor of the second electrode lay,.
The control of switch is connected with grid line, when the scanned gating of array substrate grid, adds a positive high voltage pulse on grid,
Array substrate conducting.Source electrode has signal input, and picture signal is transmitted to conducting battle array by on-state current by the array substrate of conducting
After in the connected first electrode layer of column substrate and the second electrode lay, the two charges simultaneously, and signal voltage is stored in first electrode layer
On the second electrode lay.The signal voltage driving liquid crystal molecule rotation of liquid crystal pixel, realizes corresponding display, liquid crystal capacitance plays
The effect for keeping image to show.
Embodiment one
As shown in Fig. 2, each pixel unit is made of glass substrate 201, barrier bed 202 and buffer layer 203, wherein
Polysilicon 204 is clipped between buffer layer 203 and gate insulating layer 205, interlayer insulating film 206 is placed on right above polysilicon 204,
Source-drain electrode 209 is inlayed with U-shaped structure to be set between interlayer insulating film 207 and flatness layer 208.First electrode layer 210 and the second electricity
Pole layer 211 is overlapped by dielectric layer 212, includes at least one corresponding first via hole 212 in dielectric layer 212, for reducing first
Capacitor between electrode layer 210 and the second electrode lay 211, and, this capacitor forms the electric field for controlling liquid crystal deflection.The grid
Pole 206 is switch electrode, and insulating layer 205 is for separating grid 206 and source-drain electrode 209 and signal wire.Scan line and film crystal
The grid 206 of pipe is connected, and controls the switch of a line film transistor device.The source-drain electrode 209 of thin film transistor (TFT) and signal wire phase
Even, source-drain electrode 109 is connected with thin film transistor (TFT) pixel electrode.When thin film transistor switch conducting, signal on signal wire with
Drain electrode 209, passes on source electrode 209 by thin film transistor switch, is added on the liquid crystal molecule of pixel electrode, controls liquid crystal molecule
Distortion.The edge of lead electrode and array substrate is connected with modular assemblies such as driving circuits.
Thin film transistor base plate is array substrate, under control of the clock signal to the second electrode lay 210 in pixel unit
The capacitor constituted with first electrode layer 211 charges.
The essential distinction of Fig. 2 and the prior art are as follows: the figure is provided with the first via hole 213 in dielectric layer 212, reduces shape
At the electric field for controlling liquid crystal deflection.
Preferably, the cross sectional shape of first via hole 213 is provided in round or rectangular in order to overlapping.
As shown in figure 3, its second electrode lay includes main-body electrode pattern 310 and auxiliary electrode pattern 313, main-body electrode
Electric field between pattern 310 and the second auxiliary electrode pattern 313 is used to control required for liquid crystal deflection with capacitance structure is equivalent to
Capacitor, the capacitor between main-body electrode pattern 310 and first electrode layer 311 is divided into two parts: main-body electrode pattern 310 just under
Capacitor between capacitor between side and first electrode layer 311 and 310 edge of main-body electrode pattern and first electrode layer 311.It is main
Total capacitance between body electrode pattern 310 and first electrode layer 311 is the sum of above two parts capacitor.By in main-body electrode figure
One layer of first auxiliary electrode pattern 314 is added beside case 310, wherein the second auxiliary electrode pattern 313 and main-body electrode pattern into
The electrical connection of row via hole to reduce the distance between first electrode layer 311 and main-body electrode pattern 310, and then reduces main body electricity
Capacitor between 310 edge of pole figure case and first electrode layer 311, and then reduce the time of pixel unit charging.
If Fig. 4 is the unit pixel unit top planes structural schematic diagram of Fig. 3, main-body electrode pattern 410 in the present embodiment
Side newly increases one layer of first auxiliary electrode pattern 414 and it is passed through the second auxiliary electrode pattern 413 with first electrode layer 411
Overlap joint, the main-body electrode pattern 410 overlap main-body electrode pattern 410 and first electrode layer 411, the auxiliary electrode
Pattern and the main-body electrode pattern via with along with manufacture craft formed, and ingredient is tin indium oxide.The auxiliary electrode
Pattern 423 is interspersed between first electrode layer 411 and top transparent 410, reduces main-body electrode pattern 410 in first to realize
Capacitor between electrode layer 411 reduces the purpose in pixel unit charging time.It preferably, can also be in the first electricity in the present embodiment
Flatness layer hole 415 is arranged in layer 411 side in pole, overlaps main-body electrode pattern 410 and first electrode layer 411 to facilitate.
Preferably, the main-body electrode pattern 410 is evenly distributed in 410 one end of the second electrode lay.
In the present embodiment, the pixel sequence can be that (OrganicLight-Emitting Diode, has OLED
Machine light emitting diode) array or QLED (QuantumDot Light Emitting Diodes, light emitting diode with quantum dots) battle array
Column or Micro LED (microdiode) array.
It has the beneficial effect that by newly increasing a layer main body electrode pattern beside the second electrode lay, and by itself and the first electricity
Pole layer is overlapped by auxiliary electrode pattern, to realize the capacitor reduced between the second electrode lay and first electrode layer, is reached and is subtracted
Few pixel unit charging time, to improve working efficiency.
Although above preferred embodiment is not used in conclusion the utility model is disclosed above with preferred embodiment
To limit the utility model, those skilled in the art can make without departing from the spirit and scope of the utility model
It is various to change and retouch, therefore the protection scope of the utility model subjects to the scope of the claims.
Claims (10)
1. a kind of array substrate, it is characterised in that: the array substrate includes the pixel unit of array distribution, the pixel unit
Include:
First electrode layer is set on glass substrate；
Dielectric layer is set to the first electrode layer surface；And
The second electrode lay, is set to the dielectric layer surface, and the second electrode lay includes patterned electrode pattern；
Wherein, the electrode pattern includes main-body electrode pattern, and the auxiliary electricity positioned at the main-body electrode pattern at least side
Pole figure case, the auxiliary electrode pattern and the first electrode layer are electrically connected by via hole, the auxiliary electrode pattern and institute
State the parallel electric field formed between main-body electrode pattern to drive liquid crystal deflection.
2. array substrate as described in claim 1, it is characterised in that: the main-body electrode pattern and the first electrode layer shape
At overlapping region and Non-overlapping Domain, the auxiliary electrode pattern is corresponded between the Non-overlapping Domain and the main-body electrode pattern
Every setting.
3. array substrate as claimed in claim 2, it is characterised in that: the array substrate further includes that the film of array distribution is brilliant
Body pipe, the first via hole is formed on the dielectric layer, and the auxiliary electrode pattern passes through first via hole and first electricity
Pole layer connection；The main-body electrode pattern is connect by first via hole with the drain electrode of the thin film transistor (TFT).
4. array substrate as claimed in claim 3, it is characterised in that: the auxiliary electrode pattern corresponds to the Non-overlapping Domain
In being spaced apart, an auxiliary electrode pattern at least corresponds to first via hole.
5. array substrate as claimed in claim 3, it is characterised in that: be formed with the second via hole, institute in the first electrode layer
The aperture for stating the second via hole is greater than the aperture of first via hole, and second via hole corresponds to the overlapping region and is nested in institute
It states on the first via hole, so that the main-body electrode pattern in corresponding first via hole passes through the dielectric layer and described first
Electrode layer insulation.
6. array substrate as described in claim 1, it is characterised in that: the auxiliary electrode pattern and the main-body electrode pattern
Spaced set.
7. array substrate as claimed in claim 3, it is characterised in that: the main-body electrode pattern and the first electrode layer point
It is not connect with the plain conductor of the thin film transistor (TFT), forms the voltage difference to drive liquid crystal deflection.
8. array substrate as claimed in claim 3, it is characterised in that: setting at least corresponding one described first in the dielectric layer
Via hole.
9. array substrate as described in claim 1, it is characterised in that: the auxiliary electrode pattern and the main-body electrode pattern
Via with along with manufacture craft formed, and ingredient is tin indium oxide.
10. a kind of liquid crystal display, it is characterised in that: including the array substrate as described in any claim of claim 1-9.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201821469220.9U CN208903048U (en) | 2018-09-07 | 2018-09-07 | Array substrate and liquid crystal display |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201821469220.9U CN208903048U (en) | 2018-09-07 | 2018-09-07 | Array substrate and liquid crystal display |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN208903048U true CN208903048U (en) | 2019-05-24 |
Family
ID=66571735
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201821469220.9U Active CN208903048U (en) | 2018-09-07 | 2018-09-07 | Array substrate and liquid crystal display |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN208903048U (en) |
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2018
- 2018-09-07 CN CN201821469220.9U patent/CN208903048U/en active Active
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