CN208872771U - A kind of ADCP power down signal processing board - Google Patents

Abstract

The utility model discloses a kind of ADCP power down signal processing boards, including signal acquisition unit, control unit, computing unit and sampling unit, wherein: sampling unit includes 4 road synchronized sampling ADC and 1 road single channel sampling ADC, for sampled signal to be sent to signal acquisition unit, signal acquisition unit, including FPGA module, for receiving and handling the sampled signal of sampling unit transmission, and signal after treatment is sent to computing unit, it is responsible for generating pulse transmission signals simultaneously, pulse envelope signal, power selection signal and TVG signal, control unit, it is controlled for system, including controlling and receiving circuit power, transmission power power supply, transmit circuit power supply and signal-processing board power supply, it is responsible for receiving external synchronization signal simultaneously, 4 tunnel sensor signals and battery voltage detection signal.The utility model can effectively save power consumption, and complete signal processing may be implemented and have communication function.

Description

A kind of ADCP power down signal processing board

Technical field

The utility model relates to marine survey technology field, especially a kind of ADCP power down signal processing board.

Background technique

ADCP full name is Acoustic Doppler Current Profilers, refers to acoustic Doppler fluid velocity profile instrument, It is a kind of flow measuring device that twentieth century grows up the beginning of the eighties；ADCP has the fluid velocity profile that can directly measure section, tool Have do not disturb flow field, test last the features such as short, the range that tests the speed is big, be currently used for ocean, river mouth flow field structure investigation, stream Speed and discharge measurement etc., it carries out flow velocity measurement using Doppler effect principle, and ADCP breaks through tradition because of the superiority of its principle Senses influent flow rate instrument based on machinery rotation makees sensor with acoustic wave transducer, and energy converter emits ping wave, and ping wave is logical The backscatterers backscattering such as the sand grain of uneven distribution, planktonic organism in water body is crossed, signal is received by energy converter, after measured Doppler frequency shift and calculate flow velocity.But existing ADCP signal-processing board can generate excessive loss, reduce ADCP letter The service life and durability of number processing board.

Utility model content

In view of the deficiencies of the prior art, the utility model provides a kind of ADCP power down signal processing board, can be effective Power consumption is saved, and complete signal processing may be implemented and there is communication function.

The utility model solves its technical problem and adopts the following technical solutions to achieve:

A kind of ADCP power down signal processing board, including signal acquisition unit, control unit, computing unit and sampling are single Member, in which:

Sampling unit includes 4 road synchronized sampling ADC and 1 road single channel sampling ADC, for sampled signal to be sent to signal Acquisition unit；

Signal acquisition unit, including FPGA module, for receiving and handling the sampled signal of sampling unit transmission；

Control unit is connected with signal acquisition unit and computing unit, controls for system；

Computing unit, including DSP module, the signal for sending to signal acquisition unit carry out calculation processing, and Data interaction is carried out with control unit, and is communicated with external equipment.

Preferably, the signal acquisition unit send signal after treatment to computing unit, while being responsible for generating arteries and veins Punching transmitting signal, pulse envelope signal, power selection signal and TVG signal.

Preferably, described control unit controls and receives at circuit power, transmission power power supply, transmit circuit power supply and signal Plate power supply is managed, while being responsible for receiving external synchronization signal, 4 tunnel sensor signals and battery voltage detection signal, and the control is single Member carries out data by UART, SPI, GPIO and signal acquisition unit and controls the interaction of signal, passes through UART, GPIO and calculating Unit carries out data and controls the interaction of signal.

Preferably, the signal acquisition unit designs 2 road UART serial ports, by level translator MAX3232 by Transistor-Transistor Logic level Serial ports be converted to RS232 serial ports, with external digital sensor interactive information.

Preferably, the FPGA module includes uPP interface, and FPGA module obtains adc data and passes through uPP interface after handling It send to DSP module.

Preferably, buffer is equipped between the FPGA module and external interface, for by the pin of FPGA module and outside Portion's interface is isolated.

Preferably, the DSP module includes MII interface, and DSP module is connected by MII interface with PHY chip, for real Existing ethernet feature.

Preferably, the signal-processing board further includes RTC block, and RTC block supports I2C bus, can by control unit and DSP is accessed jointly by I2C bus；

RTC block has the function of interrupt output, can be exported and be interrupted to control unit according to the timing instant of setting, for real The start by set date function of existing system.

Preferably, the DSP module includes the RS232 serial ports of 1 tunnel debugging, real by electrical level transferring chip MAX3221 The conversion of existing Transistor-Transistor Logic level and RS232 level.

Compared with prior art, the utility model embodiment bring it is following the utility model has the advantages that

1, the control unit of power down signal processing board is reduced not in hardware design by independent 3.3V power supply power supply Pull down resistor on necessary port, and low-power consumption or the external device with shutdown mode are selected, thus the control list realized First low-power consumption；

DSP module and its peripheral circuit power supply can be controlled by control unit, when not needing to use corresponding function, control The corresponding power supply of the controllable shutdown of unit processed, to achieve the purpose that save power consumption；

Signal-processing board has low power consumpting state and state of activation, when signal-processing board is in low power consumpting state, control In a dormant state, peripheral circuit is in low power consumpting state to unit, and DSP module and FPGA module and its peripheral circuit are also equal In power-down state, power consumption can be effectively saved；

Control unit design have 2 can hardware shutdown LED light, may be used to indicate control unit in the debugging stage Working condition, it is formal in application, LED light can be disabled by way of turning off the switch, to achieve the purpose that save power consumption；

2, signal-processing board includes signal acquisition unit, control unit, computing unit and sampling unit, and sampling unit will be adopted Sample signal is sent to signal acquisition unit, and signal acquisition unit send signal after treatment to computing unit, computing unit The signal sent to signal acquisition unit carries out calculation processing, and carries out data interaction with control unit, control unit into The control of row system, may be implemented complete signal processing.

Detailed description of the invention

Fig. 1 is a kind of circuit block diagram schematic diagram of ADCP power down signal processing board of the utility model；

Fig. 2 is a kind of detailed composition block diagram schematic diagram of ADCP power down signal processing board of the utility model；

Fig. 3 is 4 Channel Synchronous sampling ADCs and FPGA module in a kind of ADCP power down signal processing board of the utility model Connection schematic diagram；

Fig. 4 is single channel synchronized sampling ADC and FPGA module in a kind of ADCP power down signal processing board of the utility model Connection schematic diagram；

Fig. 5 is the uPP interfaces of DSP module in a kind of ADCP power down signal processing board of the utility model in reception mould The timing diagram of formula；

Fig. 6 is DSP module Circular buffer schematic diagram in the utility model；

Fig. 7 is ethernet circuit schematic illustration in a kind of ADCP power down signal processing board of the utility model；

Fig. 8 is battery voltage detection circuit schematic diagram in a kind of ADCP power down signal processing board of the utility model；

Fig. 9 is DSP module and peripheral circuit power supply topologies in the utility model；

Figure 10 is the circuit diagram of DSP module in the utility model；

Figure 11 is the circuit diagram of DSP module in the utility model；

Figure 12 is the circuit diagram of DSP module in the utility model.

Specific embodiment

The following will be combined with the drawings in the embodiments of the present invention, carries out the technical scheme in the embodiment of the utility model Clearly and completely describe, it is clear that the described embodiments are only a part of the embodiments of the utility model, rather than whole Embodiment.Based on the embodiments of the present invention, those of ordinary skill in the art are without making creative work Every other embodiment obtained, fall within the protection scope of the utility model.

Referring to Fig. 1, a kind of embodiment provided by the utility model: a kind of ADCP power down signal processing board, including letter Number acquisition unit, control unit, computing unit and sampling unit, in which: sampling unit includes that 4 road synchronized sampling ADC and 1 tunnel are single Channel sample ADC, for sampled signal to be sent to signal acquisition unit；Signal acquisition unit, including FPGA module, for connecing The sampled signal of sampling unit transmission is received and handled, and signal after treatment is sent to computing unit, while being responsible for generation Pulse transmission signals, pulse envelope signal, power selection signal and TVG signal；Control unit, with signal acquisition unit and calculating Unit is connected, and controls for system, including control and receive at circuit power, transmission power power supply, transmit circuit power supply and signal Plate power supply is managed, while being responsible for receiving external synchronization signal, 4 tunnel sensor signals and battery voltage detection signal, and the control is single Member carries out data by UART, SPI, GPIO and signal acquisition unit and controls the interaction of signal, passes through UART, GPIO and calculating Unit carries out data and controls the interaction of signal；Computing unit, including DSP module, for being sent to signal acquisition unit Signal carry out calculation processing, and carry out data interaction with control unit, and communicated with external equipment；

Referring to Fig. 2, a kind of embodiment provided by the utility model: the signal acquisition unit designs 2 road UART serial ports, The serial ports of Transistor-Transistor Logic level is converted into RS232 serial ports by level translator MAX3232, with external digital sensor interactive information； The FPGA module includes uPP interface, and FPGA module obtains adc data and sent by uPP interface to DSP module after handling；Institute It states and is equipped with buffer between FPGA module and external interface, for the pin of FPGA module to be isolated with external interface；Institute Stating DSP module includes MII interface, and DSP module is connected by MII interface with PHY chip, the model KSZ8001L of PHY chip, For realizing 10/100Mb ethernet feature；The signal-processing board further includes RTC block, and RTC block supports I2C bus, can It is accessed jointly by control unit and DSP module by I2C bus；RTC block has the function of interrupt output, can be determined according to setting When moment output interrupt to control unit, the button cell capacity being equipped with for realizing the start by set date function of system, RTC block Not less than 100mAh.The model PCF2129A of RTC block, built-in chip type 32.768kHz temperature-compensating crystal oscillator, -15~ Precision within the scope of 60 DEG C is ± 3ppm, can meet accuracy requirement, and the DSP module includes the RS232 serial ports of 1 tunnel debugging, The conversion of Transistor-Transistor Logic level and RS232 level is realized by electrical level transferring chip MAX3221.

Interface between FPGA module and control unit includes 1 road UART, 1 road SPI, several GPIO, is used for FPGA module The information of the non real-time nature of low speed is interacted between control unit, wherein control unit is as host, FPGA module as slave, Slave logic is designed in FPGA module；GPIO is used for transmitting control or status signal between FPGA module and control unit, Such as interruption, data transfer request, working condition；Interface between FPGA module and DSP module further includes SPI and several GPIO, SPI are used to interact the information of the non real-time nature of low speed between FPGA module and DSP module, DSP module as SPI host, FPGA module realizes the logical sequence of SPI slave as SPI slave in FPGA module.

GPIO between FPGA module and DSP module is such as interrupted, data transmission is asked for transmitting control or status signal Ask, working condition etc., the interface of DSP module and control unit include 1 road UART and several GPIO, UART for DSP module with The information of the non real-time nature of interaction low speed between control unit, GPIO are used to transmit control between DSP module and control unit Or status signal, such as interrupt, working condition.Exterior I/O Interface of control unit includes that 4 tunnels output control signal and 1 road are defeated Enter external synchronization signal, 4 tunnels output control signal are as follows: receive circuit power control, the control of transmission power power supply, transmit circuit power supply Control, the control of signal-processing board power supply, it is contemplated that external controlled plant is powerful device, therefore increases in output interface and limit The protection circuits such as leakage resistance, transient state inhibition, 1 tunnel input external synchronization signal are examined for being worked asynchronously by multiple signal-processing boards High reject signal may be introduced by considering external input, therefore increase clamper protection, current-limiting protection, transient state inhibition etc. in input interface Protect circuit.

Control unit need to acquire 4 tunnel sensor signals, and signal 0~5V of input range, sample rate 100Hz are single using control The on piece 12bitADC of member acquires No. 4 sensors in turn, and ADC reference voltage selects the 3.3V power supply electricity of control unit Pressure needs to divide input signal to match the range of ADC, and inhibit to protect in sensor signal input terminal design transient Circuit causes permanent damages to avoid the port I/O of glitch control unit；The serial ports of UART all the way of control unit passes through MAX3160 chip is converted to 422 serial ports, and MAX3160 chip has suspend mode, when the input of SHDN pin is low level, core Charge pump inside piece stops working, and the conversion of Transistor-Transistor Logic level to RS422 level stops, and the operating current of chip is down at this time 1uA, but the level conversion function of receiving direction is unaffected, i.e. control unit still can be with when MAX3160 is in suspend mode Data are received, data is if desired sent at this time, then firstly the need of high SHDN pin is set, MAX3160 is made to exit suspend mode, are waited (1ms or so) could normally send data after chip activates completely, wherein the chip model of control unit is MSP430F5438A。

Referring to Fig. 3, a kind of embodiment provided by the utility model: the model LTC2170- of 4 road synchronized sampling ADC 14, it can support the sample rate of 5Msps~25Msps, the sample rate of ADC can be 1.2Msps, 2.4Msps, 4.8Msps, 6Msps, The case where for sample rate < 5Msps, realizes, such as sample with 9.6Msps that 1/8 extracts using the method extracted after over-sampling To equivalent 1.2Msps sample rate, 1/4 extraction obtains equivalent 2.4Msps sample rate, and 1/2 extraction obtains equivalent 4.8Msps sampling Rate；The A/D transformation result of LTC2170-14 is exported in the form of serial LVDS, the optional single channel in every channel or two-way Serial output, this Serial data rate when using every channel single channel Serial output in scheme are as follows: 9.6Msps × 14bit=134.4Mbps；

Referring to Fig. 4, a kind of embodiment provided by the utility model: the model LTC2256- of 1 road single channel sampling ADC 14, LTC2256-14 data-interface supports full rate CMOS, DDR CMOS or DDR LVDS, and the design selects full rate CMOS Interface, data/address bus 14bit；

Please refer to Fig. 5-6, a kind of embodiment provided by the utility model: Fig. 5 is the uPP interfaces of DSP module in connecing The timing diagram of receipts mode, uPP interface obtain ADC for the high speed data transfer between FPGA module and DSP module, FPGA module It is sent by uPP interface to DSP module after data and processing, the uPP interface data bit wide of DSP module is 16bit, maximum clock speed Rate can reach 75MHz.For this application, the uPP interfaces of DSP module are in reception pattern, when providing interface by FPGA module Clock, when sample rate is 6Msps, the clock rate of uPP interface are as follows: the channel 6Msps × 4 × 2 tunnels (I/Q)/8 times of extraction= 6MHz, therefore uPP can fully meet required transmission rate request；DSP opens up Circular buffer in end in DDR, passes through the side of DMA Simultaneously processing is conducted batch-wise in formula data of the caching from UPP, as shown in fig. 6, being DSP module Circular buffer schematic diagram；

Please refer to Fig. 7-8, a kind of embodiment provided by the utility model: computing unit designs 10/100Mb ether all the way Net, computing unit are controlled on piece ethernet mac, and PHY chip KSZ8001L is selected to realize 10/100Mb ethernet feature, meter It calculates and is connected between unit and PHY by MII interface, isolator HR601680 is added between PHY chip and physical interface and realizes Insulation blocking；The measurement error of battery voltage measurement circuit is no more than 1%, and power consumption is no more than 0.1mW, uses the piece of control unit Upper 12bit ADC acquires cell voltage, it is contemplated that and it is not high to the monitoring requirement of real-time of cell voltage, using as shown in Figure 9 Circuit arrangement: resistance R1 and R2 divides power supply, metal-oxide-semiconductor is accessed between divider resistance, in order to use the GPIO of control unit to control The on-off of metal-oxide-semiconductor is selected VGS (th) lesser pipe 2N7002 (VGS (th)=2.1V), and controls source voltage on the left side 1V It is right；When needing to detect supply voltage, control unit exports high level to the grid of metal-oxide-semiconductor, metal-oxide-semiconductor is connected, due to pipe RDS (ON) be far smaller than the value of divider resistance, the on piece ADC that the voltage that divider resistance is got is sent into control unit is adopted Sample calculates to obtain supply voltage after the completion of supply voltage detection according to dividing ratios later and sets low the grid level of metal-oxide-semiconductor, Metal-oxide-semiconductor ends at this time, and circuit hardly consumes power；The precision of the 12bit on piece ADC of control unit is 1/4096= The introducing of 0.024%, 20:1 bleeder circuit leads to 20 times of accuracy decline of ADC, but still can achieve 20 ╳ 0.024%= 0.48%, it can satisfy measurement accuracy demand, when the frequency of supply voltage detection is lower, the program can significantly reduce power consumption, And simple circuit, area occupied are small.

Please refer to Fig. 9-12, a kind of embodiment provided by the utility model: DSP module and peripheral circuit power supply include DSP Core power DSP_1V2, DSPI/O power supply DSP _ 3V3, DDR power supply DSP _ 1V8 and power over ethernet ENET_3V3.DSP submodule Block power supply realizes that wherein power over ethernet ENET_3V3 can be by control unit control using multichannel power management chip TPS65053 System is enabled, when not needing to use ethernet feature, the controllable shutdown ENET_3V3 power supply of control unit, to reach saving function The purpose of consumption, wherein the model OMAP-L138 of DSP module.

Working principle: ADCP using Doppler effect principle carry out flow velocity measurement, control unit control and receive circuit power, The on-off of transmission power power supply, transmit circuit power supply and signal-processing board power supply, and by carrying out data transmission with FPGA module, Control FPGA module and emit certain pulses, signal is acquired to FPGA module by sampling unit, FPGA module by it is signal collected most It is sent to computing unit eventually and carries out data processing, monitoring center can be sent data to by Ethernet according to actual needs, It is possible thereby to directly measure the flow velocity of section；Wherein, EP4CE22F17I7N can be selected in FPGA module, and resource description is as follows in piece:

Resource description in 1 EP4CE22F17I7N piece of table

Finally, it should be noted that embodiment described above, only specific embodiment of the present utility model, to illustrate this The technical solution of utility model, rather than its limitations, the protection scope of the utility model is not limited thereto, although referring to aforementioned The utility model is described in detail in embodiment, those skilled in the art should understand that: it is any to be familiar with this skill The technical staff in art field within the technical scope disclosed by the utility model, still can be to skill documented by previous embodiment Art scheme modify or can readily occur in variation or equivalent replacement of some of the technical features；And these modifications, Variation or replacement, the spirit and model of the utility model embodiment technical solution that it does not separate the essence of the corresponding technical solution It encloses, should be covered within the scope of the utility model.Therefore, the protection scope of the utility model should be wanted with the right Subject to the protection scope asked.

Claims (9)

1. a kind of ADCP power down signal processing board, which is characterized in that including signal acquisition unit, control unit, computing unit And sampling unit, in which:

Sampling unit includes 4 road synchronized sampling ADC and 1 road single channel sampling ADC, for sampled signal to be sent to signal acquisition Unit；

Signal acquisition unit, including FPGA module, for receiving and handling the sampled signal of sampling unit transmission；

Control unit is connected with signal acquisition unit and computing unit, controls for system；

Computing unit, including DSP module, signal for sending to signal acquisition unit carry out calculation processing, and with control Unit processed carries out data interaction, and is communicated with external equipment.

2. a kind of ADCP power down signal processing board according to claim 1, which is characterized in that the signal acquisition unit Signal after treatment is sent to computing unit, while being responsible for generating pulse transmission signals, pulse envelope signal, power selection Signal and TVG signal.

3. a kind of ADCP power down signal processing board according to claim 1, which is characterized in that described control unit control Circuit power, transmission power power supply, transmit circuit power supply and signal-processing board power supply are received, while being responsible for receiving outer synchronous letter Number, 4 tunnel sensor signals and battery voltage detection signal, and described control unit passes through UART, SPI, GPIO and signal acquisition Unit carries out data and controls the interaction of signal, carry out data by UART, GPIO and computing unit and control the interaction of signal.

4. a kind of ADCP power down signal processing board according to claim 1, which is characterized in that the signal acquisition unit 2 road UART serial ports are designed, the serial ports of Transistor-Transistor Logic level are converted to by RS232 serial ports by level translator MAX3232, with external number Word sensor interactive information.

5. a kind of ADCP power down signal processing board according to claim 1, which is characterized in that the FPGA module includes UPP interface, FPGA module obtain adc data and are sent by uPP interface to DSP module after handling.

6. a kind of ADCP power down signal processing board according to claim 1, which is characterized in that the FPGA module and outer Buffer is equipped between portion's interface, for the pin of FPGA module to be isolated with external interface.

7. a kind of ADCP power down signal processing board according to claim 1, which is characterized in that the DSP module includes MII interface, DSP module is connected by MII interface with PHY chip, for realizing ethernet feature.

8. a kind of ADCP power down signal processing board according to claim 1, which is characterized in that the signal-processing board is also Including RTC block, RTC block supports I2C bus, can be accessed jointly by control unit and DSP by I2C bus；

RTC block has the function of interrupt output, can be exported and be interrupted to control unit, for realizing being according to the timing instant of setting The start by set date function of system.

9. a kind of ADCP power down signal processing board according to claim 1, which is characterized in that the DSP module includes 1 The RS232 serial ports of road debugging realizes the conversion of Transistor-Transistor Logic level and RS232 level by electrical level transferring chip MAX3221.