CN208836097U - A kind of analog switching circuit of adjustable opening time - Google Patents
A kind of analog switching circuit of adjustable opening time Download PDFInfo
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- CN208836097U CN208836097U CN201821767407.7U CN201821767407U CN208836097U CN 208836097 U CN208836097 U CN 208836097U CN 201821767407 U CN201821767407 U CN 201821767407U CN 208836097 U CN208836097 U CN 208836097U
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Abstract
The utility model discloses the analog switching circuits of adjustable opening time a kind of, it include: control circuit, current generating circuit and main switch circuit, wherein: control circuit receives clock signal, enable signal and time setting signal, and time setting signal is decoded, the control signal of output control current generating circuit；Current generating circuit receives control signal, control signal is converted to corresponding output electric current, and output electric current is input to main switch circuit；Main switch circuit receives the output electric current of input signal and current generating circuit, and the output electric current of current generating circuit is converted to gate source voltage required for main switch, to realize the slow unlatching of analog switching circuit.Longer open time delay can be carried out by the analog switching circuit of adjustable opening time provided by the utility model and voluntarily adjusts open time delay.
Description
Technical field
The utility model relates to semiconductor integrated circuit technology field, adjustable opened more specifically, it relates to a kind of
Open the analog switching circuit of time.
Background technique
Analog switch extensive application in terms of signal transmission, such as: the USB interface in mobile phone may be used as audio
The transmission channel of signal, it is therefore desirable to which a simulation that can be switched between normal USB signals and audio signal is opened
It closes.
The opening process of audio switch is an important course of work, but does not allow to open in practical application
Fastly, or even require the time opened adjustable, main cause is hindrance may to be brought to change if too fast unlatching
It is larger, it is direct the result is that reducing the usage experience of user in earphone or related audio output equipment generation noise.Therefore,
How to realize that with the analog switch that slowly the unlatching even opening time can set be one for semiconductor manufacturer
Thing significant and that there is challenge.
Utility model content
In view of this, the present invention provides the analog switching circuits of adjustable opening time a kind of, to solve
The problem of analog switch of existing application can not carry out longer open time delay and cannot voluntarily adjust open time delay.
To achieve the above object, the utility model provides the following technical solutions:
A kind of analog switching circuit of adjustable opening time, comprising: control circuit, current generating circuit and master open
Powered-down road, in which:
The input terminal of the control circuit receives clock signal, enable signal and time setting letter as signal input part
Number, the output end of the control circuit is connected with the input terminal of the current generating circuit, the output of the current generating circuit
End is connected with the first input end of the main switch circuit, and the second input terminal of the main switch circuit receives input signal, institute
The output end for stating main switch circuit exports gate source voltage required for main switch as signal output end；
The control circuit receives the clock signal, the enable signal and the time setting signal, and to institute
It states time setting signal to be decoded, output controls the control signal of the current generating circuit；
The current generating circuit receives the control signal, and the control signal is converted to corresponding output electric current,
And the output electric current is input to the main switch circuit；
The main switch circuit receives the output electric current of the input signal and the current generating circuit, and will be described
The output electric current of current generating circuit is converted to gate source voltage required for the main switch, to realize analog switching circuit
Slowly open.
Further, the control circuit includes: decoding circuit and counter, in which:
The decoding circuit includes first end, second end, third end, the 4th end and the 5th end, and the counter includes:
First end, second end and output end；
The first end of the decoding circuit inputs the clock signal as clock signal input terminal, the decoding circuit
Second end inputs the enable signal as enable end, when the third end of the decoding circuit is described as time setting end input
Clock setting signal, the decoding circuit are decoded the time setting signal；
First end phase of 4th end of the decoding circuit as the output end output pulse signal, with the counter
Even；5th end of the decoding circuit is connected as feedback end with the second end of the counter, receives the anti-of the counter
Feedback signal；
Output end of the third end of the counter as the control circuit, the input terminal with the current generating circuit
It is connected, output controls the control signal of the current generating circuit, the binary coding that the control signal is N bit.
Further, the current generating circuit includes: N number of current source, the first NMOS tube, the second NMOS tube, third
NMOS tube, the first PMOS tube and the second PMOS tube, in which:
The corresponding electric current of the N number of current source is I, 2I ... .2N-1* it is opened by one one end of I, each current source
The drain electrode that S [N-1] is connected to first NMOS tube is closed, and each switch S [N-1] receives the defeated of the control circuit
Out, the other end of each current source is connected, and is connected with power end, and when corresponding bit is high, the switch of response is closed
It closes；
The first end of first NMOS tube, the control terminal of first NMOS tube, the control terminal of second NMOS tube
And the control terminal of the third NMOS tube is connected；
The second of the second end of first NMOS tube, the second end of second NMOS tube and the third NMOS tube
End ground connection；
The first end of second NMOS tube is connected with the first end of first PMOS tube, and the of first PMOS tube
The control terminal of one end, the control terminal of first PMOS tube and second PMOS tube is connected；
The second end of first PMOS tube is connected with the second end of second PMOS tube, and with the power end phase
Even；
The first end electric current IH of second PMOS tube is equal with the first end electric current IL of the third NMOS tube.
Further, the first end of first NMOS tube, second NMOS tube and the third NMOS tube is leakage
Pole, second end are source electrode and control terminal is grid.
Further, the first end of first PMOS tube and second PMOS tube be drain electrode, second end be source electrode with
And control terminal is grid.
Further, the main switch circuit includes: main switch, bias current sources, switch, first switch, second opens
Pass, third switch, Zener diode, resistance, the first current source and the second current source, in which:
The first end of the main switch receives the input signal, the control terminal of the main switch respectively with it is described partially
Set one end of the cathode of current source, the negative grade of the Zener diode, one end of the first switch and third switch
It is connected, the anode of the bias current sources is connected by the switch with the power end, the second end point of the main switch
It is not connected with one end of one end of the second switch, the positive grade of the Zener diode and the resistance, it is defeated as signal
Outlet exports gate source voltage required for the main switch；
The other end of the second switch is grounded by second current source, and the other end of the first switch passes through institute
It states the first current source to be connected with the power end, the other end of the third switching tube is connected with the other end of the resistance.
Further, the main switch is NMOS tube.
Further, the first end of the main switch is drain electrode, second end is source electrode and control terminal is grid
It can be seen via above technical scheme that compared with prior art, adjustable opened the utility model discloses a kind of
Open the analog switching circuit of time, comprising: control circuit, current generating circuit and main switch circuit, in which: control circuit connects
Clock signal, enable signal and time setting signal are received, and time setting signal is decoded, output control electric current generates
The control signal of circuit；Current generating circuit receives control signal, control signal is converted to corresponding output electric current, and will be defeated
Electric current is input to main switch circuit out；Main switch circuit receives the output electric current of input signal and current generating circuit, and will
The output electric current of current generating circuit is converted to gate source voltage required for main switch, to realize the slow of analog switching circuit
It opens.Longer open time delay can be carried out by the analog switching circuit of adjustable opening time provided by the utility model
And voluntarily adjust open time delay.
Detailed description of the invention
In order to illustrate the embodiment of the utility model or the technical proposal in the existing technology more clearly, below will be to embodiment
Or attached drawing needed to be used in the description of the prior art is briefly described, it should be apparent that, the accompanying drawings in the following description is only
It is the embodiments of the present invention, for those of ordinary skill in the art, without creative efforts, also
Other attached drawings can be obtained according to the attached drawing of offer.
Fig. 1 is switching circuit ifq circuit schematic diagram provided by the embodiment of the utility model；
Fig. 2 is a kind of analog switching circuit block diagram of adjustable opening time provided by the embodiment of the utility model；
Fig. 3 is control circuit schematic diagram provided by the embodiment of the utility model；
Fig. 4 is current generating circuit schematic diagram provided by the embodiment of the utility model；
Fig. 5 is main switch circuit schematic diagram provided by the embodiment of the utility model.
Specific embodiment
The following will be combined with the drawings in the embodiments of the present invention, carries out the technical scheme in the embodiment of the utility model
Clearly and completely describe, it is clear that the described embodiments are only a part of the embodiments of the utility model, rather than whole
Embodiment.Based on the embodiments of the present invention, those of ordinary skill in the art are without making creative work
Every other embodiment obtained, fall within the protection scope of the utility model.
The filtering that switch solution in the prior art mainly uses capacitor and resistance to carry out switching voltage generates certain prolong
Late, or using switching capacity and electric current it is applied to the methods of capacitor.Although method in the prior art is to the opening time
Delay has certain effect, but as the requirement of cell phone manufacturer improves, it is desirable that when it is adjustable to have the opening time, and having longer
Between opening process, therefore, method in the prior art is not able to satisfy above-mentioned application demand then or needs biggish cost
It just can satisfy above-mentioned application demand.
As shown in Figure 1, being switching circuit ifq circuit provided by the embodiment of the utility model, by current source IB, switch S
And main switch M0 and Zener diode D0 composition, after switch S closure, electric current I of the Zener diode D0 in current source IB
Under the action of generate a clamp voltage, provide unlatching required gate source voltage for main switch M0.When the starting of the circuit
Between depending on switching tube M0 grid to source electrode and the capacitor of drain electrode, the opening time, this was right in microsecond rank under normal circumstances
Still too fast for audio class switch, it is unable to satisfy the even longer opening time requirement of millisecond, for this purpose, the utility model is real
It applies example and provides the analog switching circuit of adjustable opening time a kind of.
As shown in Fig. 2, the utility model embodiment provides the analog switching circuit of adjustable opening time a kind of, packet
It includes: control circuit 201, current generating circuit 202 and main switch circuit 203, in which:
The input terminal of above-mentioned control circuit 201 is set as signal input part reception clock signal, enable signal and time
Determine signal, the output end of above-mentioned control circuit 201 is connected with the input terminal of above-mentioned current generating circuit 202, and above-mentioned electric current generates
The output end of circuit 202 is connected with the first input end of above-mentioned main switch circuit 203, and the second of above-mentioned main switch circuit 203 is defeated
Enter end and receive input signal, the output end of above-mentioned main switch circuit 203 exports required for main switch as signal output end
Gate source voltage；
Above-mentioned control circuit 201 receives the clock signal, above-mentioned enable signal and above-mentioned time setting signal, and right
Above-mentioned time setting signal is decoded, and output controls the control signal of above-mentioned current generating circuit 202；
Above-mentioned current generating circuit 202 receives above-mentioned control signal, and above-mentioned control signal is converted to corresponding output electricity
Stream, and above-mentioned output electric current is input to above-mentioned main switch circuit 203；
Above-mentioned main switch circuit 203 receives the output electric current of above-mentioned input signal and above-mentioned current generating circuit 202, and
The output electric current of above-mentioned current generating circuit 202 is converted into gate source voltage required for above-mentioned main switch, to realize simulation
The slow unlatching of switching circuit.
As shown in figure 3, above-mentioned control circuit 201 includes: decoding circuit 2011 and counter 2012, in which:
Above-mentioned decoding circuit 2011 includes first end, second end, third end, the 4th end and the 5th end, above-mentioned counter
2012 include: first end, second end and output end；
The first end of above-mentioned decoding circuit 2011 inputs above-mentioned clock signal, above-mentioned decoding electricity as clock signal input terminal
The second end on road 2011 inputs above-mentioned enable signal as enable end, and the third end of above-mentioned decoding circuit 2011 is set as the time
End inputs above-mentioned clock set signal, and above-mentioned decoding circuit 2011 is decoded above-mentioned time setting signal；
4th end of above-mentioned decoding circuit 2011 is as above-mentioned output end output pulse signal, with above-mentioned counter 2012
First end is connected；5th end of above-mentioned decoding circuit 2011 is connected as feedback end with the second end of above-mentioned counter 2012, connects
Receive the feedback signal of above-mentioned counter 2012；
Output end of the third end of above-mentioned counter 2012 as above-mentioned control circuit 201, with above-mentioned current generating circuit
202 input terminal is connected, and output controls the control signal of above-mentioned current generating circuit 202, and above-mentioned control signal is the two of Nbit
Scale coding.
It should be noted that as shown in figure 3, the function of above-mentioned decoding circuit 2011 is true in turn according to clock set signal
The frequency of the pulse of definite decoding output, time setting can be the binary system of Nbit, such as setting value is converted to the decimal system
It is afterwards X, then a pulse CK1 can be exported every X clock cycle by decoding, which will be defeated as the clock of counter 2012
Enter, FB is the feedback signal that counter 2012 returns, which is height, then it represents that the S [0] of counter 2012~S [N-1] is
Height, i.e., decoding receive FB be it is high when, then stop the state change of CK1.Reset letter is omitted here in above-mentioned 2012 function of counter
Number, the input of counter 2012 is CK1, exports the binary coding for NBit, and maximum can be counted as 2N-1, and wherein clock is believed
Number be square wave, frequency can according to system to open time requirement set, time setting signal be Nbit binary system
Input.
As shown in figure 4, above-mentioned current generating circuit 202 include: N number of current source (as shown in Figure 4), the first NMOS tube N1,
Second NMOS tube N2, third NMOS tube N3, the first PMOS tube P1 and the second PMOS tube P2, in which:
The corresponding electric current of N number of above-mentioned current source is I, 2I ... .2N-1* I, each above-mentioned current source pass through a switch S [N-
1] it is connected to the drain electrode of above-mentioned first NMOS tube, and each above-mentioned switch S [N-1] receives the output of above-mentioned control circuit, each
The other end of above-mentioned current source is connected, and is connected with power end, and when corresponding bit is high, response is closed the switch；
The first end of above-mentioned first NMOS tube, the control terminal of above-mentioned first NMOS tube, the control terminal of above-mentioned second NMOS tube
And the control terminal of above-mentioned third NMOS tube is connected；
The second of the second end of above-mentioned first NMOS tube, the second end of above-mentioned second NMOS tube and above-mentioned third NMOS tube
End ground connection；
The first end of above-mentioned second NMOS tube is connected with the first end of above-mentioned first PMOS tube, and the of above-mentioned first PMOS tube
The control terminal of one end, the control terminal of above-mentioned first PMOS tube and above-mentioned second PMOS tube is connected；
The second end of above-mentioned first PMOS tube is connected with the second end of above-mentioned second PMOS tube, and with above-mentioned power end phase
Even；
The first end electric current IH of above-mentioned second PMOS tube is equal with the first end electric current IL of above-mentioned third NMOS tube.
Further, the first end of above-mentioned first NMOS tube, above-mentioned second NMOS tube and above-mentioned third NMOS tube is leakage
Pole, second end are source electrode and control terminal is grid.
Further, the first end of above-mentioned first PMOS tube and above-mentioned second PMOS tube be drain electrode, second end be source electrode with
And control terminal is grid.
It should be noted that above-mentioned current generating circuit is as shown in figure 4, the left side is made of N number of current source, electric current is corresponded to
I、2I….2N-1* I, each current source are connected to common end, that is, the drain terminal of the first NMOS tube N1 by a switch.Its
In, the first NMOS tube N1, the second NMOS tube N2 are identical with third NMOS tube N3 size, the first PMOS tube P1 and the second PMOS tube P2
Size is identical, then the first NMOS tube N1, the second NMOS tube N2 and third NMOS tube N3 constitute current mirror, that is, the first NMOS tube
The drain terminal electric current of N1 will be equal to IL, while size is also equal to IH, and switch S [0]~S [N-1] receives the output of control circuit, when right
Answer bit be it is high when, response closes the switch.
As shown in figure 5, above-mentioned main switch circuit includes: main switch M0, bias current sources IB, switch S, first switch
S1, second switch S2, third switch S3, Zener diode D0, resistance R, the first current source IH and the second current source IL,
In:
The first end of above-mentioned main switch M0 receives above-mentioned input signal, the control terminal of above-mentioned main switch M0 respectively with it is upper
State the cathode of bias current sources IB, the negative grade of above-mentioned Zener diode D0, one end of above-mentioned first switch S1 and above-mentioned third
One end of switch S3 is connected, and the anode of above-mentioned bias current sources IB is connected by above-mentioned switch S with above-mentioned power end VCC, above-mentioned
The second end of main switch M0 respectively with one end of above-mentioned second switch S2, the positive grade of above-mentioned Zener diode D0 and the electricity
The one end for hindering R is connected, and exports gate source voltage required for above-mentioned main switch M0 as signal output end；
The other end of above-mentioned second switch S2 is grounded by above-mentioned second current source IL, the other end of above-mentioned first switch S1
It is connected by above-mentioned first current source IH with above-mentioned power end VCC, the other end of above-mentioned third switch S3 pipe is with above-mentioned resistance R's
The other end is connected.
Further, above-mentioned main switch M0 is NMOS tube, and the first end of above-mentioned main switch M0 is drain electrode, second end is
Source electrode and control terminal are grid.
It should be noted that above-mentioned main switch circuit 203 is opened by main switch M0, bias current sources IB, switch S, first
Close S1, second switch S2, third switch S3, Zener diode D0 and the first current source IH and the second current source IL and resistance R
It forms, under normal work, first switch S1, second switch S2 and third switch S3 are disconnected, switch S closure, such main switch
The gate source voltage of M0 voltage between A and S, also will be by Zener diode D0 clamper in itself clamp voltage.
Overall startup process is as follows:
(1) switch S is closed, and first switch S1, second switch S2 and third switch S3 are closed, then the first current source IH and the
Two current source IL will generate equal electric current, which generates the voltage of IH*R by resistance R, and the voltage is with the first current source
The electric current of IH and the second current source IL become larger and become larger.
(2) all bit of above-mentioned counter 2022 it is all it is high after, closure switch S disconnects first switch S1, the
Two switch S2 and third switch S3 complete starting.
It should be noted that all the embodiments in this specification are described in a progressive manner, each embodiment weight
Point explanation is the difference from other embodiments, and the same or similar parts between the embodiments can be referred to each other.
It is exemplarily described above in conjunction with the circuit that attached drawing proposes the utility model, the explanation of above embodiments
It is merely used to help understand the core concept of the utility model.For those of ordinary skill in the art, according to the utility model
Thought, there will be changes in the specific implementation manner and application range.In conclusion the content of the present specification should not be understood
For limitations of the present invention.
The foregoing description of the disclosed embodiments can be realized professional and technical personnel in the field or using originally practical new
Type.Various modifications to these embodiments will be readily apparent to those skilled in the art, and determine herein
The General Principle of justice can be realized in other embodiments without departing from the spirit or scope of the present utility model.Cause
This, the present invention will not be limited to the embodiments shown herein, and is to fit to and principles disclosed herein
The widest scope consistent with features of novelty.
Claims (8)
1. a kind of analog switching circuit of adjustable opening time characterized by comprising control circuit, electric current generate electricity
Road and main switch circuit, in which:
The input terminal of the control circuit receives clock signal, enable signal and time setting signal as signal input part,
The output end of the control circuit is connected with the input terminal of the current generating circuit, the output end of the current generating circuit with
The first input end of the main switch circuit is connected, and the second input terminal of the main switch circuit receives input signal, the master
The output end of switching circuit exports gate source voltage required for main switch as signal output end；
The control circuit receives the clock signal, the enable signal and the time setting signal, and to it is described when
Between setting signal be decoded, output controls the control signal of the current generating circuit；
The current generating circuit receives the control signal, the control signal is converted to corresponding output electric current, and will
The output electric current is input to the main switch circuit；
The main switch circuit receives the output electric current of the input signal and the current generating circuit, and by the electric current
The output electric current of generation circuit is converted to gate source voltage required for the main switch, to realize the slow of analog switching circuit
It opens.
2. analog switching circuit according to claim 1, which is characterized in that the control circuit include: decoding circuit and
Counter, in which:
The decoding circuit includes first end, second end, third end, the 4th end and the 5th end, and the counter includes: first
End, second end and output end；
The first end of the decoding circuit inputs the clock signal as clock signal input terminal, and the second of the decoding circuit
End inputs the enable signal as enable end, and the third end of the decoding circuit inputs the clock as time setting end and sets
Determine signal, the decoding circuit is decoded the time setting signal；
4th end of the decoding circuit is connected as the output end output pulse signal with the first end of the counter；
5th end of the decoding circuit is connected as feedback end with the second end of the counter, receives the feedback letter of the counter
Number；
Output end of the third end of the counter as the control circuit, the input terminal phase with the current generating circuit
Even, output controls the control signal of the current generating circuit, the binary coding that the control signal is N bit.
3. analog switching circuit according to claim 2, which is characterized in that the current generating circuit includes: N number of electric current
Source, the first NMOS tube, the second NMOS tube, third NMOS tube, the first PMOS tube and the second PMOS tube, in which:
The corresponding electric current of the N number of current source is I, 2I ... .2N-1* a switch S is passed through in one end of I, each current source
[N-1] is connected to the drain electrode of first NMOS tube, and each switch S [N-1] receives the output of the control circuit, often
The other end of a current source is connected, and is connected with power end, and when corresponding bit is high, response is closed the switch；
The first end of first NMOS tube, the control terminal of first NMOS tube, the control terminal of second NMOS tube and
The control terminal of the third NMOS tube is connected；
Second termination of the second end of first NMOS tube, the second end of second NMOS tube and the third NMOS tube
Ground；
The first end of second NMOS tube is connected with the first end of first PMOS tube, and the first of first PMOS tube
The control terminal at end, the control terminal of first PMOS tube and second PMOS tube is connected；
The second end of first PMOS tube is connected with the second end of second PMOS tube, and is connected with the power end；
The first end electric current IH of second PMOS tube is equal with the first end electric current IL of the third NMOS tube.
4. analog switching circuit according to claim 3, which is characterized in that first NMOS tube, the 2nd NMOS
It manages and the first end of the third NMOS tube is drain electrode, second end is source electrode and control terminal is grid.
5. analog switching circuit according to claim 3, which is characterized in that first PMOS tube and the 2nd PMOS
The first end of pipe is drain electrode, second end is source electrode and control terminal is grid.
6. analog switching circuit according to claim 3, which is characterized in that the main switch circuit include: main switch,
Bias current sources, switch, first switch, second switch, third switch, Zener diode, resistance, the first current source and second
Current source, in which:
The first end of the main switch receives the input signal, the control terminal of the main switch respectively with the biased electrical
One end that the cathode in stream source, the negative grade of the Zener diode, one end of the first switch and the third switch is connected,
The anode of the bias current sources by it is described switch be connected with the power end, the second end of the main switch respectively with institute
The one end for stating one end of second switch, the positive grade of the Zener diode and the resistance is connected, defeated as signal output end
Gate source voltage required for the main switch out；
The other end of the second switch is grounded by second current source, and the other end of the first switch passes through described the
One current source is connected with the power end, and the other end of the third switching tube is connected with the other end of the resistance.
7. analog switching circuit according to claim 6, which is characterized in that the main switch is NMOS tube.
8. analog switching circuit according to claim 6, which is characterized in that the first end of the main switch be drain electrode,
Second end is source electrode and control terminal is grid.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201821767407.7U CN208836097U (en) | 2018-10-29 | 2018-10-29 | A kind of analog switching circuit of adjustable opening time |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201821767407.7U CN208836097U (en) | 2018-10-29 | 2018-10-29 | A kind of analog switching circuit of adjustable opening time |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN208836097U true CN208836097U (en) | 2019-05-07 |
Family
ID=66319728
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201821767407.7U Withdrawn - After Issue CN208836097U (en) | 2018-10-29 | 2018-10-29 | A kind of analog switching circuit of adjustable opening time |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109039315A (en) * | 2018-10-29 | 2018-12-18 | 上海艾为电子技术股份有限公司 | A kind of analog switching circuit of adjustable opening time |
-
2018
- 2018-10-29 CN CN201821767407.7U patent/CN208836097U/en not_active Withdrawn - After Issue
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109039315A (en) * | 2018-10-29 | 2018-12-18 | 上海艾为电子技术股份有限公司 | A kind of analog switching circuit of adjustable opening time |
| CN109039315B (en) * | 2018-10-29 | 2023-09-22 | 上海艾为电子技术股份有限公司 | Analog switch circuit for adjusting turn-on time |
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