CN208521939U - Insulated gate bipolar transistor equipment - Google Patents

Abstract

The utility model relates to insulated gate bipolar transistor (IGBT) equipment.The IGBT equipment may include active area, passive region, and the groove extended along the longitudinal axis in the active area.The IGBT may also include the first table top and the second table top, and first table top limits the first side wall of the groove and parallel with the groove, and second table top limits the second sidewall of the groove and parallel with the groove.At least part of first table top may include the active section of the IGBT equipment, and at least part of second table top may include the passive section of the IGBT equipment.

Description

Insulated gate bipolar transistor equipment

Technical field

This specification is related to insulated gate bipolar transistor (IGBT) equipment.

Background technique

Insulated gate bipolar transistor (IGBT) equipment is commonly used in many high voltage applications, such as PFC (PFC) and automotive ignition system, motor driver etc..In some applications, such as motor driver, it may be desirable to IGBT equipment It can satisfy short circuit to bear to require.That is, such IGBT should be able to bear short circuit current (for example, in its emitter Between terminal and collector terminal) continue specific (short) period without damaging equipment.In other application, such as function Rate factor correcting, it may be desirable to which IGBT equipment has low input capacitance (for example, miller capacitance) and fast switching time.Working as In preceding IGBT embodiment, increase short-circuit capacity (time etc. is born in short circuit) can lead to when equipment is on (Vce, sat) Collector and can have the high input capacitance that can increase the facility switching time to the undesirable increase of emitter voltage.Phase Instead, in current IGBT embodiment, improve switch time and/or reduce Vce, it is unfavorable that sat there can be short-circuit ability to bear It influences.

Utility model content

In general aspect, insulated gate bipolar transistor (IGBT) equipment may include active area, passive region and along active The groove that longitudinal axis in area extends.IGBT equipment may also include the first table top and the second table top, which limits ditch The first side wall the first side wall of adjacent trenches (extend etc.) of slot and parallel with groove, which limits the second of groove The side wall second sidewall of adjacent trenches (extend etc.) and parallel with groove.At least part of first table top may include that IGBT is set Standby active section, and at least part of the second table top may include the passive section of IGBT equipment.

In another general aspect, insulated gate bipolar (IGBT) equipment may include active area, passive region and along active The groove that longitudinal axis in area extends.IGBT may also include the first table top and the second table top, which limits groove The first side wall (the first side wall extension of adjacent trenches etc.) and, the second sidewall of second table top restriction groove parallel with groove It is (second sidewall extension of adjacent trenches etc.) and parallel with groove.The active section of the first of IGBT equipment can be included in first In the first part of table top, and the first passive section of IGBT equipment can be included in the second part of the first table top. The active section of the second of IGBT equipment can be included in the first part of the second table top, and the second passive region of IGBT equipment Section is included in the second part of the second table top.

In another general aspect, insulated gate bipolar equipment (IGBT) may include active area, passive region and along active The groove that longitudinal axis in area extends.First uneven table top can limit the first side wall (the first side of adjacent trenches of groove Wall extension etc.) and it is parallel with groove.Second uneven table top can limit the second sidewall (second sidewall of adjacent trenches of groove Extend etc.) and it is parallel with groove.

Detailed description of the invention

Figure 1A-Fig. 1 F is the signal for schematically showing various trench-gate insulated gate bipolar transistor (IGBT) equipment Figure.

Fig. 2A is a part for showing the trench-gate IGBT equipment with active gate section and passive gate section Isometric chart.

Fig. 2 B is the schematic diagram for showing the plan view of a part of trench-gate IGBT equipment corresponding with Fig. 2A.

Fig. 3 A is to show that (groove of such as Fig. 2A and Fig. 2 B-grid IGBT is set for limiting trench-gate IGBT equipment It is standby) in groove mask layout plan view schematic diagram.

Fig. 3 B and Fig. 3 C are the respective planes for showing the mask layout for limiting the groove in trench-gate IGBT equipment The schematic diagram of figure, the mask layout can be used instead of the mask layout of Fig. 3 A.

Fig. 4 A- Fig. 4 G is shown for manufacturing the trench-gate with the groove limited using the mask layout of Fig. 3 A The cross-sectional view of the semiconductor fabrication process of IGBT equipment.

Fig. 5 be schematically show may include one or more oxides filling table tops trench-gate IGBT equipment The schematic diagram of a part.

Fig. 6 A and Fig. 6 B be schematically show may include one or more oxides filling table top sections trench-gate The schematic diagram of the part of IGBT equipment.

Fig. 7 A and Fig. 7 B be schematically show may include one or more oxides filling table top sections trench-gate The schematic diagram of the part of IGBT equipment.

Fig. 8 A- Fig. 8 H is shown for manufacturing groove-grid IGBT equipment (such as Fig. 5, Fig. 6 A, Fig. 6 B, Fig. 7 A and figure The trench-gate IGBT equipment of 7B) semiconductor fabrication process cross-sectional view.

Fig. 9 is the signal for schematically showing the trench-gate IGBT equipment including active table top (for example, active island) Figure, wherein having dielectric (for example, oxide) to terminate and be isolated between active table top.

Figure 10 A- Figure 10 C is to schematically show active table top and associated dielectric isolation and terminate that (they can Trench-gate IGBT equipment is included in, in the trench-gate IGBT equipment of such as Fig. 9) schematic diagram.

Figure 11 A- Figure 11 C be show can be used to form IGBT equipment (IGBT 900 of such as Fig. 9) oxide termination and The schematic diagram of the various columns of isolation.

Figure 12 A- Figure 12 C is the schematic diagram for schematically showing the part of IGBT equipment, which can be included in IGBT In equipment (IGBT 900 of such as Fig. 9).

Figure 13 A- Figure 13 J is shown for manufacturing IGBT equipment (such as Fig. 9, Figure 10 A- Figure 10 C and Figure 12 A- Figure 12 C IGBT equipment) semiconductor fabrication process schematic diagram (cross section and plan view).

Figure 14 is the schematic diagram for schematically showing a part of trench-gate IGBT equipment.

Same reference numerals in each attached drawing indicate identical and/or similar component.Various elements shown in the accompanying drawings are logical The mode for crossing diagram is shown, and may be not necessarily drawn to scale.In addition, the ratio of various attached drawings can be different from each other, this is at least Particular figure shown in being partly dependent on.

The reference character in each attached drawing is provided for explanation and the purpose discussed.For the similar member in identical view Part may not repeat the reference character of similar elements.In addition, for point element reference character shown in a view The element in relevant view can be omitted.For example, the reference character of the point element shown in different views may Not necessarily discuss relative to each of these views.

Specific embodiment

Insulated gate bipolar transistor (IGBT) equipment, IGBT is in many commercial and industrial applications.For example, as some Example, IGBT is in automobile, telecommunication and PFC (PFC) embodiment.Specific the setting of given IGBT application Standby performance parameter is changeable.However, it is necessary to have short-circuit robustness (for example, specific short circuit bear time) and low in general Input the faster switch IGBT of (Miller) capacitor.In general, equipment performance improvement can be accomplished by the following way: reduce collection Electrode is to emitter saturation voltage (Vce, sat)；Turn off energy (for example, switch) loss (Eoff)；Reduce emitter injection point (for example, score of the active emitter area n+ to entire die area, this can reduce saturation current and improve short-circuit receiving number Time) etc..However, another parameter may be negatively affected by improving a device parameter, thus improving the one of equipment performance The cost of a aspect is to generate design tradeoff decision when reducing the other side of equipment performance.

Current method for improving IGBT performance parameter be typically aimed at the two-dimensional cross sectional based on IGBT gate trench come The design of given IGBT is modified, wherein the gate trench is uniform in structure along its length.As an example, IGBT The improvement of equipment performance can be realized by improving front side carrier injection efficiency.However, by reducing active semi-conductor table top Width (for example, from a gate trench to neighbouring or adjacent gate trenches active emitter/source semiconductor table top width Degree) conventional method to improve front side injection efficiency has limited efficiency, and can influence other equipment performance parameter, such as Switch time and/or conducting resistance.In addition, also relying on the portion of active groove length for controlling the current method that front side is injected Divide grid score to realize short-circuit robustness (for example, by the injection of masking source electrode).Such technology is reaching it and is being saturated performance The limit (for example, collector to emitter voltage and saturation current), bear time Consideration without sufficiently solving short circuit.

Method described herein can be by limiting active flute section and non-active trench section and/or increasing active grid Pitch (distance) between polar region section bears the time to improve short circuit, this can reduce since the three-dimensional structure of such IGBT is led The effective mesa width caused.For example, although current method can realize about 1/8 with acceptable Vce, sat and switch time Emitter score, but using method described herein, it can be achieved that with about 1/16 or smaller emitter score IGBT Equipment, while significantly affecting other IGBT performance parameters.

In method described herein, non-active trench section can be limited in the following manner: increasing the area of IGBT grid Dielectric thickness in section replaces the section of semiconductor mesa with dielectric, and/or will with dielectric isolation and termination The active table top (section) of IGBT and other active mesa-isolateds are to increase the pitch between active IGBT trench-gate section.

Such active section and passive section are limited by using three-dimensional IGBT device configuration, these methods can be used for reality The expectation of existing IGBT operation improves.Such configuration can improve IGBT performance for example, by following manner: realize desired short circuit The time is born without significantly affecting other equipment performance parameter, such as collector to emitter saturation current (Ice, sat), current collection Pole is to emitter saturation voltage (Vce, sat) etc..For example, in method described herein, along gate trench length and/or On the opposite side of gate trench, the whole length of IGBT gate trench may be uneven in its structure.In addition, passing through combination P- shields (for example, boron) infusion (those of shown in during such as Figure 13 A- Figure 13 J), even if utilizing relatively narrow nothing Source groove dimensions (for example, in the case where that carrier accumulation may occur), can also keep the expectation of (realization) IGBT equipment to hit Wear (locking) voltage.Although not specifically illustrated for each of described various IGBT embodiments, this type shielding (blocking) infusion also is included in those embodiments.

IGBT (therein defining active gate sections and passive gate section) is designed using such three-dimensional method to be permitted Perhaps flexible design refinement and control, while limiting negative design tradeoff.In brief, such method may include along IGBT Gate trench defines source range and passive section, wherein passive section can limit in the following manner: in gate trench Thick dielectric (for example, oxide) is formed on or near side wall (effectively reduces or effectively remove the correlation of semiconductor mesa Join part), or physically remove at least part of (for example, etching) semiconductor mesa and with dielectric (for example, heat The dielectric and/or air gap of oxide, deposition) replace removed part.Such method may also include active by increasing Grid pitch between gate segment limits active IGBT section and passive IGBT section, and wherein active gate section uses electricity Medium isolation is isolated from each other.In such method, the dielectric isolation between active gate section (for example, active table top) can also The termination of associated IGBT is served as, to eliminate the needs to injection termination structure.

Using methods illustrated and described herein, can design and manufacture with below beneficial to aspect and/or feature IGBT.It is possible, firstly, to (and manufacture) IGBT be designed, wherein front side injection (for example, excess carriers injection) is adjustable.Its It is secondary, compared with current trench grid IGBT, it can reduce the grid capacitance of IGBT (all IGBT as those described herein), so that Active mesa width (emitter) can be increased without significant performance loss, this can produce with improved anti-latch The IGBT equipment of energy.IGBT with short-circuit capacity can be by saving the heavy doping source implant in passive section (for example, n Source implant), it is designed and manufactured using disclosed method, such as wherein trench oxide is thicker, or interrupt active Table top (for example, due to the oxidation of trenched side-wall feature, removes semiconductor mesa material and replaces semiconductor mesa material with dielectric Material, and/or with dielectric isolation and terminate an active IGBT gate trench and another active IGBT gate trench Isolation).For example, can be operated by masking or be saved in the active region (for example, invalid section) of IGBT by autoregistration Remove source implant, wherein infusion be used to limit the dielectric barrier of passive section, or be used for be isolated and termination have The dielectric barrier of source IGBT section.

For example, saving heavy doping source implant from the passive section of IGBT (for example, wherein dielectric is thicker or For replacing (part or all of) semiconductor mesa) gate charge of IGBT can be reduced (for example, in passive section, wherein not Need to form conducting channel).In the method disclosed herein for wherein increasing grid pitch using dielectric termination and isolation In, such as in being shown in such as method of Figure 10 A- Figure 10 C, the active region around active gate section reduces, this also reduces The saturation current of IGBT, enhances injection efficiency, and therefore reduce Vce, sat.

In various views, for the purpose for discussing and illustrating, certain features of IGBT equipment can be shown.In embodiment party In formula, add ons can be included in such IGBT equipment, add infusion, metal interconnecting layer, passivation, encapsulation etc.. For clear and explanation purpose, this class component is not shown, in order to avoid the specific side of the fuzzy IGBT equipment for discussing and illustrating Face.

Figure 1A-Fig. 1 F is to schematically show various trench-gate insulated gate bipolar transistor (IGBT) equipment or IGBT The schematic diagram of embodiment.The view being shown in Figure 1A-Fig. 1 F is illustrated as the plane (example of (or the part of IGBT) various IGBT Such as, top-down) figure, the IGBT can the middle realization (in silicon substrate, silicon carbide substrates etc.) in the semiconductor substrate.

Figure 1A is the schematic diagram for schematically showing the embodiment of IGBT 100.As shown in Figure 1A, IGBT 100 includes Terminator 110 and active area 120.As described herein, active area 120 may include the active IGBT section of IGBT 100 and passive IGBT section.In addition, though the terminator 110 of IGBT 100 in figure 1A is illustrated as entirely around active area 120, but one In a little embodiments, terminator 100 can be partially around active area 120.In other embodiments, terminator 110 can be used Multiple non-adjacent terminators around active area 120 are set to realize.

Figure 1B is the reality for schematically showing the active area 120b that can be realized in IGBT (IGBT 100 of such as Figure 1A) Apply the schematic diagram of mode.The active area 120b (only a part of its active area 120 that can show IGBT 100) of Figure 1B includes half Conductor table top 130b, in this example, the semiconductor mesa can be used as emitter mesa operation.Active area 120b further includes electric Jie Matter part 140b, the dielectric portion may include oxide, air gap, polysilicon and/or other materials appropriate.Dielectric portion 140b can limit the passive section of the IGBT including active area 120b.As described herein, in some embodiments, active area The dielectric portion 140b of 120b can be by oxide definition in the side of the groove of IGBT (for example, IGBT those of shown in Fig. 3 A) Feature (characteristic of semiconductor) on wall is formed.

Active area 120b may also include conductive trench electrode 150b, which, which can be, is arranged in respective groove In doped polycrystalline silicon electrode, wherein groove is formed by etch process.The groove of electrode 150b can prolong along longitudinal axis L It stretches.For purposes of illustration, longitudinal axis L is shown in each of Figure 1B-Fig. 1 F.Although not showing clearly in the other drawings Out, but the groove in those attached drawings still can be described as extending along longitudinal axis (such as axis L).According to embodiment party Formula, trench electrode 150b can be the combination of gate electrode, emitter electrode or gate electrode and emitter electrode.Wherein set The groove for having set electrode 150b can be lined with gate-dielectric 160b, such as silica.In some embodiments, grid Dielectric 160b can be included in the dielectric portion 140b of active part 120b.

As shown in Figure 1B, active area 120b may also include heavy doping source implant 170b, the heavy doping source implant The active IGBT section of active area 120b can be limited.In some embodiments, source implant 170b can be in dielectric portion Extend between 140b.In addition, additional source implant 170b can be included in the passive IGBT limited by dielectric portion 140b In table top 130b except section.The specific arrangements of the various elements of active area 120b will depend on specific IGBT embodiment.

Fig. 1 C is to schematically show the active area (active area) that can be realized in IGBT (IGBT 100 of such as Figure 1A) The schematic diagram of the embodiment of a part of 120c.The active area 120c of Fig. 1 C be (its active area 120 that can show IGBT 100 Only a part) it include semiconductor mesa 130c, in this example, which can be used as emitter mesa operation.It is active Area 120c further includes dielectric portion 140c.The dielectric portion 140c for interrupting table top 130c can be limited including active area 120c's The passive section of IGBT.As described herein, dielectric portion 140c can by oxide definition in IGBT (for example, shown in Fig. 3 B Those IGBT) groove side wall on feature (characteristic of semiconductor) formed, or can by physically removing table top 130 Semiconductor material and with one or more dielectric substances (for example, dielectric of thermally grown dielectric and/or deposition) come It is formed instead of the semiconductor material removed with generating oxide filling table top or oxide filling table top section.In some realities It applies in mode, dielectric portion 140c may also include air gap (for example, closed air gap), polysilicon (for example, undoped polycrystalline Silicon) and/or other any amount of materials appropriate.

Active area 120c may also include conductive trench electrode 150c, which, which can be, is arranged in respective groove In doped polycrystalline silicon electrode, wherein groove is formed by etch process.As the electrode 150b of active area 120b, according to The trench electrode 150c of particular implementation, active area 120c can be gate electrode, emitter electrode or gate electrode and hair The combination of emitter-base bandgap grading electrode.Which provided the grooves of electrode 150c can be lined with gate-dielectric 160c, such as silica. In some embodiments, gate-dielectric 160c can be included in the dielectric portion 140c of active part 120c.

As shown in Figure 1 C, active area 120c may also include heavy doping source implant 170c, the heavy doping source implant The active IGBT section of active area 120c can be limited.In some embodiments, source implant 170c can be in dielectric portion Extend between 140c.In addition, additional source implant 170c can be included in the passive section limited by dielectric portion 140c Except table top 130c in, the dielectric portion interrupt table top 130c semiconductor material.As active area 120b, active area The specific arrangements of the element of 120c will depend on specific IGBT embodiment.

Fig. 1 D is schematically show the active area 120d that can be realized in IGBT (IGBT 100 of such as Figure 1A) one The schematic diagram of partial embodiment.In some embodiments, active area 120d can also be realized in the IGBT 900 of Fig. 9.

As shown in figure iD, active area 120d (only a part of its active area 120 that can show IGBT 100) includes partly leading Object table face 130d, in this example, the semiconductor mesa can be used as emitter mesa operation.Active area 120d further includes dielectric Part 140d, the dielectric portion replace semiconductor mesa or limit the end of the active section of the IGBT including active area 120d Only or it is isolated.In other words, dielectric portion 140d limits the passive section of the IGBT including active area 120d.Such as this paper institute State, dielectric portion 140c can by oxide definition semiconductor substrate (for example, Figure 11 A- Figure 11 C shown in those of semiconductor Substrate) in feature (characteristic of semiconductor) formed, or can be by physically removing semiconductor material and with a kind of or more Dielectric substance (for example, dielectric of thermally grown dielectric and/or deposition) is planted to replace removed semiconductor material It is formed.In some embodiments, dielectric portion 140d may also include air gap (for example, closed air gap), polysilicon (example Such as, undoped polysilicon) and/or other any amount of materials appropriate.

Active area 120d may also include conductive trench electrode 150d, which, which can be, is arranged in respective groove In doped polycrystalline silicon electrode, wherein groove is formed by etch process.According to particular implementation, the groove of active area 120d Electrode 150d can be the combination of gate electrode, emitter electrode or gate electrode and emitter electrode.Which provided electrodes The groove of 150d can be lined with gate-dielectric 160d, such as silica.In some embodiments, gate-dielectric 160d It can also be included in the dielectric portion 140d of active part 120d.

As shown in figure iD, active area 120d can also be in table top 130d (for example, along every in gate-dielectric 160d It is a) it include heavy doping source implant 170d, which limits the active IGBT section of active area 120d.

Fig. 1 E is schematically show the active area 120e that can be realized in IGBT (IGBT 100 of such as Figure 1A) one The schematic diagram of partial embodiment.Active area 120e includes similar with those elements shown in Figure 1B and Fig. 1 C, but not Element in same active IGBT section and passive IGBT section.For example, active area 120e includes table top 130e, dielectric portion 140e (for example, limiting passive section), conductive electrode 150e, gate-dielectric 160e and heavy doping source implant 170e (for example, defining source range).As active area 120b and 120c, in some embodiments, source implant 170e can Extend between dielectric portion 140e.(or extension) source implant 170e can be included in by dielectric in addition, additional In table top 130e except the passive section that part 140e is limited, which interrupts the semiconductor material of table top 130e. As active area 120e, the specific arrangements of the element of active area 120e will depend on specific IGBT embodiment.

Fig. 1 F is to schematically show the active area (active area) that can be realized in IGBT (IGBT 100 of such as Figure 1A) The schematic diagram of the embodiment of a part of 120f.The active area 120f of Fig. 1 F be (its active area 120 that can show IGBT 100 Only a part) it include semiconductor mesa 130f, in this example, which can be used as emitter mesa operation.It is active Area 120f further includes dielectric portion 140f, which may include the oxide, (doping or not of air gap and/or polysilicon The polysilicon of doping).Dielectric portion 140f can limit the passive section of the IGBT including active area 120f.As described herein, The dielectric portion 140f of active area 120f can by oxide definition IGBT those of (for example, Fig. 3 A shown in IGBT) ditch Feature (characteristic of semiconductor) on the side wall of slot limits air gap and/or with polysilicon filling oxidation dielectric material come shape At.

Active area 120f may also include conductive trench electrode 150f, which, which can be, is arranged in respective groove In doped polycrystalline silicon electrode, wherein groove is formed by etch process.According to embodiment, trench electrode 150f can be grid The combination of pole electrode, emitter electrode or gate electrode and emitter electrode.Which provided the grooves of electrode 150f to be served as a contrast There are gate-dielectric 160f, such as silica.In some embodiments, gate-dielectric 160f can be included in active portion Divide in the dielectric portion 140f of 120f.

As shown in fig. 1F, active area 120f may also include heavy doping source implant 170f, the heavy doping source implant The active IGBT section of active area 120f can be limited.In some embodiments, source implant 170f can be in dielectric portion Extend between 140f.(or extension) source implant 170f can be included in and be limited by dielectric portion 140f in addition, additional Passive section except table top 130f in.The specific arrangements of the element of active area 120f will depend on specific IGBT embodiment party Formula.

Fig. 2A is the isometric chart for showing a part of the trench-gate IGBT 200 with active section and passive section, Such as discussed relative to such as Figure 1B.Fig. 2 B is to show trench-gate corresponding with the trench-gate IGBT 200 of Fig. 2A The schematic diagram of plane (top-down) figure of a part of IGBT equipment.As shown in Figure 2 A and 2 B, IGBT 200 may include platform Face 230, dielectric portion 240 (the passive section for limiting IGBT 200), conductive electrode 250 and gate-dielectric 260.? In some embodiments, gate-dielectric 260 also is included in dielectric portion 240.

Although not specifically illustrating in fig. 2b, as shown in Figure 2 A, IGBT 200 may also include the injection of heavy doping source electrode Object 270 (the active section for limiting IGBT 200).Masking feature 242 is also shown in Fig. 2A, which can be used for limiting The masking feature of semiconductor structure can be then oxidized to limit dielectric portion 240.The example of such masking feature It is shown in Fig. 3 A- Fig. 3 C, wherein the embodiment that can be used for manufacturing the manufacturing process of IGBT 200 is shown in Fig. 4 A- Fig. 4 G.

In IGBT 200, table top 230 can be emitter mesa (for example, combination of active table top and passive table top). Table top 230 may include p trap and/or heavily-doped p-type infusion (for example, heavy body implant object).In the embodiment party including passive table top In formula, table top 230 can save and (not include) source implant 270 (for example, it may be passive table top).In certain embodiments In, such passive table top can improve during the shutdown of IGBT 200 removes excess from passive section, therefore can mention High IGBT turn-off speed.In addition in fig. 2, the open area of IGBT 200 can be semiconductor substrate materials, and such as intrinsic half Conductor substrate material, dope semiconductor substrates material, injection junction field effect transistor (JFET) layer, doped epitaxial layer etc..Half Conductor substrate material is not shown in fig. 2, therefore will not obscure the element of IGBT 200.

According to particular implementation, the width of conductive electrode 250 be can be constant (as shown in Figure 2 A), or can had Change (as shown in Figure 2 B) between source range and passive section.In addition, as shown in Figure 2 A, the central part of groove is (for example, wherein Formed conductive electrode 250 part) than groove exterior section (for example, wherein formed limit IGBT 200 passive section Dielectric portion 240 part) it is deeper.

Fig. 3 A is to show that (groove of such as Fig. 2A and Fig. 2 B-grid IGBT is set for limiting trench-gate IGBT equipment It is standby 200) in groove mask layout 300a plan view schematic diagram.In Fig. 3, for the figure shown in mask layout 300a Case indicates that masking pattern, the masking pattern can be used for limiting the semiconductor material to remove by subsequent etching processes Region.The etch process can be used for limiting groove, and therefore further define the active section and/or nothing that can be used for limiting IGBT The semiconductor material structures (not removing semiconductor material wherein) of source range.

In addition, the mask layout 300a of Fig. 3 A is shown with the line for limiting notch 1 (showing twice), notch 2 and notch 3.This A little cutting lines correspond to the associated viewgraph of cross-section in Fig. 4 B- Fig. 4 G, and they, which show, can be used for manufacturing groove-grid IGBT The semiconductor fabrication process of (the trench-gate IGBT 200 of such as Fig. 2A and Fig. 2 B).Fig. 3 A further includes that (it can be corresponded to axis X Axis L in Figure 1B-Fig. 1 E) and axis Y, they are by the exemplary dimensions relative to the feature limited by mask layout 300a To refer to.

As shown in Figure 3A, by limiting the part for the semiconductor material to be removed, masking layer 300a further defines semiconductor material Expect the part of (for example, table top 330a), once the trench features of active section and passive section such as pass through anisotropic etching Technique is removed, which still retains.For example, masking layer 330a limits the central slot sections of the passive section of corresponding IGBT 350a, such as the deeper slot part including conductive electrode 250 shown in Fig. 2A.Masking layer 300a further defines pectinate texture, The pectinate texture includes the finger-shaped material 341a for the semiconductor material to remove by trench etch, and still protects after trench etch The finger-shaped material 342a of the semiconductor material stayed.In embodiments, finger-shaped material 342a can be used (for example, oxidation, filling etc.) With formation (restriction etc.) dielectric portion (for example, dielectric portion 240), which limits IGBT equipment (such as IGBT equipment 200) passive section.

Masking layer 300a may also define source range groove 351a, which can be lined with gate-dielectric simultaneously And it is filled with conductive electrode, such as gate electrode and/or emitter electrode are all as described herein.Although being limited by masking layer 300a The specific dimensions of fixed feature will depend on particular implementation, but be below mask layout 300a various features it is exemplary Size.In embodiments, along axis X can be in the range of 1-100 microns (μm) to the distance of notch 1 from notch 1, root According to the width of the table top 330a in passive section, each of finger-shaped material 341a and 342a can be in 0.1- along the length of axis Y In the range of 0.5 μm, and the width of each of finger-shaped material 341a and 342a along axis X can also be in 0.1-0.5 μm of model In enclosing.Active section table top can be greater than or equal to 0.5 μ along the width of axis Y (for example, between active section groove 351a) m.Distance, size and spacing can particular implementation based on associated trench-gate IGBT and desirable operational parameters and change.

In some embodiments, in the IGBT equipment (such as IGBT equipment 200) manufactured using masking layer 300a, by The dielectric portion that finger-shaped material 342a is formed can not merge on table top 330a (for example, can not contact from adjacent trenches Dielectric portion).In such embodiment, the dielectric portion formed by finger-shaped material 342a can not stop hole current, And therefore can realize faster turn-off speed, though injection enhancing (IE) effect may not as good as other embodiments (for example, Using strong like that in masking layer 300b).For example, in the embodiment that wherein dielectric portion does not merge on table top, threshold value Voltage in that region (for example, in passive section) will be higher, this is significantly reduced the associated saturation in passive section Electric current, and realize better short-circuit capacity.Although these regions are still in addition, passive section can have high threshold voltage The some reversions for allowing current spread can be provided during conduction.Therefore, Vce, sat, Ice, the compromise between sat and Eoff It can be easy to accomplish for given embodiment.

Fig. 3 B and Fig. 3 C be show mask layout 300b for limiting the groove in trench-gate IGBT equipment and The schematic diagram of the respective planes figure of 300c.In some embodiments, mask layout 300b or 300c can be used to replace Fig. 3 A Mask layout 300a.Due to mask layout 300b and 300c be similar to mask layout 300a, described above relative to Fig. 3 A's The details that masking layer 300a is discussed will not repeat herein.

As shown in Figure 3B, mask layout 300b limits semiconductor mesa 330b, in this embodiment, the semiconductor mesa It is active table top.That is, as in figure 3b as it can be seen that (for example, between central slot sections 350b in passive segments area Region 340b in) the length of finger-shaped material 341a and 342a make finger-shaped material 341b (semiconductor material of removal) and 342b (remaining semiconductor material) is adjacent to each other.It is such when the finger-shaped material 342a of remaining semiconductor material is oxidized, fills etc. Structure can produce dielectric portion, the dielectric portion 140c in such as Fig. 1 C, which interrupts table top 330b.Also It is to say, in such embodiment, the semiconductor material of table top 330b is not continuous (for example, in Fig. 3 B from left to right), But the dielectric portion formed by finger-shaped material 342b interrupts (segmentation etc.).In such embodiment, solid dielectric portion Dividing may be formed in the passive section of associated IGBT.Although storing (position, exist) under such solid dielectric structure Carrier can reduce the conducting resistance of corresponding IGBT, but transverse conductance distance can increase shutdown (under dielectric medium structure) Speed (for example, shutdown loss Eoff can be increased).

As shown in Figure 3 C, mask layout 300c limits table top 330c, and in this embodiment, which may include passive region Section, wherein the part of semiconductor material 341c can be removed and the corresponding part of remaining semiconductor material 340c (for example, After trench etch) (for example, oxidation) can be used to form the dielectric portion for the passive section for limiting table top 330c.Herein In class embodiment, the side that the active section of table top 330c can be similar with mask layout 300a is arranged (by semiconductor portions What 340c was formed) between dielectric portion, which limits passive IGBT section.

Fig. 4 A- Fig. 4 G is shown for manufacturing the trench-gate having using the mask layout 300a of Fig. 3 A groove limited The cross-sectional view of the semiconductor fabrication process of pole IGBT 400.For succinct and clear purpose, shown in Fig. 4 A- Fig. 4 G Each processing step of reason process is not illustrated or is described by details in the following discussion.Therefore, Fig. 4 A- Fig. 4 G's is every A multiple semiconductor processing operations of attached figure representation.It is performed to manufacture specific the half of IGBT equipment (such as IGBT equipment 400) Conductor processing operation (and associated processing parameter) will depend on particular implementation, such as desired operation of IGBT equipment Parameter (for example, time, breakdown voltage, Vce, sat, input capacitance etc. are born in short circuit).

In addition, in Fig. 4 B- Fig. 4 G, to corresponding section in each of the line notch 1, notch 2 and notch 3 along Fig. 3 A The corresponding viewgraph of cross-section of view is illustrated as showing the structure of IGBT 400, and in some embodiments, which corresponds to figure The structure of the IGBT 200 of 2A and Fig. 2 B.Corresponding cutting line corresponding to each of these cross section views is in Fig. 4 B- Fig. 4 G Each of in show.

A referring to fig. 4, semiconductor (for example, N-shaped) substrate 401 can be used for manufacturing IGBT equipment 400.With the IGBT of Figure 1A As 100, IGBT equipment 400 may include terminator 110 and active area 120.The terminator of IGBT 400 is only shown in Figure 4 A, Because Fig. 4 B- Fig. 4 G shows the viewgraph of cross-section of the active area 120 along the cutting line being shown in Fig. 3 A, as described above.

As shown in Figure 4 A, the terminator 110 of IGBT 400 may include the terminator N+ 402 (for example, arsenic and/or phosphorus doping ), (it can have than the higher n-type doping of substrate 401 for P+ termination ring 404 (for example, boron doped) and N-shaped enhancement layer 406 Concentration).The terminator 110 of IGBT 400 may also include silicon selective oxidation (LOCOS) layer 408.In the active area 120 of IGBT 400 In, as shown in Figure 4 A, N-shaped JFET layer 412 may be formed in substrate 401, can control the shape of LOCOS layer 408 (for example, bird Beak shape) pad oxide layer 410 may be formed at (and one of the neighbouring LOCOS layer 408 of terminator 110 of active area 120 Point) top, and tetraethyl orthosilicate (TEOS) layer 414 may be formed at 120 top of terminator 110 and active area.TEOS layer 414 It may act as the hard mask layer for limiting trench features (trench features of the masking layer 300a of such as Fig. 3 A).

B referring to fig. 4 shows the viewgraph of cross-section in the active area 120 of IGBT 400, wherein as shown in Fig. 4 B, that A little viewgraph of cross-section correspond respectively to the line notch 1, notch 2 and notch 3 of Fig. 3 A.In figure 4b, photoetching and erosion are had been carried out Operation is carved to pattern 414 hard mask layer of TEOS, remove photoresist and is etched using such as isotropic plasma To etch the trench features of masking layer 300a.In some embodiments, can come in the target depth TD1 in 5-7 μ m Etch trench features.The reference character of various masking features (trench features) corresponding to masking layer 300a Fig. 4 B (and figure It is used to indicate in 4C) in a cross section view along the position of the various trench features of those of cutting line.For example, Fig. 4 B is indicated Table top 330a, the center groove 350a of passive IGBT section, the groove finger-shaped material 341a of removal, remaining groove finger-shaped material 342a And active section groove 351a.

Referring now to Fig. 4 C, it can grow and remove sacrifical oxide (SacOX), this can help to remove by the groove of Fig. 4 B Any damage caused by etch process to semiconductor substrate 401 (and JFET layer 412).After removing SacOX layers, it can be performed Gate oxidation process, it is (all which can form gate oxide 460 on the side wall of active section groove 351a As shown in the notch 1 for Fig. 4 C), and the dielectric portion 340a of passive section is formed (such as 2 He of notch of Fig. 4 C Shown in 3).As for shown in the notch 2 in Fig. 4 C, the center groove 350a of passive section is stayed open, and since semiconductor refers to Volume expansion of the shape object 342a in its oxidation, the oxidation of semiconductor finger-shaped material 342a (are grasped from gate oxidation and/or SacOX Make) it can be along (and the exterior section of non-active trench section, wherein forming the groove finger-shaped material 341a and residue of removal of notch 3 Semiconductor finger-shaped material 342a) generate dielectric 340a adjacent block.

Referring now to Fig. 4 D, conductive electrode 450 (for example, DOPOS doped polycrystalline silicon) may be formed at active section groove 351a and nothing In source range center groove 350a.As shown in Figure 4 E, dopant injection and thermal drivers operation can be performed with the shape in table top 330a At p trap 430 and n-type source infusion 440, wherein p trap 430 is formed in active section (notch 1) and passive section (2 He of notch 3) in, and source implant 440 is made only in active section (notch 1).In some embodiments, source implantation process can It is executed using mask, and other embodiments (such as using those of the masking layer 330b of Fig. 3 B embodiment) In, source implant 440 can be self-aligned (for example, wherein source implant is extended continuously between non-active trench section The dielectric portion of passive section stops).

As illustrated in figure 4f, metal dielectric layer 460 before being formed, such as phosphosilicate glass (PSG) and/or TEOS electricity Dielectric layer.Referring now to Fig. 4 G, the metal that can form the various elements of IGBT 400 and other features of IGBT 400 is mutual Even.These features may include for example p-type enhancing infusion 462, source contact 464, metalization layer 466 and 476, passivation layer 468, And conductive electrode contact 474 (for example, grid and/or emitter contact).According to the embodiment, supplementary features can be formed simultaneously And/or person can eliminate one or more of shown feature of IGBT 400.

Fig. 5 be schematically show may include one or more oxides filling table tops trench-gate IGBT 500 The schematic diagram of a part.The IGBT 500 of Fig. 5 includes multiple grooves 510,520,530,540,550,560,570 and 580. IGBT 500 further includes multiple table tops 515,525,535,545,555,565 and 575, and wherein each of table top 515-575 points It is not arranged between two in groove 510-580.In some embodiments, IGBT 500 can be used and be shown in Fig. 8 A- Fig. 8 H In semiconductor fabrication process manufacture, this is hereinafter described.

In IGBT 500, groove 510-580 can respectively be lined with dielectric (for example, gate oxide) and including setting In corresponding conductive electrode (for example, DOPOS doped polycrystalline silicon) wherein.According to particular implementation, the groove 510- of IGBT 500 Conductive electrode in 580 can be the combination of gate electrode, emitter electrode or gate electrode and emitter electrode.Table top 515-575 can be active emitter table top, passive transmitting pole table top, oxide filling table top, the passive table top that floats or have The combination of source emitter mesa, passive transmitting pole table top, oxide filling table top and the passive table top that floats.As described above, oxidation Object filling table top (or oxide fills table top section) can be used for limiting the passive section of IGBT 500.According to particular implementation side Formula, these passive sections (for example, passive part) of IGBT 500 may also comprise passive transmitting pole table top and/or float passive Table top, they can be used for realizing the particular performance characteristics of IGBT 500, conducting resistance, switch time, input capacitance etc..

The following table 1 shows the various illustrative embodiments (for example, arrangement) of IGBT 500, wherein following abbreviation makes in table With: OFM indicates oxide filling stage face (for example, the passive section for limiting IGBT 500)；AEM indicates active emitter table top (such as comprising the gate electrode groove setting in the active section of source implant and adjacent I GBT 500), PEM instruction Passive transmitting pole table top, the passive transmitting pole table top include P+ infusion in contact, but not including that n+ infusion (for example, In its part that may be disposed at passive section or IGBT 500, and the removal that can improve the charge of storage is fast to improve shutdown Degree)；The passive table top of FPM instruction floating, which includes p trap infusion, but saves P+ infusion and n+ source electrode Infusion；GT indicates gate electrode groove；And ET indicates emitter electrode groove.It is arranged in the passive section of IGBT 500 Gate electrode groove (GT) can improve such as oxide filling table top under passive section in carrier accumulation (example Such as, this can reduce the conducting resistance of IGBT 500 by enhancing the transverse conductance below passive section).Emitter electrode groove (ET) all shielding and noise suppressed for example can be provided adjacent to (adjacent) gate electrode groove, and can also reduces corresponding IGBT equipment Negative grid electrode capacitance.

In some in the embodiment (being designated as embodiment 1-8) in table 1, particular table and groove type are (in use State abbreviation) only the subgroup of groove shown in fig. 5 and table top is shown.In these embodiments, the unspecified groove of Fig. 5 and Table top is indicated as N/A in table 1, and those grooves and table top (being designated as N/A) can be not as the corresponding ditches of corresponding IGBT Slot and table top arrangement a part and including.In other words, each embodiment instruction in table 1 can be realized in IGBT 500 The arrangement of groove and mesa type.In some embodiments, these of groove and table top exemplary patterns can be in IGBT 500 Active area in repeat.For example, in embodiment 1, shown in pattern can be below active emitter table top 565 from groove 570 Gate trench electrode in (as groove 510) starts to repeat, wherein the table top 515-565 and groove 520- of embodiment 1 560 gate electrode being arranged in groove 570 continues below.In other embodiments, the different arrangements of groove and table top (for example, pattern) can be used in combination with each other in IGBT 500.For example, the exemplary arrangement of embodiment 1 and embodiment 2 can be handed over For the active area to form IGBT 500.Other combinations (including combination not specifically illustrated in table 1) are also possible.

Table 1

Fig. 6 A and Fig. 6 B be schematically show may include one or more oxides filling table top sections 630 groove- The schematic diagram of the plan view of the part of grid IGBT equipment 600a and 600b.The arrangement of IGBT equipment 600a and 600b can be such as Including in the active area 120 of IGBT 100 shown in figure 1A.

IGBT equipment 600a and 600b further include groove 610, which can be gate electrode groove, emitter electrode ditch The combination of slot or gate electrode groove and emitter electrode groove, this depends on particular implementation.IGBT equipment 600a and 600b further includes active emitter section.As shown in Figure 6A, as illustrated as a plan view, the active emitter table section of IGBT 600a Section 620 can be aligned vertically each other.Equally, in the IGBT 600a of Fig. 6 A, in the plan view, oxide fills (passive) table top Section 630 can be aligned vertically each other.

In contrast, as shown in Figure 6B, as illustrated as a plan view, in the active emitter table top section 630 of IGBT 600b It each can be vertically-aligned with neighbouring (adjacent) oxide filling (passive) table top section 630.As the IGBT 500 of Fig. 5, In some embodiments, semiconductor fabrication process shown in Fig. 8 A- Fig. 8 H can be used to manufacture for IGBT 600a and 600b, this Hereinafter have been discussed.

Fig. 7 A and Fig. 7 B be schematically show may include one or more oxides filling table top sections trench-gate The schematic diagram of the part of IGBT equipment 700a and 700b.The arrangement of IGBT equipment 700a and 700b can be for example including shown in Figure 1A IGBT 100 active area 120 in.

In IGBT equipment 700a and 700b, trench electrode (for example, gate trench electrode) can be implemented as matrix, wherein Active emitter table top section 720 and oxide filling table top section 730 are electric in groove as island or with brick wall type configuration setting In pole 710.Other arrangements other than those arrangements shown in Fig. 7 A and Fig. 7 B are possible.For example, IGBT 700a Active emitter table top section 720 and oxide filling table top section 730 can with for the active emitter section in Fig. 6 Bb The 620 arrangement offsets similar with shown in oxide filling (passive) table top section 630, wherein being given in the plan view of Fig. 7 A Active emitter section 720 and neighbouring (adjacent) oxide filling table top section 730 are vertically-aligned.With the IGBT 500 of Fig. 5 with And Fig. 6 A with the IGBT 600a of Fig. 6 B as 600b, in some embodiments, Fig. 8 A- can be used in IGBT 700a and 700b Semiconductor fabrication process shown in Fig. 8 H manufactures, this hereinafter has been discussed.

Fig. 8 A- Fig. 8 H is to show for manufacturing groove-the cross-sectional view of the semiconductor fabrication process of grid IGBT 800, should Trench-gate IGBT includes oxide filling table top to limit the passive section of IGBT 800.It is shown in partly leading in Fig. 8 A- Fig. 8 H Body technology can be used for manufacturing IGBT, which, which has, is such as shown in Fig. 5 (and upper table 1), Fig. 6 A- Fig. 6 B and Fig. 7 A- Fig. 7 B Those of the configuration of configuration etc and the other embodiments of all those embodiments etc as disclosed herein.

As the semiconductor fabrication process of Fig. 4 A- Fig. 4 G, for succinct and clear purpose, shown in Fig. 8 A- Fig. 8 H Each processing step of process flow do not illustrated or described by details in the following discussion.Therefore, Fig. 8 A- Fig. 8 H Each of the multiple semiconductor processing operations of attached figure representation.It is performed to manufacture the spy of IGBT equipment (such as IGBT equipment 800) Particular implementation, such as expectation of IGBT equipment will be depended on by determining semiconductor processing operation (and associated processing parameter) Operating parameter (for example, time, breakdown voltage, Vce, sat, input capacitance etc. are born in short circuit).

In addition, showing terminator 110 in each viewgraph of cross-section in Fig. 8 A- Fig. 8 G and active area 120 (such as existing In Figure 1A).In some embodiments, the viewgraph of cross-section of the active area 120 in Fig. 8 B- Fig. 8 H can correspond in Fig. 5 along The view of line 8, but as an example, at least some cases, it is different with the quantity of table top to be shown in the groove in Fig. 8 B- Fig. 8 H In the quantity of groove and table top shown in Figure 5.In embodiments, similar hatching can be included in Fig. 6 A- Fig. 7 B Either one or two of in, and the viewgraph of cross-section of the active area 120 of Fig. 8 A- Fig. 8 H can further correspond to such hatching.

Referring to Fig. 8 A (it has configuration identical with Fig. 4 A), semiconductor (for example, N-shaped) substrate 801 can be used for manufacturing IGBT equipment 800.As described above, IGBT equipment 800 may include terminator 110 and active area 120.As shown in Figure 8 A, IGBT 800 terminator 110 may include the terminator N+ 802 (for example, arsenic and/or phosphorus doping), P+ termination ring 804 (for example, boron doping ) and N-shaped enhancement layer 806 (it can have than the higher n-type doping concentration of substrate 801).The terminator 110 of IGBT 800 is also It may include silicon selective oxidation (LOCOS) layer 808.In the active area 120 of IGBT 800, as shown in Figure 8 A, N-shaped JFET layer 812 It may be formed in substrate 801, pad oxide layer 810 may be formed at (and neighbouring LOCOS layers of terminator 110 of active area 120 808 a part) top, and tetraethyl orthosilicate (TEOS) layer 814 may be formed on terminator 110 and active area 120 Side.As the TEOS of Fig. 4 A layer 414, TEOS layer 814 may act as hard mask layer with the groove for limiting IGBT 800.

Referring to Fig. 8 B, executable photoetching and etching operation are to pattern for removing 814 hard mask layer of TEOS Photoresist and etching groove 845 (for example, using isotropism trench etch), wherein forming groove 845 also by table top 847 It is limited in active area 120 (and in this example, terminator 120).In some embodiments, the groove of IGBT 800 845 can correspond to the groove 510-580 of Fig. 5, and the table top 847 of IGBT 800 can correspond to the table top 515-575 of Fig. 5.With figure The trench features of 4B are the same, and the groove 845 of Fig. 8 B can also be etched in the target depth in 5-7 μ m.

Referring now to Fig. 8 C, it can grow and remove sacrifical oxide (SacOX), this can help to remove by the groove of Fig. 8 B Any damage caused by etch process to semiconductor substrate 801 (and JFET layer 812).After removing SacOX layers, it can be performed Gate oxidation process, this can form gate oxide 860 on the side wall of groove 845.

Referring now to Fig. 8 D, conductive electrode 850 (e.g., including DOPOS doped polycrystalline silicon) it may be formed in groove 845.Such as figure Shown in 8E, dopant injection and thermal drivers operation can be performed to form p trap 830 and n-type source infusion 840 in table top 847 (for example, such as shown in the illustrative embodiments in Fig. 8 E).In some embodiments, mask can be used to hold Row source implantation process, and in other embodiments, it (can be filled out for example, forming oxide in the processing operation of Fig. 8 F and Fig. 8 G Fill table top and/or oxide filling table top section) source implant 840 is formed later.In such embodiment, source electrode injection Object 840 can be it is self aligned, for example, wherein source implant can be oxidized object filling table top or limit IGBT 800 The oxide filling table top section of passive section stops.In such embodiment, source implant 840 therefore will be in IGBT Autoregistration in 800 active section.

Referring now to Fig. 8 F, lithography operations can be performed to form masking layer, such as photoresist masking layer.Then it can hold Gate oxide above part or section of the row gate oxide etching to remove silicon mesa 847 to be removed, to limit Oxide fills table top.After removing gate oxide corresponding with masking layer, isotropism or anisotropy can be performed Semiconductor (for example, silicon) etches (it can be similar to the etching for being used to form groove 845) to remove semiconductor material partly to lead Gap 874 is generated (for example, to limit IGBT in the part that wherein form oxide filling table top in object table face 847 or section 800 passive section).

Referring to Fig. 8 G, can be performed dielectric thermal oxide and/or chemical vapor deposition (CVD) (for example, CVD TEOS) with Limit (formed, generated etc.) oxide filling table top section 875.As illustrated in figure 8h, oxide filling table top section 875 may include The air gap 876 of dielectric enclosed.These air gaps 876 can reduce the total stress in semiconductor substrate 801 and reduce semiconductor substrate Any bending in 801, the stress that such as may be caused or be generated by the oxidation technology for being used to form oxide filling table top 875 Or bending.It is filled up completely with the gap 874 in the table top 847 of wherein Fig. 8 F with dielectric (for example, oxide) or almost complete The embodiment of full packing is compared, and stress or bending can be reduced.

As further shown in Fig. 8 G, conductive electrode 850 can be connected to the emitter terminal or gate terminal of IGBT 800, This is suitable for particular implementation.In fig. 8, using with identical acronym used in upper table 1, be connected to The conductive electrode of the emitter terminal of IGBT 800 is indicated as ET, and is connected to the gate terminal of (for example, restriction) IGBT 800 The conductive electrode of son is indicated as GT.

As illustrated in figure 8h, metal dielectric layer 860 before being formed, such as phosphosilicate glass (PSG) and/or TEOS electricity Dielectric layer.As further shown in Fig. 8 H, the gold of the various elements of IGBT 800 and other features of IGBT 800 can be formed Belong to interconnection.These features may include such as p-type enhancing infusion 862, source contact 864, metalization layer 866 and 876 and blunt Change layer 868.Although not shown in Fig. 8 H, can also be formed with the contact of conductive electrode 850 (for example, gate contacts and/or hair Emitter-base bandgap grading contact).According to particular implementation, supplementary features can be formed and/or can be eliminated in the shown feature of IGBT 800 One or more.

Fig. 9 is to schematically show the trench-gate IGBT 900 including active table top 920 (for example, active table top island) Schematic diagram, which has the dielectric (example that (and surround the active table top) is arranged between active table top 920 Such as, oxide) terminate and be isolated (dielectric termination) area 910.As shown in Fig. 9, the active table top 920 of IGBT 900 can be such as Use conductive metal layer and/or DOPOS doped polycrystalline silicon connector (for example, connecting to be used for emitter terminal connection with gate terminal) To interconnect.In IGBT 900, active table top 920 can be active emitter table top.In some embodiments, using herein The method, other than wherein limiting the region of active table top 920, entire semiconductor substrate (for example, wafer) can quilt It aoxidizes to form the dielectric termination area 910 of IGBT 900.In such method, because dielectric termination area 910 can will be active Table top 920 is electrically isolated from one, so can be in the termination structure (such as N+ and/or P+ protection ring) or enhancing note of no any injection IGBT 900 is manufactured in the case where entering object.

Use method described herein, such as Figure 10 A- Figure 10 C, Figure 11 A- Figure 11 C, Figure 12 A- Figure 12 C and Figure 13 A- figure Those methods shown in 13J, can produce the embodiment of IGBT 900, wherein compared with current IGBT embodiment, (example Such as, by changing grid and trench emitter mesa dimensions) as the active emitter platform of the embodiment offer disclosed in these Carrier injection efficiency can be improved in the flexibility that face 920 is designed, and reduces Vce, sat (and saturation current), reduces input (rice Strangle) capacitor, reduce switching losses, and be also reduced by the emitter score of IGBT 900 to improve short-circuit ability to bear.It is logical Increase grid pitch (for example, average distance between active gate section) is crossed, can at least partly realize such IGBT performance The improvement of characteristic, therefore this can reduce the active equipment region around gate trench, reduce saturation current, improve carrier injection Efficiency, and reduce the Vce of associated IGBT (such as IGBT 900), sat.In some embodiments, grid pitch can 4 μm in the range of 50 μm.

Figure 10 A- Figure 10 C is to schematically show that the trench-gate IGBT (trench-gate of such as Fig. 9 can be included in IGBT 900) in IGBT 1000a, 1000b and 1000c active table top and dielectric (isolation) terminate cross-sectional view.? In certain embodiments, the semiconductor fabrication process being shown in Figure 13 A- Figure 13 J is can be used in IGBT 1000a, 1000b and 1000c It manufactures, this is hereinafter described.

Referring to Figure 10 A, a part for the IGBT 1000a that can be included in such as IGBT 900 is shown. IGBT 1000a is illustrated as realizing in semiconductor substrate 1001a and including dielectric termination 1010a (for example, limiting IGBT 1000a Inactive regions).In addition as shown in Figure 10 A is two active table top 1020a including p trap 1030a and source implant The part of 1040a.IGBT 1000a further includes conductive gate electrode 1050a, which passes through gate dielectric layer 1060a is isolated with active table top 1020a.In the example of Figure 10 A, active section (active emitter section) is along gate electrode 1050a is limited by active table top 1020a, and dielectric termination 1010a along gate electrode 1050a (with gate-dielectric 1050a Active section it is opposite) limit passive IGBT section.

Referring now to Figure 10 B, a part for the IGBT 1000b that can be included in such as IGBT 900 is shown.It is similar In the IGBT 1000b of the IGBT 1000a of Figure 10 A include semiconductor substrate 1001b；Dielectric termination 1010b is (for example, limit The inactive regions of IGBT 1000b)；Active table top 1020b, the active station face include p trap 1030b and source implant 1040b； And conductive gate electrode 1050b, the conductive gate electrode are isolated by gate dielectric layer 1060b with active table top 1020b. In the example of Figure 10 B, the active IGBT section of IGBT 1000b is limited along gate electrode 1050b by active table top 1020b, And dielectric termination 1010b is passive along gate electrode 1050b restriction (opposite with the active section of gate-dielectric 1050b) IGBT section.

IGBT 1000b and IGBT 1000a the difference is that conductive gate electrode 1050b in dielectric termination area Extend above 1010b, so that single gate electrode 1050b (rather than two individual gate electrode 1050a) are formed, wherein erecting Straight part 1054b extends along vertical axis V.Such method can be used for changing input (Miller) capacitor of IGBT 1000b.

Referring now to Figure 10 C, a part for the IGBT 1000c that can be included in such as IGBT 900 is shown.It is similar In the IGBT 1000c of IGBT 1000a and IGBT 1000b include semiconductor substrate 1001c；Dielectric termination 1010c (for example, Limit the inactive regions of IGBT 1000c)；Active table top 1020c, the active station face include p trap 1030c and source implant 1404c；And conductive gate electrode 1050c, the conductive gate electrode pass through gate dielectric layer 1060c and active table top 1020c isolation.In the example of Figure 10 C, the active IGBT section of IGBT 1000c is along gate electrode 1050c by active table top 1020b is limited, and dielectric termination 1010b is along gate electrode 1050c (opposite with the active section of gate-dielectric 1050c) Limit passive IGBT section.

IGBT 1000c and IGBT 1000b is the difference is that conductive gate electrode 1050c is somebody's turn to do including arranging 1052c It is listed in dielectric termination area 1010b and extends vertically along axis V (before the bottom surface of dielectric termination area 1010c eventually Only).As conductive gate electrode 1050b, such method can be used for changing input (Miller) capacitor of IGBT 1000c. For IGBT 1000c and IGBT 1000b the difference is that conductive gate electrode 1050c includes vertical portion 1054c, this is vertical Part extends to certain depth along axis V vertically, the depth of column 1052c of the depth less than IGBT 1000c, and also small In the depth of the vertical portion 1054b of IGBT 1000b.

Figure 11 A- Figure 11 C is to show the oxide termination that can be used to form trench-gate IGBT equipment and isolated area (such as The oxide termination area of the IGBT equipment of Fig. 9-Figure 10 C) various columns schematic diagram.According to particular implementation, it can be used and use The identical semiconductor etch processes of groove are formed in the active table top in associated IGBT equipment limits Figure 11 A- to be formed The groove of column in the dielectric termination area of Figure 11 C.In some embodiments, it can be used and be used to set in associated IGBT The different semiconductor etch processes of the semiconductor technology of formation groove limit Figure 11 A- Figure 11 C's to be formed in standby active table top The groove of column in dielectric termination area.(in active area and passive region in the embodiment using different groove etching process Or in dielectric termination area), different trench depths can be realized in active table top and dielectric (isolation) terminator, this is allowed Dielectric termination structure is deeper than active table top, this can further improve the isolation and termination between active table top.

The column being formed in the dielectric termination area (or other dielectric termination areas) of Figure 11 A- Figure 11 C can be oxidized, and be filled out Filled with dielectric substance, it is filled with polysilicon, and/or for limiting the air gap in dielectric termination area.As described herein, Such dielectric termination area can for IGBT active emitter table top (the active table top 920 of such as IGBT 900) provide electricity every It is terminated from electricity.

Figure 11 A shows the dielectric isolation 1110a including circular semiconductor column 1112a.In the exemplary embodiment, Each of column 1112a can have about 0.6 μm of width, be spaced apart about 0.4 μm, and with about 5 μm of height (for example, limit The depth of the groove of fixed column 1112a can be about 5 μm).Figure 11 B shows the dielectric isolation including snakelike semiconductor column 1112b 1110b, and Figure 11 C shows the dielectric isolation 1110c including Y shape semiconductor column 1112c.In the exemplary embodiment, Each of column 1112b and 1112c can have about 0.6 μm of wide overall width, be spaced apart about 0.8 μm, and because they are being tied It is more firm than circular columns 1112a on structure, so can have 16 μm of height, or higher (for example, limiting column 1112b and 1112c The depth of groove can be about 16 μm, or it is deeper).The configuration of other columns is also possible, such as gable column, I shape pillar etc..

In the method for Figure 11 A- Figure 11 C, after forming column, column can be oxidized, this will increase their volume, be caused Their external dimensions increases due to oxidation.However, due to the spacing (spacing depends on particular implementation) between column, The oxidation of column not will lead to the significant stress or bending that are used to form the semiconductor crystal wafer of associated IGBT.As described herein, Due to the close clearance between column, the oxide pillars in dielectric termination area can be further processed with polysilicon filling gap and/ Or form the air gap with the dielectric enclosed of relatively small deposition thickness.

Figure 12 A- Figure 12 C is the schematic diagram for schematically showing the part of IGBT equipment, which can be included in IGBT In (IGBT 900 of such as Fig. 9).In each of Figure 12 A- Figure 12 C, active table top, IGBT gate configuration and electricity are shown The various arrangements of medium terminator.

Referring to Figure 12 A, one of the IGBT equipment 1200a in the IGBT 900 that can be included in such as Fig. 9 is shown Point.IGBT 1200a includes dielectric termination area 1210a, active emitter table top 1220a, and is arranged in active emitter platform Source implant 1240a in the 1220a of face.IGBT equipment 1200a further includes pattern conductive gate electrode 1250b, the pattern Changing conductive gate electrode may be connected to the trench gate electrode of neighbouring active table top 1220a (for example, being shown in the conduction electricity of Figure 10 A Pole 1050a).As illustrated in fig. 12, gate electrode 1250a by gate-dielectric 1260a and active emitter table top 1220a every From.

Referring now to Figure 12 B, one of the IGBT equipment 1200b in the IGBT 900 that can be included in such as Fig. 9 is shown Part.IGBT 1200b includes dielectric termination area 1210b, active emitter table top 1220b, and is arranged in active emitter Source implant 1240b in table top 1220b.IGBT equipment 1200b further includes blanket conductive gate electrode 1250b, configuration It is different from the patterning gate electrode 1250a of Figure 12 A.Similar to patterning gate electrode 1250a, blanket gate electrode 1250b It may be connected to the trench gate electrode (for example, the conductive electrode 1050a for being shown in Figure 10 A) of neighbouring active table top 1220b.Such as figure Shown in 12B, blanket gate electrode 1250b is isolated by gate-dielectric 1270a with active emitter table top 1220b.

Referring now to Figure 12 C, one of the IGBT equipment 1200c in the IGBT 900 that can be included in such as Fig. 9 is shown Part.IGBT 1200b includes dielectric termination area 1210c, active emitter table top 1220c, and is arranged in active emitter Source implant 1240c in table top 1220c.IGBT equipment 1200b further includes pattern conductive gate electrode 1250, configuration It is different from the patterning gate electrode 1250a of Figure 12 A.Similar to patterning gate electrode 1250a and blanket gate electrode 1250b, patterning gate electrode 1250c may be connected to neighbouring active emitter table top 1220c trench gate electrode (for example, It is shown in the conductive electrode 1050a of Figure 10 A).As indicated in fig. 12 c, patterning gate electrode 1250c passes through gate-dielectric 1260a Active emitter table top 1220c isolation corresponding to its.

Figure 13 A- Figure 13 J is shown for manufacturing groove-the signal of the semiconductor fabrication process of grid IGBT equipment 1300 Scheme (cross section and plan view).In some embodiments, the semiconductor technology being shown in Figure 13 A- Figure 13 J can be used for manufacturing tool There are the configuration and other IBGT embodiments of IGBT equipment of such as Fig. 9, Figure 10 A- Figure 10 C and Figure 12 A- Figure 12 C etc The IGBT of (all those embodiments as disclosed herein).

As the semiconductor fabrication process of Fig. 4 A- Fig. 4 G and Fig. 8 A- Fig. 8 H, for succinct and clear purpose, figure Each processing step of process flow shown in 13A- Figure 13 J is not illustrated or is retouched by details in the following discussion It states.Therefore, the multiple semiconductor processing operations of the attached figure representation of each of Figure 13 A- Figure 13 J.It is performed (all to manufacture IGBT equipment Such as IGBT equipment 1300) particular semiconductor process operation (and associated processing parameter) particular implementation side will be depended on Formula, the desirable operational parameters (for example, time, breakdown voltage, Vce, sat, input capacitance etc. are born in short circuit) of such as IGBT equipment.

In Figure 13 A- Figure 13 J, dielectric termination area 1310 and active emitter platform are shown in each viewgraph of cross-section Face area 1320.In some embodiments, the viewgraph of cross-section of Figure 13 A- Figure 13 I can correspond in Figure 12 B along the view of line 13a Figure, but as an example, at least some cases, the quantity of the groove and table top that are shown in Figure 13 A- Figure 13 J is different from showing In Figure 12 B along the groove of line 13a and the quantity of table top.In addition, as an example, the viewgraph of cross-section of Figure 13 J can correspond to Along the view of line 13b in Figure 12 C.

Referring to Figure 13 A, semiconductor (for example, N-shaped) substrate 1301 can be used for manufacturing IGBT equipment 1300.As described above, IGBT equipment 1300 may include oxide termination area 1310 and active emitter table section 1320, they show in figure 13a.Such as Shown in Figure 13 A, JFET (N-shaped) layer 1312 can be formed, wherein JFET layer 1312 there can be the n-type doping higher than substrate 1301 dense Degree.In addition as shown in FIG. 13A, P+ ring 1304 (for example, boron doped) can be injected.P+ ring 1304 can improve closing for IGBT 1300 It locks voltage (breakdown voltage).P+ ring 1304 may additionally include in the active section of other IGBT as described herein, such as be shown in example IGBT such as the IGBT 200 in Fig. 2A and Fig. 2 B, or including oxide filling table top section is (shown in such as Fig. 5-Fig. 7 B Those IGBT).In certain embodiments (for example, having dielectric more deeper than groove in active emitter table top 1320 whole The only embodiment in area or broader dielectric termination area) in, P+ ring 1304 can be eliminated, because deeper and/or wider Dielectric termination can provide enough voltage blockings.

Referring to Figure 13 B, deposition (for example, TEOS is deposited), photoetching and etching operation can be performed so that hard mask layer pattern To etch groove 1315 (for example, using anisotropy trench etch), wherein forming groove 1315 (for example, with about 5 μm of depth Degree TD2) column 1316 (column such as with configuration shown in Figure 11 A) can be also limited in dielectric termination area 1310.

Referring now to Figure 13 C, it can grow and remove sacrifical oxide (SacOX), this can help to remove by the ditch of Figure 13 B Any damage caused by channel erosion carving technology to semiconductor substrate 1301 (and JFET layer 1312).It, can after removing SacOX layers Gate oxidation process is executed, this can form gate oxide on the side wall of groove 1315 and the upper surface of at least column 1316 1360.In some embodiments, gate oxidation process is than more completely oxide pillars 1316 shown in Figure 13 C.For example, grid Oxidation technology can more completely aoxidize the semiconductor material of substrate 1301, JFET layer 1312 and include the P+ ring in column 1316 1304.The amount of oxidation of column 1316 will be at least dependent on the specific shape of column 1316 and size and performed gate oxidation work The parameter (time, temperature etc.) of skill.As shown in fig. 13 c, the semiconductor in the illustrative embodiments, in oxide pillars 1316 Material can have width W1, and wherein W1 can be about 0.0 μm to 0.5 μm.Oxide pillars 1316 can have width W2, which can be about 0.5 μm to 1.2 μm, and the spacing between oxide pillars can be distance W3, which can be about 0.0 μm to 1.0 μm.

As illustrated in figure 13d, conductive electrode 1350 may be formed at (it on the interior gate oxide 1360 for being lining in groove 1315 It is interior etc.).The formation (and formation of the conductive electrode of other embodiments as described herein) of conductive electrode 1350 may include back Etching technique and/or CMP process.As shown in figure 13e, mask (such as nitride mask) 1355 may be formed at active 1320 top (for example, using lithography operations) of emitter mesa.Then mask can be used that conductive electrode 1350 (is used polycrystalline Silicon etching) it removes from dielectric termination area 1310 conductive (for example, grid) electrode 1350 is retained in active emitter table top In 1320.

Column oxidation technology can be formed more completely (for example, completely or almost for the embodiment referring to Figure 13 F Completely) the semiconductor material in oxide pillars 1316.1304 infusion of P+ ring can also be expanded to oxide end by column oxidation technology Only on the bottom in area 1320, as shown in Figure 13 F.

As shown in Figure 13 G, dielectric deposition (for example, CVD oxide deposits) and dielectric eatch-back can be performed with further Groove 1315 between oxide pillars is lined with dielectric substance 1317.As shown in Figure 13 G, air gap 1319 can be retained in dielectric material Material 1317 in, wherein air gap 1319 can reduce can due to subsequent high temperature processing and occur stress or curved amount.

As shown in Figure 13 H, dopant injection and thermal drivers operation can be performed to be formed in active emitter table top 1320 P trap 1330 and n-type source infusion 1340.In the illustrative embodiments, source implantation process can be self aligned (example Such as, pass through the dielectric termination area of blocking source implant).

Referring to Figure 13 I, dielectric cap can be formed with the air gap 1319 in encapsulated dielectric terminator 1310.Dielectric cap can Including boron phosphorus silicate glass (BPSG) layer 1318 (and/or other dielectric substances), which can be refluxed so that IGBT 1300 Top surface plane.Dielectric cap may also include nitride-barrier 1321 and TEOS layer 1323.

As shown in Figure 13 J (it corresponds to the cross section along the line 13b in Figure 12 C), each of IGBT 1300 can be formed The metal interconnection of other features of kind element and IGBT 1300.These features may include for example p-type enhancing infusion 1362, Source contact 1364, metalization layer 1366 and 1376 and passivation layer 1368.It can also be in active emitter table top 1320 Touching (although not specifically illustrating in Figure 13 J) is conductively connected in conductive gate electrode 1350.According to the embodiment, can be formed attached Add one or more of feature and/or the shown feature that IGBT 1300 can be eliminated.

Figure 14 is the schematic diagram for schematically showing a part of trench-gate IGBT 1400, trench-gate IGBT The techniques described herein can be used, such as by manufacturing in conjunction with various operations as described herein.As shown in figure 14, IGBT 1400 include dielectric (isolation) terminator 1410, is isolated and terminates two active IGBT sections.Dielectric termination area can make With forming (manufacture etc.) above in relation to method described in Figure 11 A- Figure 11 C and Figure 13 A- Figure 13 J, and IGBT's 1400 has Source IGBT section (for example, one above dielectric termination part 1410 and one below dielectric termination part 1410) It can be used and form (manufacture) such as the method for Fig. 4 A- Fig. 4 G.

As shown in figure 14, the active IGBT section of IGBT equipment 1400 respectively includes active emitter mesa 1430, this has Source emitter mesa has the source implant 1440 being disposed therein.Each of active IGBT section further includes conductive trench Electrode 1450 (for example, trench gate electrode in the example).Active IGBT section further includes gate-dielectric 1460, the grid Pole dielectric interior can be lining in groove, and conductive gate electrode 1450 is set in the groove.

Various semiconductor processes and/or encapsulation technology can be used to realize for various devices as described herein and technology.It is some Various types of semiconductor processing techniques associated with semiconductor substrate can be used to realize for embodiment, the semiconductor substrate Including but not limited to such as silicon (Si), GaAs (GaAs), silicon carbide (SiC).

It is also understood that when element such as layer, region or substrate be mentioned on the other element, be connected to another yuan Part, when being electrically connected to another element, be couple to another element or being conductively coupled to another element, which can directly exist It on another element, connects another element or is couple to another element, or one or more intermediary elements may be present.Phase Instead, when element is mentioned directly on another element or layer, is directly connected to another element or layer or is directly coupled to another When one element or layer, intermediary element or layer is not present.

It is upper although may not directly be existed using term in the whole text in entire detailed description ..., be directly connected to ... or straight Connect and be couple to ..., but be illustrated as directly on element, the element that is directly connected to or directly couples can be referred in a manner of such.This The claim of application can be revised to describe the exemplary relation for describing or being shown in the accompanying drawings in the description.

It is as used in this specification, unless based on context it is manifestly intended that specific condition, otherwise singular It may include plural form.Other than orientation shown in the drawings, spatially relative term (for example... top ... above, ... on ... lower section ... below ... it is following ... under etc.) be intended to cover device in use or operation Different orientation.In some embodiments, on existing ... and ... under relative terms can respectively include vertically existing ... it Under existing above and vertically ....In some embodiments, it may include laterally adjacent to (or laterally adjacent), vertical neighbour that term is neighbouring It is closely (or vertical adjacent) or horizontal neighbouring (or horizontally adjacent), it indicates that intermediary element may be disposed at wherein adjacent and is retouched It states between neighbouring element.

Although certain features of described embodiment are illustrated as described herein, art technology Personnel will expect many modifications, alternative form, version and equivalent form now.It will thus be appreciated that appended right It is required that being intended to cover all such modifications fallen within the scope of the embodiments and version.It should be appreciated that these are repaired Reshaping formula and version are only presented in an illustrative manner, rather than are limited, and can carry out in form and details each Kind changes.Other than mutually exclusive combination, any part of device as described herein and/or method can in any combination into Row combination.The embodiment described herein may include the various of the functions of described different embodiments, component and/or feature Combination and/or sub-portfolio.

Claims (12)

1. a kind of insulated gate bipolar transistor IGBT equipment, comprising:

Active area；

Passive region；

Groove, the groove extend along the longitudinal axis in the active area；

First table top, first table top limit the first side wall of the groove and parallel with the groove；With

Second table top, second table top limit the second sidewall of the groove and parallel with the groove,

Wherein, at least part of first table top includes the active section of the IGBT equipment, and

At least part of second table top includes the passive section of the IGBT equipment.

2. IGBT equipment according to claim 1, wherein the active area section is the first active section, the passive section It is the first passive section, described at least part of first table top includes the first part of first table top, and institute The described at least part for stating the second table top includes the first part of second table top, the IGBT equipment further include:

Second active section, the second active section are included in the second part of second table top；And

Second passive section, the second passive section are included in the second part of first table top.

3. IGBT equipment according to claim 1, in which:

First table top is included in the active table top in the active area, and second table top is included in institute State the passive table top in passive region；And

The passive region is the terminator of the IGBT equipment.

4. a kind of insulated gate bipolar transistor IGBT equipment, comprising:

Active area；

Passive region；

Groove, the groove extend along the longitudinal axis in the active area；

First table top, first table top limit the first side wall of the groove and parallel with the groove；

Second table top, second table top limit the second sidewall of the groove and parallel with the groove；

Described first active section of the first active section of the IGBT equipment, the IGBT equipment is included in described first In the first part of table top；

Described first passive section of the first passive section of the IGBT equipment, the IGBT equipment is included in described first In the second part of table top；

Described second active section of the second active section of the IGBT equipment, the IGBT equipment is included in described second In the first part of table top；And

Described second passive section of the second passive section of the IGBT equipment, the IGBT equipment is included in described second In the second part of table top.

5. IGBT equipment according to claim 4, in which:

The passive region includes the terminator of the IGBT equipment, and the terminator is at least partly around the active area；

First table top is non-uniform along the longitudinal axis；

Second table top is non-uniform along the longitudinal axis；

Described first active section of the IGBT equipment and the second active section include source implant；And

Described first passive section of the IGBT equipment and the second passive section do not include the source implant.

6. IGBT equipment according to claim 4, in which:

The first part of first table top includes the semiconductor material with the first width, along first table top The dielectric of first thickness is provided on the first side wall of the groove of the first part；And

The second part of first table top includes the semiconductor material with the second width, along first table top The dielectric of second thickness is provided on the first side wall of the groove of the second part,

First width is greater than second width, and

The first thickness is less than the second thickness.

7. IGBT equipment according to claim 4, in which:

Described first active section of the IGBT equipment is the first emitter segment of the IGBT equipment；

Described second active section of the IGBT equipment is the second emitter segment of the IGBT equipment；

The first part of first table top is the semiconductor portions of first table top；And

The second part of first table top is the dielectric portion of first table top.

8. IGBT equipment according to claim 7, wherein the dielectric portion in the First face is described first The dielectric filler part of table top.

9. a kind of insulated gate bipolar transistor IGBT equipment, comprising:

Active area；

Passive region；

Groove, the groove extend along the longitudinal axis in the active area；

First uneven table top, the first uneven table top limit the first side wall of the groove and put down with the groove Row；And

Second uneven table top, the second uneven table top limit the second sidewall of the groove and put down with the groove Row.

10. IGBT equipment according to claim 9, in which:

The first part of the first uneven table top includes the first active section of the IGBT equipment；

The second part of the first uneven table top includes the first passive section of the IGBT equipment；

The first part of the second uneven table top includes the second active section of the IGBT equipment；And

The second part of the second uneven table top includes the second passive section of the IGBT equipment.

11. IGBT equipment according to claim 10, in which:

Described first active section of the IGBT equipment is the first emitter segment of the IGBT equipment, and including source electrode Infusion；

Described second active section of the IGBT equipment is the second emitter segment of the IGBT equipment, and including described Source implant；And

Described first passive section of the IGBT equipment and the described second passive section of the IGBT equipment do not include institute State source implant.

12. IGBT equipment according to claim 10, in which:

The first part of the first uneven table top includes the semiconductor material with the first width, along the table top The first part the groove the first side wall on be provided with the dielectric of first thickness；

The second part of the first uneven table top includes the semiconductor material with the second width, along the table top The second part the groove the first side wall on be provided with the dielectric of second thickness, first width is big In second width, and the first thickness is less than the second thickness；

The first part of first table top is the semiconductor portions of first table top；

The second part of first table top is the dielectric portion of first table top；And

The dielectric portion of first table top is the dielectric filler part of first table top.