CN208444843U - Field effect transistor and storage memory - Google Patents
Field effect transistor and storage memory Download PDFInfo
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- CN208444843U CN208444843U CN201820870458.6U CN201820870458U CN208444843U CN 208444843 U CN208444843 U CN 208444843U CN 201820870458 U CN201820870458 U CN 201820870458U CN 208444843 U CN208444843 U CN 208444843U
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Abstract
The utility model discloses a kind of field effect transistor and storage memories.The field effect transistor includes source electrode, drain electrode, channel region, first grid and an at least second grid, it is connected between the source electrode and drain electrode through channel region, the first grid setting is over the channel region, and dielectric layer is provided between the first grid and channel region, at least one described second grid and the channel region cooperatively form the knot to store charge.Compared with the prior art, field-effect transistor structure provided by the utility model is more simple, occupied space is less, and manufacturing process steps simplify, it can be compatible with existing transistor fabrication process, it is low in cost, and single device memory may be implemented, therefore have wide practical use in fields such as computers.
Description
Technical field
The utility model relates to a kind of field effect transistor, especially it is a kind of have structure improved field effect transistor and
Its application in preparation storage memory, belongs to technical field of semiconductors.
Background technique
Currently, in a variety of devices with data-handling capacity, such as in personal computer, smart phone equipment, partly lead
Body memory element is widely used.One of important data storage elements are DRAM (Dynamic RandomAccess
Memory), i.e. dynamic random access memory.Refering to Figure 1, the basic unit of existing DRAM generally includes an effect
Answer transistor 101 ' and a capacitor 102 '.In order to keep data, DRAM is stored using capacitor, but capacitor inevitably exists
Leaky, if charge deficiency will lead to corrupt data, therefore capacitor periodically must be refreshed (precharge).And electricity
The charge and discharge of appearance need a process, and refreshing frequency can not infinitely promote (frequency hinders), this results in the frequency of DRAM to be easy to
Reach the upper limit, even if there is the support of advanced technologies also to produce little effect.
Summary of the invention
The main purpose of the utility model is to provide a kind of field effect transistor and storage memories, to overcome existing skill
Deficiency in art.For realization aforementioned invention purpose, the technical solution adopted in the utility model includes:
The utility model embodiment provides a kind of field effect transistor, including source electrode, drain electrode, channel region and the first grid
Pole connects between the source electrode and drain electrode through channel region, first grid setting over the channel region, and the first grid with
Dielectric layer is provided between channel region；Also, the field effect transistor further includes at least one second grid, and described at least one
A second grid and the channel region cooperatively form the knot to store charge.
Wherein, it is designed by using aforementioned structure, such as the structure by first grid setting over the channel region, this can be made
The transistor of utility model embodiment is easier to make, and controllability is more preferable, and has preferably with existing transistor fabrication process
Compatibility.
Further, the knot can select the knot that can be used to store charge known in the art, such as hetero-junctions, homogeneity
Knot, semiconductor/insulating layer knot, PN junction, PIN junction etc., and it is without being limited thereto.
Further, in some embodiments, the field effect transistor includes conduction region, and the conduction region is as institute
It states second grid and the channel region cooperatively forms the knot.
Wherein, the material of the conduction region is to be different from the material of the channel region.
Further, in some embodiments, the second grid can the direct channel region contacts.
Further, in some embodiments, it also can be set between the second grid and the channel region absolutely
Edge layer.
Further, in some embodiments, buffer layer is provided between the second grid and the channel region
(buffer layer)。
Further, in some embodiments, the field effect transistor further includes cooperating with the second grid
Semiconductor region.
Wherein, the material of the conduction region is to be different from the material of the channel region.
Further, in some embodiments, insulating layer is provided between the semiconductor region and second grid.
Further, in some embodiments, the second gate can be multiple.
Further, in some embodiments, the second grid either one or two of is set to around the semiconductor region
Or the region between the semiconductor region and channel region is deviateed in multiple specified regions, any specified region.For example, if false
If the semiconductor region is cuboid, and defines it with upper surface, lower end surface and four sides, and one side and channel region
It is oppositely arranged, then the second grid can be set to appointing in the upper surface, lower end surface and other three sides of the second semiconductor
Near one or more.In fact, the relative position of aforementioned second gate and the second semiconductor, can according to actual needs and
Fixed, this is that those skilled in the art can know according to this specification and industry common sense, is no longer explained in detail herein.
Further, in some embodiments, the second grid either one or two of be set to around the channel region or
Multiple specified regions, region where any one in any specified region and the source region, drain region and first grid without
It contacts and is not also overlapped.For example, if assuming, the channel region is cuboid, and defines it with upper surface, lower end surface and four
Side, and first grid is located on the upper surface of channel region, and source region, drain region are respectively arranged at the two sides of channel region, then it is described
Second grid can be set near any one of other two side, lower end surface of channel region or more persons.Certainly, some
In the case of, second grid also can be set on the upper surface of channel region and be arranged with first grid interval.To sum up, aforementioned
Setting position of the second gate extremely in the field effect transistor, can be with depend on the actual needs, this is art technology
Personnel can know according to this specification and industry common sense, no longer be explained in detail herein.
In some embodiments, the material in aforementioned trenches area includes graphene, carbon nanotube or indium tin oxide,
Indium potassium zinc oxygen, tin oxide, titanium dioxide, gallium oxide, ITO, In2O3, zinc oxide, p-type Cu2O、SnO、NiO、CuO、V2O3、WO3、
Molybdenum oxide, Co3O4Material layer, nano wire, the two-dimensional material of equal formation, and it is without being limited thereto, such as can also be other semiconductors
Material.
Further, the field effect transistor includes semiconductor layer, distribution active area in the semiconductor layer, drain region and
Channel region, the source region, drain region are connected with source electrode, drain electrode respectively.
In some embodiments, the semiconductor layer can be the first doping type, and the source region and drain region can be with
It is the second doping type.Wherein, first doping type can be p-type or N-type, and the second doping type is different from the
The N-type or p-type of one doping type.
For example, the field effect transistor includes p type semiconductor layer, described in some more specific embodiments
Source region, drain region be respectively be set in the p type semiconductor layer N-type source region, N-type drain region, the channel region be distributed in source region,
Between drain region.In other words, it can also be expected that the field effect transistor is to be based in some more specifically embodiments
The basic structure of NMOS pipe and construct.Wherein, the p type semiconductor layer can be using semiconductor material known to industry, example
Such as P type silicon.And the N-type source region and N-type drain region can be through photoetching, diffusion technique etc. in p type semiconductor layer
Corresponding region is doped and is formed, these techniques are known to industry, and details are not described herein again.
In another example the field effect transistor includes n type semiconductor layer in some more specific embodiments, institute
Source region, the p-type source region that drain region is respectively set in the n type semiconductor layer, p-type drain region are stated, the channel region is distributed in source
Between area, drain region.In other words, it can also be expected that the field effect transistor is base in some more specifically embodiments
In PMOS pipe basic structure and construct.Wherein, the n type semiconductor layer can use semiconductor material known to industry,
Such as N-type silicon semiconductor layer.And the p-type source region and p-type drain region can be through photoetching, diffusion technique etc. to N-type semiconductor
Corresponding region in layer is doped and is formed, these techniques are known to industry, and details are not described herein again.
In other embodiments, being also possible to source region, drain region and the conducting channel being distributed in channel region is all N
Type etc., that is, source region, drain region directly pass through the conducting channel and connect.
In some embodiments, the field effect transistor is fin formula field effect transistor, the fin of the transistor
The second grid described at least one is distributed on channel region.The second grid is centered around fin channel area two sides and top,
And the knot to store charge is formed with fin channel area.
Further, the field effect transistor obviously further includes source electrode, drain electrode etc., and the source electrode, drain electrode, first
Conductor characteristics material known to industry can be used in grid, second grid etc., for example, metal, alloy, conducting polymer, conduction
Carbon nanotube, indium tin oxide (ITO), indium gallium zinc oxide (IGZO) etc., wherein metal is aluminium, copper, tungsten, molybdenum, gold or caesium
Deng；Alloy is and without being limited thereto at least containing two kinds in aluminium, copper, tungsten, molybdenum, gold, caesium.In addition, in some embodiments, the
Two grids are also possible to the formation of the materials such as graphene, carbon nanotube.It is attached and, second grid can with source, drain electrode be formed simultaneously.
Wherein, the channel region can be a variety of suitable shapes, such as strip.And for the size of the channel region,
Depending on it can be according to the demand of practical application.For example, in some case study on implementation, the length of the channel region can be
0.001~5000 μm, preferably 0.01~100 μm, more preferably 0.1~10 μm, width are 0.0001~1000 μm, preferably
0.01~100 μm, more preferably 0.01~10 μm, the electrical thickness of channel region are 0.001~8000nm, preferably 0.01~
200nm, more preferably 1~50nm.
Wherein, the physical thickness of the insulating layer can be 0.001~1000 μm, preferably 1~200 μm, certainly may be used
Other sizes are adjusted to the demand according to practical application.
Further, the material of the insulating layer can be silica (such as porous silica, thermally grown titanium dioxide
Silicon), benzocyclobutene, polyester, acrylic resin, aluminium oxide, the high-K gate dielectric materials such as silicon oxynitride, can be and pass through object
Reason, chemical vapour deposition technique etc. are formed on aforementioned p type semiconductor layer or n type semiconductor layer, be also possible to by dielectric film from
The external world is transferred on aforementioned p type semiconductor layer or n type semiconductor layer and is formed.
Further, the material of the buffer layer can be any suitable material known in the art, such as can be selected from III
The graphenes such as~V semiconducting compound, carbon nanotube or indium tin oxide, indium potassium zinc oxygen, tin oxide, titanium dioxide, oxygen
Change gallium, ITO, In2O3, material layer, nano wire, the two-dimensional material of formation such as zinc oxide etc., alternatively, p-type Cu2O、SnO、NiO、
CuO、 V2O3、WO3, molybdenum oxide, Co3O4Material layer, nano wire, the two-dimensional material of equal formation, and it is without being limited thereto.
The utility model embodiment additionally provides a kind of storage memory comprising the field effect transistor.
The utility model embodiment additionally provides the purposes of the field effect transistor or the storage memory.
For example, the utility model embodiment additionally provides a kind of device comprising the field effect transistor or institute
The storage memory stated.Typical such device can be computer, smart phone, tablet computer, industrial control equipment and
Other electronic equipments, optoelectronic device, electromechanical equipment etc..
Compared with the prior art, field-effect transistor structure provided by the utility model is more simple, and occupied space is less, and
And single device memory may be implemented, while it also can avoid when application is the basic unit of dynamic random access memory
Because of the brings a series of problems such as capacity fall off in existing DRAM, refreshing frequency is also obviously improved, and ibid it makes work
Skill is simple, can be compatible with existing transistor fabrication process, low in cost, therefore before the fields such as computer are widely used
Scape.
Detailed description of the invention
Fig. 1 is a kind of electrical block diagram of the basic unit of existing DRAM.
Fig. 2 is a kind of the schematic diagram of the section structure of field effect transistor in the utility model embodiment 1.
Fig. 3 is a kind of top view of field effect transistor in the utility model embodiment 1.
Fig. 4 is a kind of top view of field effect transistor in the utility model embodiment 2.
Fig. 5 is a kind of the schematic diagram of the section structure of field effect transistor in the utility model embodiment 3.
Fig. 6 is a kind of the schematic diagram of the section structure of field effect transistor in the utility model embodiment 4.
Fig. 7 is a kind of top view of field effect transistor in the utility model embodiment 5.
Fig. 8 is a kind of top view of field effect transistor in the utility model embodiment 6.
Fig. 9 is a kind of structural schematic diagram of field effect transistor in the utility model embodiment 7.
Figure 10 is a kind of structural schematic diagram of field effect transistor in the utility model embodiment 8.
Specific embodiment
In order to illustrate the embodiment of the utility model or the technical proposal in the existing technology more clearly, below will be to embodiment
Or attached drawing needed to be used in the description of the prior art is briefly described, it should be apparent that, the accompanying drawings in the following description is only
It is some embodiments recorded in the utility model, for those of ordinary skill in the art, is not making the creative labor
Under the premise of, it is also possible to obtain other drawings based on these drawings.
Postscript, it should be noted that in the present specification, relational terms such as first and second and the like are used merely to
It distinguishes one entity or operation from another entity or operation, without necessarily requiring or implying these entities or behaviour
There are any actual relationship or orders between work.Moreover, the terms "include", "comprise" or its any other variant
It is intended to non-exclusive inclusion, so that including that the process, method, article or equipment of a series of elements not only includes
Those elements, but also including other elements that are not explicitly listed, or further include for this process, method, article or
The intrinsic element of person's equipment.In the absence of more restrictions, the element limited by sentence "including a ...", not
There is also other identical elements in the process, method, article or apparatus that includes the element for exclusion.
Embodiment 1: please referring to shown in Fig. 2, and one of the present embodiment field effect transistor can be based on NMOS tube
Architecture building, including semiconductor layer 10, the interior distribution active area 11 of the semiconductor layer, drain region 12 and channel region 17, institute
It states and is connected between source region and drain region through channel region 17, be provided with first grid 15 on the first surface 101 of the semiconductor layer
(gate), dielectric layer 16 can be set between the first grid (also can be considered as top-gated, top gate) and channel region.
Opposite facing with the first surface 101 is second surface 102.
Further, it please refers to shown in Fig. 3, in the field effect transistor of the embodiment, in the side of channel region 17 or two
Side is nearby additionally provided with second grid 18 (control gate, i.e. control gate), and makes second grid 18 and the formation of channel region 17
To store the knot of charge.The knot can be selected from but not limited to schottky junction, hetero-junctions, homojunction, PN junction, PIN junction, half
Conductor/insulation layer knot etc..
Further, the also settable buffer layer (not shown) between the second grid 18 and channel region 17,
Its material can be selected from any suitable material known in the art.
Further, in the field effect transistor, aforementioned semiconductor layer can be selected from P-type wafer, especially low-doped
The P type silicon wafer of concentration, and source region therein, drain region can be by being arranged patterned mask in the P-type wafer, and to
Source, leakage corresponding region carry out ion implanting processing etc. and are formed.
Further, in the field effect transistor, aforementioned dielectric layer can be the high K such as silicon nitride, aluminium nitride and be situated between
Material composition.For example, aforementioned dielectric layer can be formed directly into semiconductor layer by modes such as MOCVD, PECVD
First surface.
Further, in the field effect transistor, window can be opened up in the source of dielectric layer, drain region, in favor of system
Make source electrode 13 (source), 14 (drain) of drain electrode, and keeps source electrode, drain electrode in electrical contact with aforementioned source region, drain region respectively, such as
Form Ohmic contact.
Further, in the field effect transistor, first grid can be in directly production is formed on dielectric layer.
Further, aforementioned source electrode, drain electrode, first grid, second grid etc. can be the gold such as aluminium, copper, tungsten, molybdenum, gold, caesium
Other conductor materials category material or above-mentioned.If metal material, then it can be formed by techniques such as sputterings.
The manufacture craft of the present embodiment field effect transistor can be compatible with existing transistor fabrication process.
It will be apparent that the basic unit compared with existing DRAM, the area of the field effect transistor of the present embodiment significantly reduce (from
The cross-sectional area of+1 capacitor of 1 transistor of existing DRAM basic unit, i.e. about two transistors, becomes 1 transistor
Cross-sectional area), and manufacturing process steps are simplified, it can effectively save cost.
Further, which at work, can be aforementioned with being formed between channel and control gate
" knot " forms charge storage layer, and can realize erasable and control by applying voltage on the control gate.
Embodiment 2: please referring to shown in Fig. 4, and the structure of the field effect transistor of the embodiment is substantially the same manner as Example 1,
Difference place is: semiconductor layer can be using N-type silicon substrate etc.；And it is also set up between second grid 18 and channel region 17
There is an insulating layer 19.The insulating layer can be the materials such as silicon nitride, aluminium nitride composition.Likewise, in some embodiment party
In case, a buffer layer (not shown) can also be set between the second grid 18 and channel region 17.The present embodiment field
The manufacture craft of effect transistor can be compatible with existing transistor fabrication process.
Embodiment 3: please referring to shown in Fig. 5, and one of the present embodiment field effect transistor can be based on PMOS tube
Architecture building, including semiconductor layer 20, the n type semiconductor layer is interior to form active area 21 and drain region 22, the source region
It is connect between drain region through channel region 27, first grid 25 (gate), institute is provided on the first surface 201 of the semiconductor layer
It states and dielectric layer 26 can be set between first grid and channel region.Opposite facing with the first surface 201 is second surface
202.Further, it please refers to shown in Fig. 4, it is also settable at 17 bottom surface of channel region in the field effect transistor of the embodiment
There is a second grid 28, and second grid 28 and channel region 27 is made to form the knot to store charge.
Further, in the field effect transistor, aforementioned semiconductor layer can be obtained by commercially available approach, and therein
Source region, drain region can be by the way that patterned mask is arranged on the semiconductor layer, and carry out ion note to source, leakage corresponding region
Enter processing etc. to be formed.
Further, in the field effect transistor, aforementioned dielectric layer can be the high K such as silicon nitride, aluminium nitride and be situated between
Material composition.For example, aforementioned dielectric layer can be formed directly into semiconductor layer by modes such as MOCVD, PECVD
First surface.
Further, in the field effect transistor, window can be opened up in the source of dielectric layer, drain region, in favor of system
Make source electrode 23 (source), 24 (drain) of drain electrode, and keeps source electrode, drain electrode in electrical contact with aforementioned source region, drain region respectively, such as
Form Ohmic contact.
Further, in the field effect transistor, first grid can be in directly production is formed on dielectric layer.
Further, aforementioned source electrode, drain electrode, first grid, second grid etc. can be the gold such as aluminium, copper, tungsten, molybdenum, gold, caesium
Other conductor materials category material or above-mentioned.If metal material, then it can be formed by techniques such as sputterings.
The manufacture craft of the present embodiment field effect transistor can be compatible with existing transistor fabrication process.
Embodiment 4: please referring to shown in Fig. 6, and one of the present embodiment field effect transistor is substantially the same manner as Example 3,
Difference place is: it is additionally provided with semiconductor area 30 between second grid 28 and channel region, and second grid 28 and semiconductor
An insulating layer 29 is additionally provided between area 30.The semiconductor region 30 can be different from the semiconductor material of commonly seeing of channel region by material
Material composition.The insulating layer can be the materials such as silicon nitride, aluminium nitride composition.The production of the present embodiment field effect transistor
Technique can be compatible with existing transistor fabrication process.
Embodiment 5: please referring to shown in Fig. 7, and one of the present embodiment field effect transistor is substantially the same manner as Example 4,
Difference place is: channel region side is provided with semiconductor area 30, and a second gate is provided at the upper end of the semiconductor region 30
Pole 28, and an insulating layer (not shown) is additionally provided between the second grid 28 and semiconductor region 30.The present embodiment field effect
Answer the manufacture craft of transistor can be compatible with existing transistor fabrication process.
Embodiment 6: please referring to shown in Fig. 8, and one of the present embodiment field effect transistor is substantially the same manner as Example 1,
Difference place is: the second grid 18 is arranged at the side of 17 top of channel region, and is formed with channel region 17 to store
The knot of charge.The manufacture craft of the present embodiment field effect transistor can be compatible with existing transistor fabrication process.
Embodiment 7: it please refers to Fig. 9 and shows one of embodiment field effect transistor, a lining can be formed in
On bottom 31, including source electrode 32, drain electrode 33 and the graphene, carbon nanotube or the ito thin film 34 that form channel region, source electrode 32 and leakage
Pole 33 is connected through the film 34, is provided with dielectric layer 35 on channel region, the first grid as top-gated is provided on dielectric layer 35
36, while directly being contacted as the second grid 37 of control gate with the channel region there are also one, the second grid 37 and channel region
Between formed can store knot, such as schottky junction of charge, etc..Aforementioned dielectric layer can be such as silicon nitride, aluminium nitride
Contour K dielectric material composition.Aforementioned source electrode, drain electrode, first grid, second grid etc. can be aluminium, copper, tungsten, molybdenum, gold, caesium
Other conductor materials equal metal materials or above-mentioned.The field effect transistor at work, can use channel and control
Aforementioned " knot " that is formed between grid forms charge storage layer, and can by applying voltage on the control gate, realize it is erasable and
Control.
Embodiment 8: please referring to Figure 10 and show one of embodiment field effect transistor, is FinFET (fin
Field effect transistor), source region 42, drain region 43 and fin channel area 44 including being formed on a substrate 41 (further include certainly
Corresponding source electrode, drain electrode etc., are not shown in the figure), source region 42 is connect with drain region 43 through fin channel area 44, and fin channel is set in area
It is equipped with dielectric layer (not shown), first grid 45 and second grid 46 are provided on dielectric layer, the first grid 45 and
Two grids 46 are centered around 44 two sides of fin channel area and top.The second grid 46 is formed with fin channel area 44 to store
Knot of charge, such as schottky junction, hetero-junctions, homojunction, PN junction, PIN junction, semiconductor/insulating layer knot etc..In the FinFET
The material of each component part can be identical as previous embodiment, and working principle is also substantially the same as in the previous example.
In foregoing embodiments, channel region also be can be replaced by such as indium tin oxide, indium potassium zinc oxygen, tin oxide, dioxy
Change titanium, gallium oxide, ITO, In2O3, zinc oxide, p-type Cu2O、SnO、NiO、CuO、V2O3、WO3, molybdenum oxide, Co3O4In equal materials
The material layer that one or more combinations is formed.These materials above-mentioned can be the forms such as nano wire, nanometer sheet.It should manage
Solution, above-described embodiment are only to illustrate the technical ideas and features of the present invention, and its object is to allow person skilled in the art
Scholar can understand the content of the utility model and implement accordingly, not limit the protection scope of the present invention.All
According to equivalent change or modification made by the spirit of the present invention essence, should be covered within the scope of the utility model.
Claims (10)
1. a kind of field effect transistor, including source electrode, drain electrode, channel region and first grid, through ditch between the source electrode and drain electrode
The connection of road area, the first grid setting over the channel region, and are provided with dielectric layer between the first grid and channel region；Its
Be characterized in that: the field effect transistor further includes at least one second grid, at least one described second grid and the ditch
Road area cooperatively forms the knot to store charge.
2. field effect transistor as described in claim 1, it is characterised in that: the field effect transistor includes conduction region, institute
It states conduction region and cooperatively forms the knot as the second grid and the channel region.
3. field effect transistor as claimed in claim 2, it is characterised in that: set between the second grid and the channel region
It is equipped with insulating layer and/or buffer layer.
4. field effect transistor as described in claim 1, it is characterised in that: the field effect transistor further includes and described
The semiconductor region of two grids cooperation.
5. field effect transistor as claimed in claim 4, it is characterised in that: be arranged between the semiconductor region and second grid
There is insulating layer.
6. field effect transistor as described in claim 4 or 5, it is characterised in that: the second grid, which is set to, described partly leads
Any one or more specified regions around body area, any one or more described specify region to deviate the semiconductor region and ditch
Region between road area.
7. field effect transistor as described in claim 1, it is characterised in that: the field effect transistor includes semiconductor layer,
Distribution active area, drain region and channel region in the semiconductor layer, the source region, drain region are connected with source electrode, drain electrode respectively.
8. field effect transistor as claimed in claim 7, it is characterised in that: the second grid is set to the channel region week
The specified region of any one or more enclosed, any one or more described specify region and the source region, drain region and first grid
In region where any one it is contactless and be not also overlapped.
9. field effect transistor as described in claim 1, it is characterised in that: the field effect transistor is that fin field effect is brilliant
Body pipe is distributed in the second grid described at least one on the fin channel region of the transistor.
10. a kind of storage memory, it is characterised in that including field effect transistor of any of claims 1-9.
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| CN201820870458.6U CN208444843U (en) | 2018-06-06 | 2018-06-06 | Field effect transistor and storage memory |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN108767014A (en) * | 2018-06-06 | 2018-11-06 | 中国科学院宁波材料技术与工程研究所 | Field-effect transistor, storage memory and its application |
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| CN108767014A (en) * | 2018-06-06 | 2018-11-06 | 中国科学院宁波材料技术与工程研究所 | Field-effect transistor, storage memory and its application |
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