A kind of arbitrary waveform generator based on FPGA closed-loop control
Technical field
The utility model relates to a kind of waveform generators, more particularly to a kind of random waveform based on FPGA closed-loop control
Generator.
Background technique
A kind of signal generator of the arbitrary waveform generator as multimode, it not only can produce sawtooth wave, sine wave
Deng conventional waveform, and the diversified feature of carrier modulation can also be shown, make waveform that amplitude modulation, phase modulation, frequency modulation and pulse occur
Modulation etc..The editor that waveform can be even realized using computer software, generates random waveform required for user.Random waveform hair
Raw device is widely used in automatic control, electronic circuit and scientific experimentation field, is that a electron measurement work offer meets skill
The electric signal equipment that art requires, therefore swift and violent development is all obtained in every field.
Arbitrary waveform generator is the best instrument of emulation experiment in laboratory, and arbitrary waveform generator is the one of signal source
Kind, it has the characteristics that signal source is all.It is generally acknowledged that known signal required for signal source is mainly provided to circuit-under-test is (each
Kind waveform), then with the interested parameter of other instrument measurements.Visible signal source is in electronic experiment and test processes, not
Any parameter is measured according to the requirement of user, various test signals is emulated, is supplied to circuit-under-test, to reach test
It needs.Arbitrary waveform generator passes through the data sample point for reading look-up table, to create function waveform and random waveform.It is most of
Modern arbitrary waveform generator synthesizes (DDS) technology using direct signal, provides signal in extensive frequency range.
Utility model content
The task of the utility model is to provide a kind of arbitrary waveform generator based on FPGA closed-loop control, steady to realize
Fixed output and large-scale voltage are adjusted.
Technical solutions of the utility model are such that a kind of arbitrary waveform generator based on FPGA closed-loop control, including
FPGA module, D/A converter module, low-pass filter circuit, programmable amplifying circuit, analog-to-digital conversion module, the FPGA module difference
It is connect with D/A converter module, programmable amplifying circuit and analog-to-digital conversion module, the output end connection of the D/A converter module is low
The output end of bandpass filter circuit, the low-pass filter circuit connects programmable amplifying circuit, and the analog-to-digital conversion module is put with program-controlled
The output end connection acquisition output signal voltage value of big circuit, the FPGA module includes control module, phase accumulator and wave
Shape memory, the phase accumulator are controlled by the control module and carry out data accumulation, the wave memorizer stored waveform
Data and according to the data accumulation result output waveform of the phase accumulator to D/A converter module, the control module receives
The output signal voltage value of analog-to-digital conversion module acquisition and the amplification factor for controlling the programmable amplifying circuit.
Further, including keyboard input module and display module, the keyboard input module and display module with it is described
Control module connection.
Further, including host computer, the FPGA module include RAM module, and the RAM module turns for storing modulus
The output signal voltage value of block acquisition is changed the mold, the host computer is connect with FPGA module reads RAM module storing data.
Further, the wave memorizer includes sinusoidal wave data memory, square wave data storage, triangular wave data
Memory and sawtooth wave data storage.
The utility model compared with prior art the advantages of be: use FPGA for hardware controls core, produced using FPGA
The analog signal of raw specific waveforms, is filtered the DAC waveform signal exported by low-pass filter circuit, removes noise
It influences, keeps its signal more steady.Filter output signal is sampled after programmable amplifier through high-speed ADC, and in real time
ADC collection value be passed to FPFA in carry out parameter preset be compared, by pid algorithm change programmable amplifier amplification factor come
Output voltage adjustable extent is bigger, more stable signal specific, more perfect to the protection of circuit.It is realized by host computer
Storage, display and the analysis of waveform, it is more intuitive and convenient, more parameters and data can be obtained by analysis, convenient for wave
The observation and analysis of shape.
Detailed description of the invention
Fig. 1 is the arbitrary waveform generator structural schematic diagram based on FPGA closed-loop control.
Fig. 2 is FPGA module schematic diagram.
Fig. 3 is phase accumulator and phase accumulator structural schematic diagram.
Fig. 4 is D/A converter module schematic diagram.
Fig. 5 is low-pass filter circuit schematic diagram.
Fig. 6 is programmable amplifying circuit schematic diagram.
Fig. 7 is programmable amplifying circuit gain control circuit schematic diagram.
Specific embodiment
Below with reference to embodiment, the utility model is described in further detail, but not as the restriction to the utility model.
Incorporated by reference to shown in Fig. 1, the arbitrary waveform generator based on FPGA closed-loop control that the present embodiment is related to, including FPGA
Module 1, D/A converter module 2, low-pass filter circuit 3, programmable amplifying circuit 4, analog-to-digital conversion module 5,6 and of keyboard input module
Display module 7.Using the EP4CE15FPGA of ALTERA, keyboard input module 6 and display module 7 are FPGA module 1
ILI9341TFT touch screen.Information exchange between FPGA module 1 and ILI9341TFT touch screen realizes the control of output parameter,
According to touch screen be passed to information generate a cycle in voltage parameter and recycle output control D/A converter module continue it is defeated
Out.
Specifically, as shown in connection with fig. 2, in FPGA module 1, the soft core of an embedded QSYS constructs II processor of NIOS
Module forms control module 1a, and control module 1a includes CPU, EPCS, SDRAM, JTAG, SYSID and correlated inputs output end
Mouth (I/O) etc. realizes key logic control, LCD screen driving and Correlation method for data processing etc..FPGA module 1 further includes that phase is tired
Add device 1b, wave memorizer 1c and RAM module 1d, waveform generates mainly by two moulds of phase accumulator 1b and wave memorizer 1c
Block is completed, and the data difference in wave memorizer 1c can generate different waveform signals, and wave memorizer 1c includes
Sinusoidal wave data memory, square wave data storage, triangular wave data storage and sawtooth wave data storage.As shown in figure 3,
This part-structure are as follows: phase accumulator 1b is connected with wave memorizer 1c.Input port RESET, frequency control word K and clock are defeated
Enter CLK.Output port: Wave data sin.Phase accumulator 1b is substantially a counter, is controlled according to the frequency of input
Number of words value is different, carries out the data accumulation that step value does not wait and output, the waveform of a cycle is stored in wave memorizer 1c
Data export corresponding waveforms amplitude according to the accumulation result of phase accumulator 1b, these amplitude continuously exported points are just constituted
Specific waveform.
As shown in Figures 4 and 5, the waveform continuously exported converts digital signals into simulation letter by D/A converter module 2
Number, then pass through 3 filtering and noise reduction of low-pass filter circuit.D/A converter module 1 uses AD9708 high-speed digital-analog conversion chip, such core
Piece is eight bit data interface, and maximum speed reaches 125Msps, and eight bit parallel datas are inputted D/A converter module 2 by FPGA module,
Analog signal is converted by digital signal, exports two-way analog difference signal.Low-pass filter circuit 3 is seven rank passive filter circuits
Two-way analog difference signal is filtered, is mainly made of capacitance resistance and inductance, cutoff frequency is set as 40MHz, this
Sample can remove the influence such as noise, improve signal anti-interference ability.Then two-way analog differential is believed by two amplifiers
Number it is changed into one-channel signal, while output signal amplitude can be manually adjusted, maximum exportable 10VppSignal, convenient for applying
Different occasions.
As shown in fig. 6, FPGA module 1 by control programmable amplifier, first makes precompensation parameter input programmable amplifying circuit 4
It generates certain amplification factor, and collected voltage value is returned to FPGA after the acquisition of analog-to-digital conversion module 5 in signal.One side
5 collection value of analog-to-digital conversion module is compared with predeterminated voltage in face, controls DAC output control electricity by pid algorithm FPGA
Pressure changes the programmable amplifier gain in Fig. 7, changes the amplification factor of programmable amplifier, burning voltage, 16 lists can be used in DAC
On the other hand collected voltage is stored in the RAM module 1c of FPGA module 1 by channel DAC8411, host computer 8 and FPGA mould
RAM module 1d storing data is read in the connection of block 1, is analyzed by signal Tap tool and MATLAB output waveform.