CN208424250U - Control device for AGV motor - Google Patents

Abstract

The utility model belongs to field of embedded technology, specifically provides a kind of control device for AGV motor.Aim to solve the problem that the problem of prior art can not accurately and efficiently drive the motor of AGV trolley.For this purpose, the utility model provides a kind of control device for AGV motor, including sequentially connected master controller, FPGA controller and digital analog converter；The data-signal that master controller is used to be sent according to FPGA controller obtains motor driven instruction, and motor driven instruction is sent to FPGA controller；FPGA controller is used to obtain the data-signal and motor drive signal of digital analog converter transmission, and data-signal and motor drive signal are respectively sent to master controller and digital analog converter；Digital analog converter is used to motor drive signal being converted to analog signal, and analog signal is sent to AGV motor.Master controller may be implemented to the real time access of data in device provided by the utility model, improves the drive efficiency to AGV motor.

Description

Control device for AGV motor

Technical field

The utility model belongs to field of embedded technology, and in particular to a kind of control device for AGV motor.

Background technique

In complicated AGV site environment, it is each efficiently to complete that the module for installing various functions is needed on AGV trolley Kind task, the controller of AGV trolley connect with each functional module and pass through the data for handling each functional module to realize phase The function of answering, therefore a large amount of I/O interface of controller needs and the convenient data read capability of high speed of AGV trolley, but mistake The time that more I/O interface access controllers will lead to controller access I/O interface is slower, reduces real-time.Wherein, it is actually answering In, AGV trolley is higher to motor-driven rate request, in order to accurately and efficiently driving motor, needs to enhance AGV small The ability of vehicle controller efficient access I/O interface is flexibly operated and is expanded to AGV trolley to realize.

Utility model content

In order to solve the above problem in the prior art, in order to which the prior art can not accurately and efficiently drive AGV trolley Motor the problem of, the utility model provides a kind of control device for AGV motor, including sequentially connected main control Device, FPGA controller and digital analog converter；The input terminal of the digital analog converter is connect with the FPGA controller, the digital-to-analogue The output end of converter is connect with AGV motor；

The data-signal that the master controller is used to be sent according to the FPGA controller obtains motor driven instruction, and will The motor driven instruction is sent to the FPGA controller；

The FPGA controller is used to obtain the data-signal that the digital analog converter is sent and motor driven instruction, And the data-signal and motor driven instruction are respectively sent to the master controller and the digital analog converter；

The digital analog converter is used to motor driven instruction being converted to analog signal, and the analog signal is sent out It send to the AGV motor.

In the preferred embodiment of above-mentioned apparatus, the master controller and the FPGA controller by address bus and Data/address bus connection.

In the preferred embodiment of above-mentioned apparatus, the FPGA controller and the digital analog converter pass through SPI communication Bus connection.

In the preferred embodiment of above-mentioned apparatus, the AGV motor includes motor driver and motor, and the digital-to-analogue turns The output end of parallel operation is connect with the motor driver, and the motor driver is according to the analog signal driving motor.

In the preferred embodiment of above-mentioned apparatus, the IP kernel of the FPGA controller carries the IP kernel of MCU platform.

In the preferred embodiment of above-mentioned apparatus, the digital analog converter is the conversion that output data precision is 16 Device.

In the preferred embodiment of above-mentioned apparatus, the digital analog converter includes DAC8563 chip.

Compared with the immediate prior art, above-mentioned technical proposal is at least had the following beneficial effects:

1, master controller is connect by FPGA unit with digital analog converter, and it is straight with digital analog converter that master controller may be implemented Row data exchange is tapped into, master controller can directly be written and read behaviour without carrying out corresponding I/O port expansion with logarithm mode converter Make, realizes that the data in master controller logarithm mode converter carry out real time access, and then improve digital analog converter to AGV motor Drive efficiency.

2, the IP kernel of FPGA controller can carry the IP kernel of MCU platform, can be with the data of logarithm mode converter at Reason, and the hardware configuration of whole device can be simplified with the multiple peripheral chips of carry and circuit, on the IP kernel of FPGA controller The personal code work of layer can also be transplanted to arbitrary MCU platform, high recycling rate.

Detailed description of the invention

Fig. 1 is a kind of primary structure schematic diagram of the control device for AGV motor of embodiment of the utility model.

Specific embodiment

It is practical new below in conjunction with this to keep the objectives, technical solutions, and advantages of the embodiments of the present invention clearer Attached drawing in type embodiment, the technical scheme in the utility model embodiment is clearly and completely described, it is clear that is retouched The embodiment stated is the utility model a part of the embodiment, instead of all the embodiments.Based on the implementation in the utility model Example, every other embodiment obtained by those of ordinary skill in the art without making creative efforts belong to The range of the utility model protection

Preferred embodiments of the present invention are described with reference to the accompanying drawings.It should be understood by those skilled in the art that It is that these embodiments are used only for explaining the technical principle of the utility model, it is not intended that limit the protection of the utility model Range.

Refering to attached drawing 1, Fig. 1 illustratively gives the primary structure in the present embodiment for the control device of AGV motor, Master controller, FPGA controller and digital analog converter are sequentially connected with, and the input terminal of digital analog converter is connected with FPGA controller, number The output end of mode converter is connect with AGV motor.As shown in Figure 1, including master for the control device of AGV motor in the present embodiment Controller, FPGA controller and digital analog converter.

Master controller by address bus and data/address bus and FPGA (Field-Programmable Gate Array, Field programmable gate array) controller connection, wherein ADDR1-ADDR8 is address bus, and D0-D15 is data/address bus.FPGA Controller can send data-signal to master controller by data/address bus, wherein data-signal can be FPGA controller and turn The data-signal that digital analog converter is sent is sent out, the data-signal that master controller can be sent according to FPGA controller obtains corresponding Motor driven instruction, and motor driven instruction is sent to FPGA controller by data/address bus, motor driven instructs can be with It is the correspondence driving instruction generated according to the model of AGV motor, speed control method and input voltage and input current value.

Master controller can also send GPMC_CS signal, nOE signal and nWE signal, GPMC_CS to FPGA controller Signal is that the bank piece of master controller RAM (random access memory, random access memory) selects, and nOE signal is to read Enable signal, nWE signal are write enable signal, and FPGA controller can send EINT interrupt signal to master controller.In EINT Break signal can be when master controller carries out procedure operation, and the data of FPGA controller have been stored in the data register of master controller When the data output register of device or master controller has emptied, FPGA controller is sent by interface circuit to master controller Interrupt request singal, master controller can suspend the program for executing and being currently executing, then execute in the case where meeting certain condition It is correspondingly able to carry out the subprogram of input/output operations, after to be entered/output operation is finished, master controller can be returned It returns and continues to execute the program being interrupted originally.FPGA controller can send EINT interrupt signal to master controller can be to avoid master Controller wastes a large amount of waiting time, improves the working efficiency of master controller.

FPGA controller can simulate SRAM (Static Random Access Memory, the static random of master controller Access memory), master controller can directly be written and read the data in FPGA controller, carry out the direct visit of data It asks.IP (intellectual property, intellectual property) core of FPGA controller can carry MCU The IP kernel of (Microcontroller Unit, micro-control unit) platform.In practical applications, it can be taken in FPGA controller The IP kernel for carrying 8051 single-chip microcontrollers develops hardware using the mode of software programming, and FPGA controller can be allowed to generate different IO timing Operation.In addition, FPGA controller can be with the multiple peripheral chips of carry and circuit, and it can be direct to certain data-signals It is handled, while simplifying hardware configuration, upper-layer user's code can also be transplanted to any MCU platform, high recycling rate. The data-signal that digital analog converter is sent is forwarded to master controller by FPGA unit, and master controller is opened up without carrying out corresponding I/O port Exhibition, can logarithm mode converter be directly written and read, it is real to realize that the data in master controller logarithm mode converter carry out When access.

In practical applications, master controller needs a large amount of I/O interface and the convenient data read capability of high speed, needs Corresponding IO expansion and the specific chip register of access are carried out to complete the specific function of corresponding functional module, this is to master control The requirement of real-time of device processed is higher.But to will cause main control slack-off to the access time of data for excessive I/O interface, leads to reality When property reduces.FPGA controller can distribute certain address space for digital analog converter by carrying IP kernel for main control Device access, to reduce the burden of master controller data acquisition.When FPGA controller is connect with multiple digital analog converters, FPGA The IP kernel of controller can open up different address spaces according to the quantity of digital analog converter, so that master controller can be visited directly It asks these address spaces, reduces the complexity of entire hardware system, improve the convenience of master controller data access.

FPGA controller can by SPI (Serial Peripheral Interface, Serial Peripheral Interface (SPI)) interface with The motor drive signal that master controller is sent can be forwarded to digital-to-analogue and turned by the connection of at least one digital analog converter, FPGA controller Parallel operation, motor drive signal is converted to analog signal by digital analog converter, and the analog signal is sent to AGV motor.

FPGA controller can by SPI (Serial Peripheral Interface, Serial Peripheral Interface (SPI)) interface with The connection of at least one digital analog converter.The motor drive signal that FPGA controller is sent can be converted to simulation by digital analog converter Signal, and the analog signal is sent to AGV motor.Wherein, digital analog converter may include DAC8563 chip, and AGV motor can To include motor driver and motor, motor driver is for driving motor.

By taking motor model is EVDR-K045CQE as an example, control model that there are three types of the motors, respectively speed control mode, Duty control model and position control mode.In practical applications, speed control mode can be used, speed control mode uses Direct I/O or communication far end I/O signal control operating, the control target using revolving speed as motor running.It is connected to motor After motor driver receives the analog signal of digital analog converter, exports corresponding voltage and the speed of motor is controlled, number Mode converter can export 16 data, so as to realize the high-precision control to motor.

So far, it has been combined preferred embodiment shown in the drawings and describes the technical solution of the utility model, still, this Field technical staff is it is easily understood that the protection scope of the utility model is expressly not limited to these specific embodiments.? Under the premise of the principles of the present invention, those skilled in the art can make equivalent change to the relevant technologies feature Or replacement, the technical solution after these changes or replacement are fallen within the protection scope of the utility model.

Claims (7)

1. a kind of control device for AGV motor, it is characterised in that including sequentially connected master controller, FPGA controller and Digital analog converter；The input terminal of the digital analog converter is connect with the FPGA controller, the output end of the digital analog converter It is connect with AGV motor；

The data-signal that the master controller is used to be sent according to the FPGA controller obtains motor driven instruction, and will be described Motor driven instruction is sent to the FPGA controller；

The FPGA controller is used to obtain the data-signal that the digital analog converter is sent and motor driven instruction, and will The data-signal and motor driven instruction are respectively sent to the master controller and the digital analog converter；

The digital analog converter is used to motor driven instruction being converted to analog signal, and the analog signal is sent to The AGV motor.

2. the control device according to claim 1 for AGV motor, which is characterized in that the master controller with it is described FPGA controller is connected by address bus with data/address bus.

3. the control device according to claim 2 for AGV motor, which is characterized in that the FPGA controller and institute Digital analog converter is stated to connect by SPI communication bus.

4. the control device according to claim 3 for AGV motor, which is characterized in that the AGV motor includes motor Driver and motor, the output end of the digital analog converter are connect with the motor driver, and the motor driver is according to institute State analog signal driving motor.

5. the control device according to claim 4 for AGV motor, which is characterized in that the IP of the FPGA controller The IP kernel of core carrying MCU platform.

6. the control device according to any one of claims 1-5 for AGV motor, which is characterized in that the digital-to-analogue Converter is the converter that output data precision is 16.

7. the control device according to claim 6 for AGV motor, which is characterized in that the digital analog converter includes DAC8563 chip.