CN203149961U - Reconstructible EDA experimental platform - Google Patents
Reconstructible EDA experimental platform Download PDFInfo
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- CN203149961U CN203149961U CN2013201113760U CN201320111376U CN203149961U CN 203149961 U CN203149961 U CN 203149961U CN 2013201113760 U CN2013201113760 U CN 2013201113760U CN 201320111376 U CN201320111376 U CN 201320111376U CN 203149961 U CN203149961 U CN 203149961U
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Abstract
The utility model relates to a reconstructible EDA experimental platform, comprising a core processing unit and a peripheral circuit, wherein the core processing unit comprises a host processing FPGA chip and a slave processing FPGA chip in direct interconnection, and the peripheral circuit comprises a main memory, an LCD interface circuit, an LED interface circuit, a keyboard interface circuit, a mouse interface circuit, an SPI interface circuit, a network interface, an A/D interface chip, two configuration storage chips, a JTAG interface circuit and the like. According to the utility model, through reconstruction of functions of the host and slave FPGA chips, application characteristics of the experimental platform can respectively meet requirements of application occasions like an embedded experimental platform, a DSP experimental platform and an FPGA experimental platform, so an application scope of the reconstructible EDA experimental platform is broadened, a plurality of experiment contents are combined for experiment and training on the same experimental platform, cost for purchase of the experimental platform is recued for a user, and application efficiency of the experimental platform is improved.
Description
Technical field
The utility model relates to a kind of EDA experiment porch, particularly a kind of reconfigurable EDA experiment porch.
Background technology
Carry out the abbreviation of EDA(Electronic Design Automation, be translated into electric design automation) experiment has very important booster action to principle and method, the raising EDA application technology that improves the user and understand the EDA design.Yet people find in carrying out the process of various experiments at present, and along with experiment content and experiment that people need carry out are of different types, needed experiment porch is also different fully.Particularly, mainly divide three class experiment porchs, be based on the experiment porch of single-chip microcomputer respectively, based on the experiment porch of DSP with based on the experiment porch of FPGA.This three classes experiment porch emphasis has nothing in common with each other: SCM Based experiment porch more is for the user provides comprehensive calculating and control resource, makes the user understand and grasps the operation logic of microcontroller and the basic control function that can finish.Experiment porch based on DSP is for the user provides high performance calculation services more, and the user can be realized such as some typical application services such as image processing, high-performance calculations.And based on the abbreviation of FPGA(Field-Programmable Gate Array, be field programmable gate array) experiment porch then be mainly the user abundant programmable logic resource be provided, make the user develop various combinations or sequential logical circuit neatly according to the application demand of reality, finish specific application demand.Yet, this three classes experiment porch the function that can provide single relatively, range of application is limitation relatively also.
Summary of the invention
The technical problems to be solved in the utility model is: provide a kind of reconfigurable EDA experiment porch, to solve the function singleness that above-mentioned prior art exists, the weak point that range of application is relatively limited to.
The technical scheme that solves the problems of the technologies described above is: a kind of reconfigurable EDA experiment porch, comprise core processing unit and peripheral circuit, described core processing unit comprise be used to finish various main calculating and control function main handle fpga chip and be used for finishing into the conversion of various interface circuit data interface format and data latch function from handling fpga chip, describedly mainly handle fpga chip and to carry out data interconnected from handling the mode that adopts direct line between the fpga chip.
Further technical scheme of the present utility model is: the described main fpga chip of handling adopts the Spartan-3XC3S1000 chip, and is described from handling fpga chip employing Virtex-E XCV600E chip.
Further technical scheme of the present utility model is: described peripheral circuit contains the primary memory that is only conducted interviews and control by main processing fpga chip, the address wire of this primary memory, data line and access control signal wire directly are connected with the main I/O port of handling fpga chip, and the clock line of primary memory is connected with the main output terminal of clock mouth of handling fpga chip.
Described peripheral circuit contains LCD interface circuit, LED interface circuit, keyboard interface circuit and mouse interface circuit, and this LCD interface circuit, LED interface circuit, keyboard interface circuit and mouse interface circuit directly with from the I/O port signal line of handling fpga chip output are connected.
Described LCD interface circuit, LED interface circuit, keyboard interface circuit and mouse interface circuit and also be connected with for amplifying from handling the driving circuit that the fpga chip output signal is carried out from handling between the fpga chip output I/O port signal line.
Described peripheral circuit contains RS232 interface circuit, I2C interface circuit, SPI interface circuit and netting twine interface, and this RS232 interface circuit, I2C interface circuit, SPI interface circuit and netting twine interface I/O port signal line direct and from handle fpga chip respectively link to each other.
Described peripheral circuit contains the A/D interface chip that uses when being used to experiment porch that the simulating signal amount is conducted interviews control, and this A/D interface chip directly links to each other with the main fpga chip of handling.
Described A/D interface chip is the ADC0809 chip.
Described peripheral circuit contains two configuration store chips that are used for storage fpga chip operational process relative program, and these two configuration store chips are the 24C256 chip, and described two configuration store chips directly link to each other with the main fpga chip of handling.
Described peripheral circuit contains to be useful on to main to be handled fpga chip and provides the jtag interface circuit of program loading and renewal path from handling fpga chip, and this jtag interface circuit directly links to each other with the main fpga chip of handling.
Because adopt said structure, the reconfigurable EDA experiment porch of the utility model compared with prior art has following beneficial effect:
(1) diverse in function has wide range of applications:
Because core processing unit of the present utility model comprises for main processing fpga chip with from handling fpga chip, wherein the master handles fpga chip and passes through transmission and the exchange that the IO interface is realized data between the fpga chip from handling, the main fpga chip of handling is mainly finished main calculating and control task in the restructural EDA experiment porch, mainly finishes functions such as the data structure format conversion of various interface signal and data latch from handling fpga chip.Therefore, the reconfigurable EDA experiment porch of the utility model can be by to organizing the reconstruct of heavy fpga chip function, make this experiment porch application characteristic can satisfy the application scenario of embedded experiment porch, DSP experiment porch and FPGA experiment porch respectively, greatly enlarged the range of application of experiment porch.
(2) also be connected with the multiple interfaces circuit owing to of the present utility model from handling fpga chip, make this EDA experiment porch can satisfy different peripheral interface circuit modules, provide good hardware supported for this experiment porch satisfies diversified experimental applications demand by reconstruct.
(3) use the reconfigurable EDA experiment porch of the utility model, the kinds of experiments content can be incorporated in and experimentize on the experiment porch and train, greatly reduced the cost that the user buys experiment porch, improved the application efficiency of experiment porch.
Below, the technical characterictic to the reconfigurable EDA experiment porch of the utility model is further described in conjunction with the accompanying drawings and embodiments.
Description of drawings
Fig. 1: the structured flowchart of the reconfigurable EDA experiment porch of the utility model;
Fig. 2: the schematic diagram of driving circuit;
Fig. 3: the catenation principle figure of spi bus;
Fig. 4: the main catenation principle figure that handles fpga chip and A/D interface chip.
Embodiment
Embodiment one:
A kind of reconfigurable EDA experiment porch (structured flowchart is referring to Fig. 1), comprise core processing unit and peripheral circuit, described core processing unit comprises main handles fpga chip and from handling fpga chip, wherein, the main fpga chip of handling adopts the Spartan-3XC3S1000 chip, is used for finishing various main calculating and control function; Adopt Virtex-E XCV600E chip from handling fpga chip, be used for finishing conversion and data latch function into various interface circuit data interface format, describedly mainly handle fpga chip and to carry out data interconnected from handling the mode that adopts direct line between the fpga chip.
Described peripheral circuit contains primary memory, LCD interface circuit, LED interface circuit, keyboard interface circuit and mouse interface circuit, RS232 interface circuit, I2C interface circuit, SPI interface circuit and netting twine interface, A/D interface chip, two configuration store chips, jtag interface circuit, wherein
Described primary memory is only conducted interviews by main processing fpga chip and controls, the address wire of this primary memory, data line and access control signal wire directly are connected with the main I/O port of handling fpga chip, and the clock line of primary memory is connected with the main output terminal of clock mouth of handling fpga chip.
Described LCD interface circuit, LED interface circuit, keyboard interface circuit and mouse interface circuit are connected with the I/O port signal line of exporting from the processing fpga chip by the driving circuit that is used for amplifying from handling the fpga chip output signal.
Described RS232 interface circuit, I2C interface circuit, SPI interface circuit and netting twine interface I/O port signal line direct and from handle fpga chip respectively link to each other.
Described A/D interface chip uses when being used to experiment porch that the simulating signal amount is conducted interviews control, and this A/D interface chip model is the ADC0809 chip, and described A/D interface chip directly links to each other with the main fpga chip of handling.
Described two configuration store chips are used for the relative program of storage fpga chip operational process, and these two configuration store chips are model 24C256 chip, and described two configuration store chips directly link to each other with the main fpga chip of handling.
Described jtag interface circuit is used for handling fpga chip and providing program to load and the renewal path from handling fpga chip to main, and this jtag interface circuit directly links to each other with the main fpga chip of handling.
Implementation method when the reconfigurable EDA experiment porch of the utility model is used for carrying out the motor-driven experiment is as follows:
1. when the user need carry out the motor-driven experiment, can make the main main functionality that fpga chip is finished motor-driven control of handling by designing and load to main processing fpga chip with from the program of handling fpga chip.
2. carry out format conversion from handling fpga chip for finishing the relevant control parameter that main processing fpga chip is calculated, transfer to driving circuit.And after driving circuit amplifies according to the signal received, drive motor is controlled, thereby realize utilizing the restructural experiment porch to finish motor-driven experiment content, wherein, driving circuit is to carry out the Key Circuit module of in the motor-driven control procedure signal being amplified, and its circuit implementation structure as shown in Figure 2.
3. need conduct interviews and when controlling to typical display devices such as LCD, LED as the user, can design respectively to main processing fpga chip with from handling fpga chip, and load designed program, finish the function that the related data of display modules such as LCD, LED is handled and controlled by the main fpga chip of handling.Then finish from main and handle the data that fpga chip receives and carry out format conversion from handling fpga chip, transfer to LCD and LED signaling interface respectively.Wherein, when transferring signals to the LED signaling interface, its control procedure is simple relatively, only control signal directly need be delivered to the control that can realize on the signal wire of LED display lamp the LED display lamp.
4. then need develop the interface routing of LCD from handling fpga chip to the control of LCD signal, by runnable interface circuit program during the FPGA (Field Programmable Gate Array), realization is to the conversion of LCD access interface agreement and data layout, thereby realization is to visit and the control of LCD.
5. when the user need carry out the data communication experiment, handle the FPGA program and from handling the FPGA program by user exploitation and design are main, wherein, the main FPGA of processing program finishes that data in the data communication are prepared and the relevant treatment work of data after receiving, and then finishes the conversion of data-interface form and signal sequence from handling fpga chip.Be illustrated in figure 3 as the SPI data bus protocol, to need to make the winner handle fpga chip and can realize corresponding data access function by DAP in accordance with regulations according to simulation and the realization of DAP realization to this data communication access protocal from handling fpga chip.
6. when the user need carry out the Comprehensive Experiment of image processing, can develop the main FPGA of processing program by the user, and be loaded in the fpga chip, according to the complexity of computing scale and calculation task, determine whether to need to use restructural EDA primary memory resource.
If the image processing program of user's exploitation is simple relatively, computation complexity is not high, and then this image processing program is finished in FPGA fully.Its needed calculating storage space is simulated realization by the programmable logic cells among the FPGA.
If the image processing program that the user need finish is comparatively complicated, need fairly large storage space to support, then the image processing program of user design can be with the storage resources that provides in the primary memory as addressing space, realizes that finally image handles the various calculation requirements of experiment.
7. when the user need finish temperature control related experiment, can be designed by the user and main handle the FPGA program and from handling the FPGA program, and be respectively loaded in two fpga chips, by the A/D conversion chip target area temperature is sampled, and the result that sampling obtains carried out data-switching, and transfer to the control pre-service that the main FPGA of processing program is correlated with according to the Temperature numerical of receiving, the control result transmission that obtains is extremely from handling fpga chip, by from handling fpga chip according to certain format conversion, finally deliver to relevant control module by driving circuit, realize the stepless control target of temperature.Wherein, the main annexation principle of handling between fpga chip and the A/D interface chip concerns as shown in Figure 4.
Claims (10)
1. reconfigurable EDA experiment porch, comprise core processing unit and peripheral circuit, it is characterized in that: described core processing unit comprise be used to finish various main calculating and control function main handle fpga chip and be used for finishing into the conversion of various interface circuit data interface format and data latch function from handling fpga chip, describedly mainly handle fpga chip and to carry out data interconnected from handling the mode that adopts direct line between the fpga chip.
2. reconfigurable EDA experiment porch according to claim 1 is characterized in that: the described main fpga chip of handling adopts the Spartan-3XC3S1000 chip, describedly adopts Virtex-E XCV600E chip from handling fpga chip.
3. reconfigurable EDA experiment porch according to claim 1, it is characterized in that: described peripheral circuit contains the primary memory that is only conducted interviews and control by main processing fpga chip, the address wire of this primary memory, data line and access control signal wire directly are connected with the main I/O port of handling fpga chip, and the clock line of primary memory is connected with the main output terminal of clock mouth of handling fpga chip.
4. reconfigurable EDA experiment porch according to claim 1, it is characterized in that: described peripheral circuit contains LCD interface circuit, LED interface circuit, keyboard interface circuit and mouse interface circuit, and this LCD interface circuit, LED interface circuit, keyboard interface circuit and mouse interface circuit directly with from the I/O port signal line of handling fpga chip output are connected.
5. reconfigurable EDA experiment porch according to claim 4 is characterized in that: described LCD interface circuit, LED interface circuit, keyboard interface circuit and mouse interface circuit and also be connected with for amplifying from handling the driving circuit that the fpga chip output signal is carried out from handling between the fpga chip output I/O port signal line.
6. reconfigurable EDA experiment porch according to claim 1, it is characterized in that: described peripheral circuit contains RS232 interface circuit, I2C interface circuit, SPI interface circuit and netting twine interface, and this RS232 interface circuit, I2C interface circuit, SPI interface circuit and netting twine interface I/O port signal line direct and from handle fpga chip respectively link to each other.
7. reconfigurable EDA experiment porch according to claim 1, it is characterized in that: described peripheral circuit contains the A/D interface chip that uses when being used to experiment porch that the simulating signal amount is conducted interviews control, and this A/D interface chip directly links to each other with the main fpga chip of handling.
8. reconfigurable EDA experiment porch according to claim 7, it is characterized in that: described A/D interface chip is the ADC0809 chip.
9. reconfigurable EDA experiment porch according to claim 1, it is characterized in that: described peripheral circuit contains two configuration store chips that are used for storage fpga chip operational process relative program, these two configuration store chips are the 24C256 chip, and described two configuration store chips directly link to each other with the main fpga chip of handling.
According to claim 1 to the described reconfigurable EDA experiment porch of the arbitrary claim of claim 9, it is characterized in that: described peripheral circuit contains to be useful on to main to be handled fpga chip and provides the jtag interface circuit of program loading and renewal path from handling fpga chip, and this jtag interface circuit directly links to each other with the main fpga chip of handling.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2013201113760U CN203149961U (en) | 2013-03-12 | 2013-03-12 | Reconstructible EDA experimental platform |
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| Application Number | Priority Date | Filing Date | Title |
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| CN2013201113760U CN203149961U (en) | 2013-03-12 | 2013-03-12 | Reconstructible EDA experimental platform |
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| CN203149961U true CN203149961U (en) | 2013-08-21 |
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| CN2013201113760U Expired - Fee Related CN203149961U (en) | 2013-03-12 | 2013-03-12 | Reconstructible EDA experimental platform |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103150952A (en) * | 2013-03-12 | 2013-06-12 | 广西生态工程职业技术学院 | Reconfigurable electronic design automation (EDA) experimental platform |
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2013
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103150952A (en) * | 2013-03-12 | 2013-06-12 | 广西生态工程职业技术学院 | Reconfigurable electronic design automation (EDA) experimental platform |
| CN103150952B (en) * | 2013-03-12 | 2015-06-17 | 广西生态工程职业技术学院 | Reconfigurable electronic design automation (EDA) experimental platform |
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| Date | Code | Title | Description |
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| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20130821 Termination date: 20150312 |
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| EXPY | Termination of patent right or utility model |