CN208367918U - A kind of high reliability traffic trip vehicle guidance control system - Google Patents
A kind of high reliability traffic trip vehicle guidance control system Download PDFInfo
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- CN208367918U CN208367918U CN201821156940.XU CN201821156940U CN208367918U CN 208367918 U CN208367918 U CN 208367918U CN 201821156940 U CN201821156940 U CN 201821156940U CN 208367918 U CN208367918 U CN 208367918U
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Abstract
The utility model discloses a kind of high reliability traffic trip vehicle guidance control system, guidance information is shown suitable for drive control LED display, including main control card, network transmission module and card is received, network transmission module passes through network or be electrically connected with main control card and reception card respectively to be connected；Main control card includes: core processor, Video decoding module, double RAM processing modules, storage module and FPGA Co-processor Module；Core processor is electrically connected with Video decoding module, double RAM processing modules, storage module respectively；FPGA Co-processor Module and double RAM processing modules are electrically connected.This system is provided with Multistage Control chip, realize multistage division of labor control, it is high to can avoid load caused by one single chip operational mode, chip is reduced because of the generation for phenomena such as high temperature leads to data bit reversal and hardware signal mistake, and it is decoded using fpga chip, each clock cycle is capable of handling more tasks, has many advantages, such as that operational capability is high, failure rate is low and stability is high.
Description
Technical field
The utility model relates to intelligent transportation and technical field of image processing more particularly to a kind of high reliability traffic to go out
The Induction Control system of driving.
Background technique
With the fast development of science and technology, LED display is shown from the image/video of simple text importing till now,
From asynchronous control system to synchronous control system, be widely used in the information publication of every profession and trade, be it is a kind of relatively at
Ripe display technology.The LED synchronization system of the prior art is realized there are mainly two types of frameworks:
1) mode of card is received based on Industrial Control Computer and dot matrix.However, this mode often occurs in practical applications
Phenomena such as blank screen, suspension, crash, main cause is as follows:
High temperature continuous operation is very high to the design requirement of hardware outdoors for a long time for Industrial Control Computer, Industrial Control Computer setting
Processor quantity is few, and continuous heavy-duty service causes processor to be easy fever, any on mainboard along with the factor of outdoor high temperature
Phenomena such as chip high-temperature resistance is poor, is likely to cause data bit reversal, hardware signal mistake, so cause software error and
The crash of operating system；
Client software long-play may cause to report an error due to hardware and software on Industrial Control Computer；Behaviour
Phenomena such as making system long-play cannot safeguard, be also easy to appear Caton, crash；
2) mode based on the soft decoding+FPGA dot matrix driving card of ARM.
Which problem mainly appears on the part ARM, synchronous to shield data process load height rich in color, outdoors continuous height
Temperature operation, is easy to appear loss firmware, and software reports an error lamp failure, and in addition when LED screen increases, the abundanter arm processor of color is just
It is more inadequate.
Therefore, the prior art is defective, needs to improve.
Utility model content
The purpose of the utility model is to overcome the deficiencies in the prior art, and it is same to provide a kind of high reliability LED traffic guidance screen
Walk control system.
The technical solution of the utility model is as follows: a kind of high reliability traffic trip vehicle guidance control system, is suitable for driving
Dynamic control LED display shows guidance information, including main control card, network transmission module and reception card, network transmission mould
Block by network or is electrically connected connection with main control card and reception card respectively；Main control card includes: core processor, video decoding mould
Block, double RAM processing modules, storage module and FPGA Co-processor Module；Core processor respectively with Video decoding module, double
RAM processing module, storage module are electrically connected；FPGA Co-processor Module and double RAM processing modules are electrically connected；Main control card can
The signal from host computer is received and responds, the image information which generates after main control card resume module passes through network transmission
Module is received clamping and receives, and LED display is driven to show picture.
Preferably, core processor can be ZYNQ-7000 processor, including ARM chip and fpga chip；In processor
ARM chip is responsible for the work operation of system, including network configuration, parameter save, system mode is shown, log recording, USB interface
Driving and WEB page login etc., fpga chip are responsible for JPEG decoding and are H.264 decoded；The core processor can receive
And the signal from host computer is responded, and the image information that preliminary treatment generates is stored in storage module to other component
It is further processed.
Preferably, storage module includes the one or more of RAM card, flash memory and SD card；RAM card can be in DDR3
It deposits, and one end of RAM card and core processor are electrically connected；Flash memory can be Nand Flash chip；Storage module can be deposited
The image information for storing up core processor preliminary treatment, can also provide the image information prestored or program code.
Preferably, core processor is electrically connected with double RAM processing modules, double RAM processing modules include two data selectors
With two RAM chips, two data selectors are respectively the first data selector and the second data selector, and two RAM chips are respectively
First RAM chip and the second RAM chip；The output end of the input terminal connection core processor of first data selector, the first number
The input terminal of the first RAM chip and the second RAM chip, the first RAM chip and second are electrically connected according to the output end of selector
The output end of RAM chip is separately connected the input terminal of the second data selector, and the output end of the second data connector connects FPGA
Co-processor Module；Double RAM processing modules start with system electrification synchronous initiation, and the first data selector receives image data simultaneously
The format of data is judged, two kinds of results can be generated: when data format is incorrect, without data processing and rejecting；
It is transferred to the first RAM chip and the second RAM chip when the data format is correct and carries out data processing, through the first RAM chip and the
The data of two RAM chips processing are transferred to the second data selector and make format judgement again, only retain the data of correct format；It is logical
Ineligible image is rejected in the selection for crossing data, is realized RAM ping-pong operation, is improved the working efficiency of main control card.
Preferably, core processor is established a connection by connecting double RAM processing modules with FPGA Co-processor Module, it should
FPGA Co-processor Module can be ATREA Cyclonc-IV chip, and be also connected with one end of DDR3 memory；The processing of FPGA association
Module is responsible for the image real time transfer of DDR3 memory, realizes gray scale, Gamma correction and generation of driving signal etc..
Preferably, main control card is equipped with network unit, which includes network chip and network interface；Network chip
It can be PHY chip and gigabit PHY chip, network interface can be RJ45 type interface；The output end of network chip connects core
Processor, the output end of the input terminal connection network interface of network chip；The network unit can transmit the signal of host computer, touching
Send out the work of core processor.
Preferably, core processor is also connected with Video decoding module, which includes several Video Decoders；
The input terminal of Video Decoder is connected with video source, and video source includes VGA video source and DVI video source.
Preferably, main control card is additionally provided with audio decoder module, audio decoder module includes several audio DA decoders, audio
DA decoder connects core processor, and the output end of audio DA decoder connects stereo output module.
Preferably, receiving card includes hub chip, RAM card and several LED display interfaces；Hub chip connects net
The output end of network transmission module, one end of RAM card are electrically connected hub chip, and the input terminal of LED display interface connects maincenter
Chip；Hub chip can be ATREA Cyclonc-IV chip, and RAM card can be DDR3 memory, and LED display interface can
To be 74HC245 type interface；The hub chip receives the information of main control card output and is for data processing, and can be by treated
Information is stored in RAM card and waits driver to take or directly export picture by LED display interface driver.
Preferably, in main control card and receiving equipped with a network transmission module between card, network transmission module includes network core
Piece and network interface；The input terminal of network interface connects FPGA Co-processor Module, and the output end of network interface connects network chip
Input terminal, network chip output end connection receive card input terminal；The information that the network transmission module exports main control card
It is transferred to reception card.
Using the above scheme, the utility model is capable of providing a kind of high reliability traffic trip vehicle guidance control system,
Compared to other synchronous control systems, this system is had the advantage that
1) core processor in utility model includes ARM chip and fpga chip, and ARM chip and fpga chip cooperate with work
Make, the division of labor is clear, and each clock cycle is capable of handling more tasks, has surmounted the operational capability of arm processor；
2) it is provided with double RAM processing module cooperation core processors in the system of utility model and realizes LED traffic guidance screen
Control includes Multistage Control chip, realizes multistage division of labor control, can avoid the high feelings of load caused by one single chip operational mode
Condition reduces chip because of the generation for phenomena such as high temperature leads to data bit reversal and hardware signal mistake, and failure rate is low, and stability is high；
3) system of utility model is decoded using fpga chip, is reduced the task load of ARM core, is effectively improved ARM
The stability of core；Relative to the system that other use Industrial Control Computer, cost is greatly lowered, and reduces malfunctioning node.
Detailed description of the invention
In order to illustrate the embodiment of the utility model or the technical proposal in the existing technology more clearly, below will be to embodiment
Or attached drawing needed to be used in the description of the prior art is briefly described, it should be apparent that, the accompanying drawings in the following description is only
It is some embodiments of the utility model, for those of ordinary skill in the art, in the premise not made the creative labor
Under, the structure that can also be shown according to these attached drawings obtains other attached drawings.
Fig. 1 is the main control card hardware structure diagram of the utility model；
Fig. 2 is the network transmission module and reception card hardware structure diagram of the utility model.
The embodiments will be further described with reference to the accompanying drawings for the realization, functional characteristics and advantage of the utility model aim.
Specific embodiment
Below in conjunction with the drawings and specific embodiments, the utility model is described in detail.
The utility model provides a kind of high reliability traffic trip vehicle guidance control system, and it is aobvious to be suitable for drive control LED
Display screen show guidance information, including main control card, network transmission module and receive card, network transmission module respectively with master control
Card and reception card by network or are electrically connected connection；Main control card includes: core processor 100, Video decoding module 110, double
RAM processing module 120, storage module 130 and FPGA Co-processor Module 140；Core processor 100 decodes mould with video respectively
Block 110, double RAM processing modules 120, storage module 130 are electrically connected；FPGA Co-processor Module 140 and double RAM processing modules
130 are electrically connected；Main control card can receive and respond the signal from host computer, the figure which generates after main control card is handled
It is received as information is received clamping by network transmission module, and LED display is driven to show picture.
In the present embodiment, core processor 100 can be ZYNQ-7000 processor, including ARM chip and FPGA core
Piece；ARM chip is responsible for the work operation of system in processor, including network configuration, parameter save, system mode is shown, log
Record, USB interface driving and WEB page login etc., fpga chip are responsible for JPEG decoding and are H.264 decoded；Core processing
Device 100 can receive and respond the signal from host computer, and the image information that preliminary treatment generates is stored in storage module
In 130, storage module includes the one or more of RAM card 1301, flash memory 1302 and SD card 1303；RAM card 1301 can be
DDR3 memory, and one end of RAM card 1301 and core processor are electrically connected；Flash memory 1302 can be Nand Flash chip；
Storage module can store the image information of core processor preliminary treatment, can also provide the image information prestored or program generation
Code.
In the present embodiment, core processor 100 is electrically connected with double RAM processing modules 120, and double RAM processing modules 120 are wrapped
Two data selectors and two RAM chips are included, two data selectors are respectively the first data selector 1201 and the selection of the second data
Device 1202, two RAM chips are respectively the first RAM chip 1203 and the second RAM chip 1204；First data selector 1201 it is defeated
Enter the output end of end connection core processor 100, the output end of the first data selector 1201 is electrically connected the first RAM chip
1203 and second RAM chip 1204 input terminal, the output end of the first RAM chip 1203 and the second RAM chip 1204 connects respectively
The input terminal of the second data selector 1202 is connect, the output end of the second data connector 1202 connects FPGA Co-processor Module 140；
Double RAM processing modules 120 start with system electrification synchronous initiation, and the first data selector 1201 receives image data and logarithm
According to format judged, two kinds of results can be generated: when data format is incorrect, without data processing and rejecting；Work as number
It is transferred to the first RAM chip 1203 when correct according to format and the second RAM chip 1204 carries out data processing, through the first RAM chip
1203 and second the data that handle of RAM chip 1204 be transferred to the second data selector 1202 and make format judgement again, only retain
The data of correct format；By the selection of data, ineligible image is rejected, RAM ping-pong operation is realized, improves master control
The working efficiency of card.
In the present embodiment, core processor 100 is by connecting double RAM processing modules 120 and FPGA Co-processor Module 140
It establishes a connection, which can be ATREA Cyclonc-IV chip, and be also connected with DDR3 memory
1301 one end；FPGA Co-processor Module 140 is responsible for the image real time transfer of DDR3 memory 1301, realizes gray scale, Gamma correction
And generation of driving signal etc..
In the present embodiment, main control card be equipped with network unit 150, the network unit 150 include network chip 1501 and
Network interface 1502；Network chip 1501 can be PHY chip and gigabit PHY chip, and network interface 1502 can be RJ45 type
Interface；The output end of network chip 1501 connects core processor 100, and the input terminal of network chip 1501 connects network interface
1502 output end；The network unit 150 can transmit the signal of host computer, trigger the work of core processor.
In the present embodiment, core processor 100 is also connected with Video decoding module 110, if the Video decoding module includes
Dry Video Decoder 1101；The input terminal of Video Decoder 1101 is connected with video source, video source include VGA video source 1102 with
And DVI video source 1103.
In the present embodiment, main control card is additionally provided with audio decoder module 170, and audio decoder module includes several audio DA solutions
Code device 1701, audio DA decoder 1701 connect core processor 100, and the output end connection of audio DA decoder 1701 is stereo
Output module 1702.
In the present embodiment, receiving card includes hub chip 210, RAM card 220 and several LED display interfaces 230；
Hub chip 210 connects the output end of network transmission module, and one end of RAM card 220 is electrically connected hub chip 210, and LED is aobvious
The input terminal of display screen interface 230 connects hub chip 210；Hub chip 210 can be ATREA Cyclonc-IV chip, memory
Card 220 can be DDR3 memory, and LED display interface 230 can be 74HC245 type interface；Hub chip 210 receives master control
The information for blocking output is simultaneously for data processing, and can will treated information is stored in the waiting driver of RAM card 220 takes or
Directly pass through the driving output picture of LED display interface 230.
In the present embodiment, it is equipped with a network transmission module between main control card and reception card, network transmission module includes
Network chip 310 and network interface 320；The input terminal of network interface 320 connects FPGA Co-processor Module 140, network interface 320
Output end connection network chip 310 input terminal, network chip 310 output end connection receive card input terminal；The network
The information that main control card exports is transferred to reception card by transmission module.
Utility model works principle: after system electrification starting, core processor is received by network unit from upper
The signal of machine simultaneously calls modules to start to work, and Video decoding module will be transferred to core processing after image information preliminary decoder
Device, fpga chip carries out JPEG decoding or H.264 decoded one or two to decoded image information in core processor
Decoding process, audio decoder module are decoded audio-frequency unit, and are transferred to stereo output module and show with LED display
Picture synchronization exports audio；The secondary image information decoded can store waits FPGA Co-processor Module to take in storage module
It with processing, can also be screened by the first data selector of double RAM processing modules, the correct data of format are transferred to
One RAM chip and the second RAM chip carry out data processing, and the data handled through the first RAM chip and the second RAM chip are transferred to
Second data selector screens again, and the correct data of format are transferred at FPGA association by the output end of the second data selector
Resume module is managed, realize gray scale, Gamma correction and generates driving signal；FPGA Co-processor Module and network transmission module connect
It connects, and data is transferred to by the input terminal of network interface by network transmission module；The network chip of network transmission module exports
It holds and is connect with the input terminal for receiving card, and data are transferred to reception card by the input terminal by receiving card, receive card and deposit information
It is stored in RAM card to wait driver to take or directly export picture by LED display interface driver, to realize synchronization
Control system drives the function of LED display display picture.
In conclusion the utility model compared to the prior art for, system is provided with the core of multiple responsible different tasks
Piece can avoid the height of load caused by one single chip operational mode, reduce chip because high temperature leads to data bit reversal and hardware signal
The generation of phenomena such as mistake, and using ARM chip and fpga chip collaborative work and fpga chip decoding, each clock week
Phase is capable of handling more tasks, has many advantages, such as that operational capability is high, failure rate is low and stability is high, is a kind of high reliability
Traffic trip vehicle guidance control system.
The above is only the preferred embodiments of the present utility model only, is not intended to limit the utility model, all practical at this
Made any modifications, equivalent replacements, and improvements etc., should be included in the guarantor of the utility model within novel spirit and principle
Within the scope of shield.
Claims (9)
1. a kind of high reliability traffic trip vehicle guidance control system is suitable for drive control LED display and shows traffic guidance
Information, including main control card, network transmission module and receive card, the network transmission module respectively with main control card and reception cartoon
It crosses network or is electrically connected connection；It is characterized in that, the main control card includes: core processor, Video decoding module, double RAM
Processing module, storage module and FPGA Co-processor Module；The core processor is respectively and at Video decoding module, double RAM
It manages module and storage module is electrically connected；The FPGA Co-processor Module and double RAM processing modules are electrically connected.
2. a kind of high reliability traffic trip vehicle guidance control system according to claim 1, which is characterized in that described
Double RAM processing modules are electrically connected the core processor, and double RAM processing modules further include two data selectors and two RAM
Chip, two data selector are respectively the first data selector and the second data selector, and two RAM chip is respectively
First RAM chip and the second RAM chip；The input terminal of first data selector connects the output of the core processor
End, the output end of the first data selector are electrically connected the input terminal of the first RAM chip and the second RAM chip, and described first
The output end of RAM chip and the second RAM chip is separately connected the input terminal of the second data selector, second data selector
Output end connect FPGA Co-processor Module.
3. a kind of high reliability traffic trip vehicle guidance control system according to claim 1, which is characterized in that described
Storage module includes several RAM cards, and one end of the RAM card and core processor are electrically connected, at the other end and FPGA association
Module is managed to be electrically connected.
4. a kind of high reliability traffic trip vehicle guidance control system according to claim 1, which is characterized in that described
Main control card is equipped with network unit, and the network unit includes network chip and network interface；The output end of the network chip
The core processor is connected, the input terminal of the network chip connects the output end of the network interface.
5. a kind of high reliability traffic trip vehicle guidance control system according to claim 1, which is characterized in that described
Video decoding module includes several Video Decoders, and the input terminal of the Video Decoder is also connected with video source；The video source
Including VGA video source and DVI video source.
6. a kind of high reliability traffic trip vehicle guidance control system according to claim 1, which is characterized in that described
Main control card is additionally provided with audio decoder module, and the audio decoder module includes several audio DA decoders, the audio DA decoding
Device connects the core processor, and the output end of the audio DA decoder connects stereo output module.
7. a kind of high reliability traffic trip vehicle guidance control system according to claim 1, which is characterized in that described
Receiving card includes hub chip, RAM card and several LED display interfaces；The hub chip connects the network transmission mould
The output end of block, the hub chip are electrically connected one end of the RAM card, and the hub chip connects the LED display
The input terminal of interface.
8. a kind of high reliability traffic trip vehicle guidance control system according to claim 1, which is characterized in that described
Network transmission module is set to the master control card module and receives between card module, the network transmission module include network chip with
And network interface；The input terminal of the network interface connects the FPGA Co-processor Module, and the output end of network interface connects net
The input terminal of network chip, the output end of the network chip connect the input terminal for receiving card module.
9. a kind of high reliability traffic trip vehicle guidance control system according to claim 3, which is characterized in that storage
Module further includes flash memory and SD card.
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201821156940.XU CN208367918U (en) | 2018-07-20 | 2018-07-20 | A kind of high reliability traffic trip vehicle guidance control system |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201821156940.XU CN208367918U (en) | 2018-07-20 | 2018-07-20 | A kind of high reliability traffic trip vehicle guidance control system |
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| CN208367918U true CN208367918U (en) | 2019-01-11 |
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| CN201821156940.XU Expired - Fee Related CN208367918U (en) | 2018-07-20 | 2018-07-20 | A kind of high reliability traffic trip vehicle guidance control system |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110930738A (en) * | 2019-11-14 | 2020-03-27 | 宋凤玲 | Information display screen for high-speed intelligent traffic |
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2018
- 2018-07-20 CN CN201821156940.XU patent/CN208367918U/en not_active Expired - Fee Related
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110930738A (en) * | 2019-11-14 | 2020-03-27 | 宋凤玲 | Information display screen for high-speed intelligent traffic |
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| GR01 | Patent grant | ||
| CP01 | Change in the name or title of a patent holder | ||
| CP01 | Change in the name or title of a patent holder |
Address after: 518000 Factory A1501, Tian'an Digital Innovation Park, 441 Huangge Road, Longgang District, Shenzhen City, Guangdong Province Patentee after: Shenzhen Boyuan Science and Technology Innovation Development Co.,Ltd. Address before: 518000 Factory A1501, Tian'an Digital Innovation Park, 441 Huangge Road, Longgang District, Shenzhen City, Guangdong Province Patentee before: SHENZHEN BOYUAN TRAFFIC FACILITIES Co.,Ltd. |
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| CF01 | Termination of patent right due to non-payment of annual fee | ||
| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20190111 |