CN208285625U - High-accuracy multilayer buried blind via wiring board - Google Patents
High-accuracy multilayer buried blind via wiring board Download PDFInfo
- Publication number
- CN208285625U CN208285625U CN201820735429.9U CN201820735429U CN208285625U CN 208285625 U CN208285625 U CN 208285625U CN 201820735429 U CN201820735429 U CN 201820735429U CN 208285625 U CN208285625 U CN 208285625U
- Authority
- CN
- China
- Prior art keywords
- circuit layer
- layer
- circuit
- hole
- dielectric layer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Abstract
The utility model provides a kind of high-accuracy multilayer buried blind via wiring board, it includes the first circuit layer being cascading, first medium layer, the second circuit layer, second dielectric layer, tertiary circuit layer, third dielectric layer, 4th circuit layer, 4th dielectric layer, 5th circuit layer, 5th dielectric layer and the 6th circuit layer, the second dielectric layer is provided with the buried via hole of perforation to the 4th dielectric layer, the inner surface of the buried via hole is coated with a layers of copper, the second circuit layer, tertiary circuit layer, 4th circuit layer, 5th circuit layer keeps electrical connection by the buried via hole, the first circuit layer is provided with the through-hole of perforation to the 6th circuit, the inner surface of the through-hole is coated with a layers of copper, the first circuit layer, the second circuit layer, tertiary circuit layer, 4th circuit layer, 5th circuit layer, 6th circuit layer keeps electricity by the through-hole Connection.The high-accuracy multilayer buried blind via wiring board of the utility model has the advantages that manufacturing process is simple and with high accuracy.
Description
Technical field
The utility model relates to field of circuit boards, and in particular to a kind of high-accuracy multilayer buried blind via wiring board.
Background technique
Power auger control deep hole technology is one kind of HDI product, and HDI is the English of High Density Interconnector
Text is write a Chinese character in simplified form, and high density interconnection (HDI) manufacture is printed circuit board, and printed circuit board is to be aided with conductor wirings institute with insulating materials
The structural member of formation.Printed circuit board when making the final product, will be installed thereon integrated circuit, transistor, diode,
Passive device (such as: resistance, capacitor, connector) and other various electronic components.By conducting wire connection is write, can be formed
Electric signal links and should have function.Therefore, printed circuit board is a kind of platform of offer element connection, to accept connection zero
The substrate of part.
There are two types of HDI is usual, a kind of to be made of laser drilling machine, usual aperture is in 0.075mm-0.15mm, in addition
A kind of to be made of power auger control deep hole, usual aperture is in 0.15mm or more, this referred to as mechanical blind hole.With wiring board technology
Develop, more and more conductting layers are connected using blind hole in route design.Early stage, can not due to mechanical drilling machine technical restriction
Control deep hole is directly bored, production machinery blind hole all is completed first by all layers of blind hole connection as dual platen bore process
Level after the electroplates in hole again with other needs presses together, and such fabrication processing is complex, inefficient, pressing
Often, and internal layer is repeatedly processed, and panel shrinkage is larger, and interlayer offset is more difficult to control, causes precision not high.
Utility model content
High-accuracy multilayer buried blind via route simple the purpose of the utility model is to provide a kind of manufacturing process and with high accuracy
Plate.
The utility model is to solve technical solution used by its technical problem:
A kind of high-accuracy multilayer buried blind via wiring board comprising the first circuit layer that is cascading, first medium layer,
The second circuit layer, second dielectric layer, tertiary circuit layer, third dielectric layer, the 4th circuit layer, the 4th dielectric layer, the 5th circuit layer,
5th dielectric layer and the 6th circuit layer, the second dielectric layer is provided with the buried via hole of perforation to the 4th dielectric layer, described to bury
The inner surface in hole is coated with a layers of copper, and the second circuit layer, tertiary circuit layer, the 4th circuit layer, the 5th circuit layer pass through described
Buried via hole keeps electrical connection, and the first circuit layer is provided with the through-hole of perforation, the inner surface of the through-hole to the 6th circuit
It is coated with a layers of copper, the first circuit layer, the second circuit layer, tertiary circuit layer, the 4th circuit layer, the 5th circuit layer, the 6th electricity
Road floor keeps electrical connection by the through-hole.
Further, the first circuit layer is provided with blind hole, the inner surface plating of the blind hole to the first medium layer
There are a layers of copper, the first circuit layer and the second circuit layer to keep being electrically connected by the blind hole.
Further, the 6th circuit layer is provided with blind hole, the inner surface plating of the blind hole to the 5th dielectric layer
There are a layers of copper, the 5th circuit layer and the 6th circuit layer to keep being electrically connected by the blind hole.
Further, the second circuit layer, second dielectric layer, tertiary circuit layer, third dielectric layer, the 4th circuit layer,
4th dielectric layer, the 5th circuit layer press together in first time process for pressing, and the buried via hole is after first time process for pressing
It is formed by machine drilling and copper-plating technique.
Further, the first circuit layer, first medium layer, the 5th dielectric layer, the 6th circuit layer and the second circuit layer,
Second dielectric layer, tertiary circuit layer, third dielectric layer, the 4th circuit layer, the 4th dielectric layer, the 5th circuit layer are pressed at second
It is pressed together in technique, the through-hole is formed after second of process for pressing by machine drilling and copper-plating technique.
Compared with prior art, the high-accuracy multilayer buried blind via wiring board of the utility model passes through process for pressing system twice
It forms, buried via hole is made after the first first time process for pressing, then pass through second of process for pressing for the dielectric layer of outer layer and electricity
Road is laminated together in buried via hole circuit layer two sides, by mechanical holes drilled through, then is carried out hole metallization and is realized electrical connection, without first every
It is being pressed after layer punching, so as to prevent panel shrinkage and interlayer from deviating the alignment accuracy of caused buried via hole or through-hole,
Improve the precision of circuit board.
Detailed description of the invention
Fig. 1 is a kind of structural schematic diagram of the high-accuracy multilayer buried blind via wiring board of embodiment of the utility model.
Specific embodiment
In order to make the purpose of the utility model, technical solutions and advantages more clearly understood, below in conjunction with attached drawing and implementation
Example, the present invention will be further described in detail.It should be appreciated that specific embodiment described herein is only used to explain
The utility model is not used to limit the utility model.
As shown in Figure 1, an embodiment of the present invention provides a kind of high-accuracy multilayer buried blind via wiring board comprising successively
First circuit layer 11, first medium layer 21, the second circuit layer 12, the second dielectric layer 22, tertiary circuit layer 13, being stacked
Three dielectric layers 23, the 4th circuit layer 14, the 4th dielectric layer 24, the 5th circuit layer 15, the 5th dielectric layer 25 and the 6th circuit layer 16.
The second dielectric layer 22 is provided with the buried via hole 31 of perforation, the interior table of the buried via hole 31 to the 4th dielectric layer 24
Face is coated with a layers of copper 32, and the second circuit layer 12, tertiary circuit layer 13, the 4th circuit layer 14, the 5th circuit layer 15 pass through institute
It states buried via hole 31 and keeps electrical connection.The first circuit layer 11 is provided with the through-hole 41 of perforation to the 6th circuit 16, described logical
The inner surface in hole 41 is coated with a layers of copper 42, the first circuit layer 11, the second circuit layer 12, tertiary circuit layer 13, the 4th circuit
The 14, the 5th circuit layer 15 of layer, the 6th circuit layer 16 keep electrical connection by the through-hole 41.
Further, the first circuit layer 11 is provided with blind hole 51 to the first medium layer 21, the blind hole 51
Inner surface is coated with a layers of copper, the first circuit layer 11 and the second circuit layer 12 and keeps being electrically connected by the blind hole 51.
6th circuit layer 16 is provided with blind hole 61 to the 5th dielectric layer 25, and the inner surface of the blind hole 61 is coated with a layers of copper
62, the 5th circuit layer 25 and the 6th circuit layer 26 keep being electrically connected by the blind hole 61.
The manufacturing process of foregoing circuit plate is as follows:
Firstly, by the second circuit layer 12, second dielectric layer 22, tertiary circuit layer 13, the 23, the 4th electricity of third dielectric layer
Road floor 14, the 4th dielectric layer 24, the 5th circuit layer 15 press together in first time process for pressing, and the buried via hole 31 is first
It is formed after secondary process for pressing by machine drilling and copper-plating technique.
Then, by the first circuit layer 11, first medium layer 21, the 5th dielectric layer 25, the 6th circuit layer 16 and second
Circuit layer 12, second dielectric layer 22, tertiary circuit layer 13, third dielectric layer 23, the 4th circuit layer 14, the 4th dielectric layer 24,
Five circuit layers 15 press together in second of process for pressing, and the through-hole 41 passes through power auger after second of process for pressing
Hole and copper-plating technique are formed.
Finally, by machine drilling in the first circuit layer 11, first medium layer 21 making blind hole 51 respectively and the
Six circuit layers 16, the 5th dielectric layer 25 make blind hole 22, and to 22 copper facing of the blind hole 21 and blind hole.
In conclusion the high-accuracy multilayer buried blind via wiring board of the utility model is formed by the production of process for pressing twice,
Buried via hole is made after the first first time process for pressing, then is pressed the dielectric layer of outer layer and circuit layer by second of process for pressing
In buried via hole circuit layer two sides, by mechanical holes drilled through, then carries out hole metallization and realize electrical connection, without first after every layer of punching
It is being pressed, so as to prevent panel shrinkage and interlayer from deviating the alignment accuracy of caused buried via hole or through-hole, is simplifying and beat
Hole technique improves the precision of circuit board.
The above is only the preferred embodiment of the utility model only, is not intended to limit the utility model, all at this
Made any modifications, equivalent replacements, and improvements etc., should be included in the utility model within the spirit and principle of utility model
Protection scope within.
Claims (5)
1. a kind of high-accuracy multilayer buried blind via wiring board, which is characterized in that including be cascading first circuit layer, first
Dielectric layer, the second circuit layer, second dielectric layer, tertiary circuit layer, third dielectric layer, the 4th circuit layer, the 4th dielectric layer, the 5th
Circuit layer, the 5th dielectric layer and the 6th circuit layer, the second dielectric layer are provided with the buried via hole of perforation to the 4th dielectric layer,
The inner surface of the buried via hole is coated with a layers of copper, and the second circuit layer, tertiary circuit layer, the 4th circuit layer, the 5th circuit layer are logical
It crosses the buried via hole and keeps electrical connection, the first circuit layer is provided with the through-hole of perforation to the 6th circuit, the through-hole
Inner surface is coated with a layers of copper, the first circuit layer, the second circuit layer, tertiary circuit layer, the 4th circuit layer, the 5th circuit layer,
6th circuit layer keeps electrical connection by the through-hole.
2. high-accuracy multilayer buried blind via wiring board as described in claim 1, which is characterized in that the first circuit layer is described in
First medium layer is provided with blind hole, and the inner surface of the blind hole is coated with a layers of copper, the first circuit layer and the second circuit
Layer keeps being electrically connected by the blind hole.
3. high-accuracy multilayer buried blind via wiring board as described in claim 1, which is characterized in that the 6th circuit layer is described in
5th dielectric layer is provided with blind hole, and the inner surface of the blind hole is coated with a layers of copper, the 5th circuit layer and the 6th circuit
Layer keeps being electrically connected by the blind hole.
4. high-accuracy multilayer buried blind via wiring board as described in claim 1, which is characterized in that the second circuit layer, second
Dielectric layer, tertiary circuit layer, third dielectric layer, the 4th circuit layer, the 4th dielectric layer, the 5th circuit layer are in first time process for pressing
In press together, the buried via hole is formed after first time process for pressing by machine drilling and copper-plating technique.
5. high-accuracy multilayer buried blind via wiring board as claimed in claim 4, which is characterized in that the first circuit layer, first
Dielectric layer, the 5th dielectric layer, the 6th circuit layer and the second circuit layer, second dielectric layer, tertiary circuit layer, third dielectric layer,
Four circuit layers, the 4th dielectric layer, the 5th circuit layer press together in second of process for pressing, and the through-hole is pressed at second
It is formed after closing technique by machine drilling and copper-plating technique.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
CN201820735429.9U CN208285625U (en) | 2018-05-17 | 2018-05-17 | High-accuracy multilayer buried blind via wiring board |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
CN201820735429.9U CN208285625U (en) | 2018-05-17 | 2018-05-17 | High-accuracy multilayer buried blind via wiring board |
Publications (1)
Publication Number | Publication Date |
---|---|
CN208285625U true CN208285625U (en) | 2018-12-25 |
Family
ID=64729936
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
CN201820735429.9U Active CN208285625U (en) | 2018-05-17 | 2018-05-17 | High-accuracy multilayer buried blind via wiring board |
Country Status (1)
Country | Link |
---|---|
CN (1) | CN208285625U (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN113993274A (en) * | 2021-09-27 | 2022-01-28 | 惠州Tcl移动通信有限公司 | SIP module and mobile terminal |
-
2018
- 2018-05-17 CN CN201820735429.9U patent/CN208285625U/en active Active
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN113993274A (en) * | 2021-09-27 | 2022-01-28 | 惠州Tcl移动通信有限公司 | SIP module and mobile terminal |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US8107254B2 (en) | Integrating capacitors into vias of printed circuit boards | |
US5038252A (en) | Printed circuit boards with improved electrical current control | |
EP1286579A4 (en) | Multilayer printed wiring board | |
GB1125526A (en) | Multilayer circuit boards | |
CN101389191B (en) | Multi-layer circuit board | |
KR101084250B1 (en) | Electronic Components Embedded Printed Circuit Board and Method of Manufacturing the Same | |
CN111316434A (en) | Electronic substrate with differential coaxial vias | |
CN109788663B (en) | Manufacturing method of circuit board and circuit board manufactured by same | |
CN101472403B (en) | Printed circuit board and method for producing the same | |
CN111315110A (en) | Circuit board and electronic device | |
TW200420203A (en) | Multilayer board and its manufacturing method | |
CN208285625U (en) | High-accuracy multilayer buried blind via wiring board | |
CN103052281A (en) | Embedded multilayer circuit board and manufacturing method thereof | |
CN211063845U (en) | Mechanical blind hole HDI circuit board | |
CN104302099A (en) | Circuit board and manufacturing method thereof | |
CN104125699A (en) | Printed circuit board and manufacturing method | |
CN214800022U (en) | High-precision multilayer buried blind hole circuit board | |
CN112351600A (en) | High-speed ATE test board and manufacturing method thereof | |
CN205657918U (en) | Embedded electric capacity multilayer printed board that easy metallization switched on | |
CN111787715B (en) | Method for manufacturing interconnection of inner layers of circuit board | |
CN111712066B (en) | Method for manufacturing interconnection of inner layers of circuit board | |
US11234331B2 (en) | Multilayer printed circuit board and method for manufacturing the same | |
US11122674B1 (en) | PCB with coin and dielectric layer | |
CN102686050A (en) | Blind via manufacture method of multi-layer printed circuit board | |
CN208285636U (en) | A kind of circuit board using high frequency machinery blind hole deep drilling |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
GR01 | Patent grant | ||
GR01 | Patent grant |