CN208226981U - A kind of NMOS tube protection circuit and its chip - Google Patents
A kind of NMOS tube protection circuit and its chip Download PDFInfo
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- CN208226981U CN208226981U CN201820119984.9U CN201820119984U CN208226981U CN 208226981 U CN208226981 U CN 208226981U CN 201820119984 U CN201820119984 U CN 201820119984U CN 208226981 U CN208226981 U CN 208226981U
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- 238000002955 isolation Methods 0.000 claims description 2
- 239000000126 substance Substances 0.000 claims 1
- 238000004519 manufacturing process Methods 0.000 abstract description 6
- WHXSMMKQMYFTQS-UHFFFAOYSA-N Lithium Chemical compound [Li] WHXSMMKQMYFTQS-UHFFFAOYSA-N 0.000 description 8
- 229910052744 lithium Inorganic materials 0.000 description 8
- 230000015556 catabolic process Effects 0.000 description 6
- 238000010586 diagram Methods 0.000 description 5
- 238000005516 engineering process Methods 0.000 description 5
- 230000002441 reversible effect Effects 0.000 description 3
- 230000005611 electricity Effects 0.000 description 2
- 238000000034 method Methods 0.000 description 2
- 230000024241 parasitism Effects 0.000 description 2
- 230000002159 abnormal effect Effects 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 230000005669 field effect Effects 0.000 description 1
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- 239000004065 semiconductor Substances 0.000 description 1
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Abstract
The utility model provides a kind of NMOS tube protection circuit; it include: NMOS tube NM0, NMOS tube NM3, the first ESD protective module and the 2nd ESD protective module; the drain electrode of the NMOS tube NM0 is connected with the drain electrode of the NMOS tube NM3; the source electrode and grid of the NMOS tube NM0 is connected with the first ESD protective module respectively, and the source electrode and grid of the NMOS tube NM3 is connected with the 2nd ESD protective module respectively.The utility model is by increasing the first ESD protective module to NMOS tube NM0; 2nd ESD protective module is increased to NMOS tube NM3; and then strengthen the ESD protective value of the grid of NMOS tube NM0 and NMOS tube NM3; reinforce the ESD protective value of the NMOS tube chip including NMOS tube protection circuit; meets the needs of production, at low cost and performance is excellent.
Description
Technical field
The utility model relates to a kind of protection circuits more particularly to a kind of NMOS tube to protect circuit, and be related to including this
The NMOS tube chip of NMOS tube protection circuit.
Background technique
Independent MOS chip on the market mostly uses greatly the structure of VDMOS at present, and VDMOS is vertical double diffused metal-oxidation
Object semiconductor field effect transistor, as vertical structure, the end Source (source electrode) of VNMOS pipe is in top surface, and Drain(drains)
At bottom surface, work electric current can flowing from top to bottom, the channel of VNMOS is Gate Oxide(gate oxide) below the area P-
Domain causes channel length chip chamber to differ greatly, so the channel length of VDMOS is controlled by diffusion so as to cause NMOS
The cut-in voltage deviation of pipe is larger (changing between -1.5V ~ -3V).
This VDMOS has the advantages of bipolar transistor and common MOS device concurrently, and either switch application is still linearly answered
With VDMOS is ideal power device；But the ESD performance at the end gate (grid) of VDMOS pipe is poor, is easily damaged.
The characteristics of VDMOS, has: close to infinitely great static input impedance characteristic, very fast switch time, the positive temperature system of conducting resistance
Number, the mutual conductance of approximate constant, high dV/dt；Therefore, battery protection, the fields such as electronic switch or power management be can be widely applied for
It closes.And with the fast development of lithium battery, so that lithium electric protection circuit requirements is increased severely, wherein 8205 chips of binary channels NMOS tube exist
It is even more to be widely used in lithium electric protection.
Wherein, the major parameter of 8205 chips of NMOS has VDS pressure resistance to reach 20V, and cut-in voltage Vgs (th) is arrived in 1.5V
Within the scope of 3V, conduction impedance Rdson is in Europe 20m or so.8205 chips are a universal NMOS in early days, are mostly applied at present
In lithium fulgurite reason, lithium battery voltage is mostly between 2.7-4.2v, and the 20V pressure resistance of 8205 chips is much larger than its operating voltage.
According to 2*VDD experience, the pressure resistance of 8205 chips, which is greater than 8.4V, can satisfy requirement；And currently used 5V CMOS technology
NMOS tube pressure resistance be generally higher than 11V, be greater than lithium electricity battery pressure resistance demand, therefore, the present NMOS tube that is unable to fully meets life
The demand of production, meanwhile, it also cannot get good ESD protection.
Summary of the invention
Technical problem to be solved in the utility model is to need to provide a kind of ESD performance that can improve NMOS tube grid
NMOS tube protect circuit, and NMOS tube is further optimized for lateral NMOS tube, to reach optimization NMOS tube chip, reduced
The purpose of cost and guarantee production capacity supply.
In this regard, the utility model provides a kind of NMOS tube protection circuit, comprising: NMOS tube NM0, NMOS tube NM3, first
The drain electrode of ESD protective module and the 2nd ESD protective module, the NMOS tube NM0 is connected with the drain electrode of the NMOS tube NM3,
The source electrode and grid of the NMOS tube NM0 is connected with the first ESD protective module respectively, the source electrode of the NMOS tube NM3
It is connected respectively with the 2nd ESD protective module with grid.
Further improvement of the utility model is that the first ESD protective module includes NMOS tube NM1, NMOS tube NM2
With NMOS tube NM6, the source electrode of the NMOS tube NM1 is connected with the source electrode of the NMOS tube NM2, the leakage of the NMOS tube NM1
Pole is connected with the grid of the NMOS tube NM0, and the drain electrode of the NMOS tube NM2 is connected with the source electrode of the NMOS tube NM0,
The grid of the grid of the NMOS tube NM1 and the NMOS tube NM2 are connected to the drain electrode of the NMOS tube NM6, the NMOS tube
The grid and source electrode of NM6 is connected to wafer substrate；The source electrode, described of the source electrode of the NMOS tube NM1, the NMOS tube NM2
The drain electrode of the grid of NMOS tube NM1, the grid of the NMOS tube NM2 and the NMOS tube NM6 is both connected to together.
Further improvement of the utility model is that the NMOS tube NM0 includes parasitic diode D0, parasitic two pole
The anode of pipe D0 is connected to the source electrode of the NMOS tube NM0, and the cathode of the parasitic diode D0 is connected to the NMOS tube NM0
Drain electrode.
Further improvement of the utility model is that the NMOS tube NM1 includes parasitic diode D1, parasitic two pole
The anode of pipe D1 is connected to the source electrode of the NMOS tube NM1, and the cathode of the parasitic diode D1 is connected to the NMOS tube NM1
Drain electrode；The NMOS tube NM2 includes parasitic diode D2, and the anode of the parasitic diode D2 is connected to the NMOS tube
The source electrode of NM2, the cathode of the parasitic diode D2 are connected to the drain electrode of the NMOS tube NM2；The NMOS tube NM6 includes posting
Raw diode D6, the anode of the parasitic diode D6 are connected to the source electrode of the NMOS tube NM6, the parasitic diode D6's
Cathode is connected to the drain electrode of the NMOS tube NM6.
Further improvement of the utility model is that the 2nd ESD protective module includes NMOS tube NM4, NMOS tube NM5
With NMOS tube NM7, the source electrode of the NMOS tube NM4 is connected with the source electrode of the NMOS tube NM5, the leakage of the NMOS tube NM4
Pole is connected with the grid of the NMOS tube NM3, and the drain electrode of the NMOS tube NM5 is connected with the source electrode of the NMOS tube NM3,
The grid of the grid of the NMOS tube NM4 and the NMOS tube NM5 are connected to the drain electrode of the NMOS tube NM7, the NMOS tube
The grid and source electrode of NM7 is connected to wafer substrate；The source electrode, described of the source electrode of the NMOS tube NM4, the NMOS tube NM5
The drain electrode of the grid of NMOS tube NM4, the grid of the NMOS tube NM5 and the NMOS tube NM7 is both connected to together.
Further improvement of the utility model is that the NMOS tube NM3 includes parasitic diode D3, parasitic two pole
The anode of pipe D3 is connected to the source electrode of the NMOS tube NM3, and the cathode of the parasitic diode D3 is connected to the NMOS tube NM3
Drain electrode.
Further improvement of the utility model is that the NMOS tube NM4 includes parasitic diode D4, parasitic two pole
The anode of pipe D4 is connected to the source electrode of the NMOS tube NM4, and the cathode of the parasitic diode D4 is connected to the NMOS tube NM4
Drain electrode；The NMOS tube NM5 includes parasitic diode D5, and the anode of the parasitic diode D5 is connected to the NMOS tube
The source electrode of NM5, the cathode of the parasitic diode D5 are connected to the drain electrode of the NMOS tube NM5；The NMOS tube NM7 includes posting
Raw diode D7, the anode of the parasitic diode D7 are connected to the source electrode of the NMOS tube NM7, the parasitic diode D7's
Cathode is connected to the drain electrode of the NMOS tube NM7.
Further improvement of the utility model is that the source electrode and drain electrode of the NMOS tube NM0 is respectively arranged at the NMOS
Setting is isolated with wafer substrate by N well layer for the substrate of the left and right sides of the grid of pipe NM0, the NMOS tube.
Further improvement of the utility model is that the source electrode and drain electrode of the NMOS tube NM3 is respectively arranged at the NMOS
The left and right sides of the grid of pipe NM3.
The utility model also provides a kind of NMOS tube chip, includes NMOS tube protection circuit as described above.
Compared with prior art, the utility model has the beneficial effects that: by increasing the first ESD to NMOS tube NM0
Protective module increases the 2nd ESD protective module to NMOS tube NM3, strengthens the grid of NMOS tube NM0 and NMOS tube NM3
ESD protective value, and then reinforce the ESD protective value of the NMOS tube chip including NMOS tube protection circuit, meet production
Demand；Also, further the NMOS tube can also be optimized for lateral NMOS tube, and then it is low and inclined to have cut-in voltage
The small advantage of difference, has achieved the purpose that at low cost and performance is excellent.
Detailed description of the invention
Fig. 1 is a kind of circuit theory schematic diagram of embodiment of the utility model；
Fig. 2 is a kind of circuit diagram of embodiment of the utility model；
Fig. 3 is a kind of detailed circuit schematic diagram of embodiment of the utility model；
Fig. 4 is a kind of the schematic diagram of the section structure of the NMOS tube of embodiment of the utility model.
Specific embodiment
With reference to the accompanying drawing, the preferably embodiment of the utility model is described in further detail.
As shown in Figure 1, this example provides a kind of NMOS tube protection circuit, comprising: NMOS tube NM0, NMOS tube NM3, the first ESD
The drain electrode of protective module 1 and the 2nd ESD protective module 2, the NMOS tube NM0 is connected with the drain electrode of the NMOS tube NM3, institute
The source electrode and grid for stating NMOS tube NM0 are connected with the first ESD protective module 1 respectively, the source electrode of the NMOS tube NM3 and
Grid is connected with the 2nd ESD protective module 2 respectively.
This example increases the first ESD protective module 1 and the 2nd ESD protective module 2 the two ESD protective modules, reinforces
The ESD protective value of the grid G 2 of the grid (G1) and NMOS tube NM3 of NMOS tube NM0, strengthens the protectiveness of NMOS tube chip
Energy.
As shown in Fig. 2, the first ESD protective module 1 described in this example includes NMOS tube NM1, NMOS tube NM2 and NMOS tube NM6,
The source electrode of the NMOS tube NM1 is connected with the source electrode of the NMOS tube NM2, the drain electrode of the NMOS tube NM1 and the NMOS
The grid of pipe NM0 is connected, and the drain electrode of the NMOS tube NM2 is connected with the source electrode of the NMOS tube NM0, the NMOS tube
The grid of the grid of NM1 and the NMOS tube NM2 are connected to the drain electrode of the NMOS tube NM6, the grid of the NMOS tube NM6 and
Source electrode is connected to wafer substrate；The source electrode of the NMOS tube NM1, the source electrode of the NMOS tube NM2, the NMOS tube NM1
The drain electrode of grid, the grid of the NMOS tube NM2 and the NMOS tube NM6 is both connected to together.
2nd ESD protective module 2 described in this example includes NMOS tube NM4, NMOS tube NM5 and NMOS tube NM7, the NMOS tube
The source electrode of NM4 is connected with the source electrode of the NMOS tube NM5, the drain electrode of the NMOS tube NM4 and the grid of the NMOS tube NM3
It is connected, the drain electrode of the NMOS tube NM5 is connected with the source electrode of the NMOS tube NM3, the grid of the NMOS tube NM4 and institute
The grid for stating NMOS tube NM5 is connected to the drain electrode of the NMOS tube NM7, and the grid and source electrode of the NMOS tube NM7 is connected to
Wafer substrate；The source electrode of the NMOS tube NM4, the source electrode of the NMOS tube NM5, the grid of the NMOS tube NM4, the NMOS
The drain electrode of the grid of pipe NM5 and the NMOS tube NM7 are both connected to together.
Wherein, NMOS tube NM0 and NMOS tube NM3 is area very high power tube, NMOS tube NM1, NMOS tube NM2 and NMOS tube
NM6 connects and composes the first esd protection circuit ESD module 1 of this power tube of NMOS tube NM0, NMOS tube NM4, NMOS tube NM5 and
NMOS tube NM7 connects and composes the 2nd ESD protective module 2 of this power tube of NMOS tube NM3.Its working principle is that chip is being deposited
The links such as storage, transport and processing can generate electrostatic charge, which can generate extra-high voltage (a few kilovolts) at pin, breakdown half
Conductor device.If G1(or G2 in Fig. 2) there are electrostatic charge, the G1(or G2 of 8205 chips of traditional VDMOS structure) do not have
Have discharge path, electrostatic charge can be accumulated in G1(or G2) end, it generates high pressure and damages VDMOS device.
And shown in Fig. 2 is NMOS chip corresponding circuit diagram of this example added with esd protection circuit, G1(or G2)
Electrostatic charge can pass through NMOS tube NM1 and NMOS tube NM2(or NMOS tube NM4 and NMOS tube NM5) ESD device flow to the end S1
(source electrode of NMOS tube NM0) and the end D (drain electrode of NMOS tube NM0), electrostatic charge is released, to reach the end Gate (grid)
ESD protects purpose.
The not no esd protection circuit of existing VDMOS, causes the ESD performance of the G1 and G2 of existing 8205 chip poor,
Common esd protection circuit is the NMOS tube that gate connects GND connection.And the NMOS tube using back-to-back connection of this example novelty
NM1 and NMOS tube NM2 pipe, as shown in Fig. 2, the first ESD protective module 1 that NMOS tube NM1 described in this example and NMOS tube NM2 is formed
Both it is not breakdown to have can protect the end G1, while G1 and S1 also being made to form isolation, has prevented NMOS tube NM1 or NMOS in normal work
Pipe NM2 conducting, influences working performance.The also innovative introducing NMOS tube NM6 of this example and NMOS tube NM7 pipe simultaneously, due to this example
Using isolated form NMOS tube, the P_sub of chip is floating state, and P_sub is wafer substrate, by introducing NMOS tube NM6
With NMOS tube NM7, by the clamping of wafer substrate P_sub to the minimum level of A and B point, while guaranteeing wafer substrate P_sub
It can be synchronized with A/B node, the wafer substrate P_sub of floating state can be effectively prevent to generate abnormal level.
As shown in figure 3, NMOS tube NM0 described in this example includes parasitic diode D0, the anode of the parasitic diode D0 connects
It is connected to the source electrode of the NMOS tube NM0, the cathode of the parasitic diode D0 is connected to the drain electrode of the NMOS tube NM0.It is described
NMOS tube NM1 includes parasitic diode D1, and the anode of the parasitic diode D1 is connected to the source electrode of the NMOS tube NM1, institute
The cathode for stating parasitic diode D1 is connected to the drain electrode of the NMOS tube NM1；The NMOS tube NM2 includes parasitic diode D2,
The anode of the parasitic diode D2 is connected to the source electrode of the NMOS tube NM2, and the cathode of the parasitic diode D2 is connected to
The drain electrode of the NMOS tube NM2；The NMOS tube NM6 includes parasitic diode D6, the anode connection of the parasitic diode D6
To the source electrode of the NMOS tube NM6, the cathode of the parasitic diode D6 is connected to the drain electrode of the NMOS tube NM6.
Likewise, as shown in figure 3, NMOS tube NM3 described in this example includes parasitic diode D3, the parasitic diode D3's
Anode is connected to the source electrode of the NMOS tube NM3, and the cathode of the parasitic diode D3 is connected to the leakage of the NMOS tube NM3
Pole.The NMOS tube NM4 includes parasitic diode D4, and the anode of the parasitic diode D4 is connected to the NMOS tube NM4's
Source electrode, the cathode of the parasitic diode D4 are connected to the drain electrode of the NMOS tube NM4；The NMOS tube NM5 includes parasitism two
Pole pipe D5, the anode of the parasitic diode D5 are connected to the source electrode of the NMOS tube NM5, the cathode of the parasitic diode D5
It is connected to the drain electrode of the NMOS tube NM5；The NMOS tube NM7 includes parasitic diode D7, the sun of the parasitic diode D7
Pole is connected to the source electrode of the NMOS tube NM7, and the cathode of the parasitic diode D7 is connected to the drain electrode of the NMOS tube NM7.
When the G1 of Fig. 3 is there are when electrostatic charge, the end G1 (grid) electrostatic charge can generate high voltage pressure breakdown parasitic diode
The breakdown reverse voltage of D1, parasitic diode D1 can be lower than G1 grid damage voltage, and electrostatic charge can flow through reverse breakdown parasitism two
Then pole pipe D1 flows to the end S1 (source electrode) by parasitic diode D2 forward, or pass through parasitic diode D0 forward again
Flow to the end D (drain electrode).To the end G1 (grid) electrostatic charge of releasing, the electrostatic charges accumulated damage G1(grid at the end G1 (grid) are prevented
Pole).Since electrostatic charge transient energy is smaller, in parasitic diode D1 can be in tolerance range, so parasitic diode D1 is short
In time then reverse breakdown restores, and parasitic diode D1 will not be damaged, and realizes ESD defencive function.G2(grid) etc. other
The ESD protection philosophy of port is protected with the ESD at the above-mentioned end G1 (grid).
Wherein the back-to-back connection of NMOS tube NM1 and NMOS tube NM2 can obtain parasitic diode D1 as shown in Figure 3 and post
Raw diode D2 is also back-to-back connection relationship, and the parasitic diode NM1 and parasitic diode NM2 of the back-to-back connection make G1
(grid) and S1(source electrode) no matter positive inverted signal can all have a reversed diode, prevent G1(grid) and S1(source electrode)
There are current paths when work, influence the normal work of parasitic diode NM0.Such as G1(grid) be high level, S1(source electrode) be
When low level, the reversed stopping of parasitic diode D1, parasitic diode D2 does not work forward.Such as G1(grid) it is low electricity
Flat, S1(source electrode) when being high level, the reversed stopping of parasitic diode D2, parasitic diode D1 does not work forward.So
The ESD structure not only may be implemented to improve G1(or G2) end ESD performance while, but also will not influence NMOS tube NM0(or NMOS tube
NM3 the normal work of power tube).
As shown in figure 4, the source electrode and drain electrode of NMOS tube NM0 described in this example is respectively arranged at the grid of NMOS tube NM0
Setting is isolated with wafer substrate by N well layer for the substrate of the left and right sides, the NMOS tube.Likewise, NMOS tube NM3 described in this example
Source electrode and drain electrode be respectively arranged at NMOS tube NM3 grid the left and right sides.
Therefore, as shown in figure 4, NMOS tube NM0 and NMOS tube NM3 described in this example are to be produced using mainstream CMOS processes
The structure of the NMOS sectional view of isolated form, NMOS tube NM0 and NMOS tube NM3 are transverse structure, and the NMOS tube of isolated form is
The substrate (PW) of NMOS tube and wafer substrate (P_sub) are kept apart by N well layer (Deep NW), wherein the PW of Fig. 4 is NMOS
The substrate of pipe, P_sub are wafer substrates.The source electrode (Source) of NMOS tube and drain electrode (Drain) are in the left and right of grid (Gate)
Both sides, electric current lateral flow when work.Since the CMOS technology of mainstream is all using self-registered technology, the channel length of NMOS tube
It is determined by the width of Gate Oxide.And the width of the Gate Oxide of CMOS technology can accomplish 0.5uM, and can be accurate
Control, thus CMOS technology production NMOS tube cut-in voltage it is all smaller (between -0.8V ~ -1V), and variation range compared with
It is small.The feature is suitble to lithium battery switch driving, because lithium battery voltage is 2.7V-4.2V variation.
This example also provides a kind of NMOS tube chip, includes NMOS tube protection circuit as described above, that is to say, that will scheme
1 is encapsulated to any one circuit theory shown in Fig. 3, is exactly improved 8205 chip, than existing 8205 chip
Can be more excellent, and cost is reasonable.
To sum up, this example increases second to NMOS tube NM3 by increasing the first ESD protective module 1 to NMOS tube NM0
ESD protective module 2 strengthens the ESD protective value of the grid of NMOS tube NM0 and NMOS tube NM3, and then reinforces including the NMOS
The ESD protective value of the NMOS tube chip of tube protective circuit, meets the needs of production；Also, can also further, it will be described
NMOS tube is optimized for lateral NMOS tube, and then has that cut-in voltage is low and the small advantage of deviation, has reached at low cost and performance is excellent
Purpose.
The specific embodiment of the above is the better embodiment of the utility model, and it is practical new not to limit this with this
The specific implementation range of type, the scope of the utility model includes being not limited to present embodiment, all according to the utility model
Shape, structure made by equivalence changes it is within the protection scope of the present utility model.
Claims (8)
1. a kind of NMOS tube protects circuit characterized by comprising NMOS tube NM0, NMOS tube NM3, the first ESD protective module
Drain electrode with the 2nd ESD protective module, the NMOS tube NM0 is connected with the drain electrode of the NMOS tube NM3, the NMOS tube
The source electrode and grid of NM0 is connected with the first ESD protective module respectively, source electrode and the grid difference of the NMOS tube NM3
It is connected with the 2nd ESD protective module；
The first ESD protective module includes NMOS tube NM1, NMOS tube NM2 and NMOS tube NM6, the source electrode of the NMOS tube NM1
It is connected with the source electrode of the NMOS tube NM2, the drain electrode of the NMOS tube NM1 is connected with the grid of the NMOS tube NM0, institute
The drain electrode for stating NMOS tube NM2 is connected with the source electrode of the NMOS tube NM0, the grid of the NMOS tube NM1 and the NMOS tube
The grid of NM2 is connected to the drain electrode of the NMOS tube NM6, and the grid and source electrode of the NMOS tube NM6 is connected to wafer substrate；
The source electrode of the NMOS tube NM1, the source electrode of the NMOS tube NM2, the grid of the NMOS tube NM1, the NMOS tube NM2 grid
The drain electrode of pole and the NMOS tube NM6 are both connected to together；
The 2nd ESD protective module includes NMOS tube NM4, NMOS tube NM5 and NMOS tube NM7, the source electrode of the NMOS tube NM4
It is connected with the source electrode of the NMOS tube NM5, the drain electrode of the NMOS tube NM4 is connected with the grid of the NMOS tube NM3, institute
The drain electrode for stating NMOS tube NM5 is connected with the source electrode of the NMOS tube NM3, the grid of the NMOS tube NM4 and the NMOS tube
The grid of NM5 is connected to the drain electrode of the NMOS tube NM7, and the grid and source electrode of the NMOS tube NM7 is connected to wafer substrate；
The source electrode of the NMOS tube NM4, the source electrode of the NMOS tube NM5, the grid of the NMOS tube NM4, the NMOS tube NM5 grid
The drain electrode of pole and the NMOS tube NM7 are both connected to together.
2. NMOS tube according to claim 1 protects circuit, which is characterized in that the NMOS tube NM0 includes parasitic two poles
Pipe D0, the anode of the parasitic diode D0 are connected to the source electrode of the NMOS tube NM0, and the cathode of the parasitic diode D0 connects
It is connected to the drain electrode of the NMOS tube NM0.
3. NMOS tube according to claim 1 protects circuit, which is characterized in that the NMOS tube NM1 includes parasitic two poles
Pipe D1, the anode of the parasitic diode D1 are connected to the source electrode of the NMOS tube NM1, and the cathode of the parasitic diode D1 connects
It is connected to the drain electrode of the NMOS tube NM1；The NMOS tube NM2 includes parasitic diode D2, the anode of the parasitic diode D2
It is connected to the source electrode of the NMOS tube NM2, the cathode of the parasitic diode D2 is connected to the drain electrode of the NMOS tube NM2；Institute
Stating NMOS tube NM6 includes parasitic diode D6, and the anode of the parasitic diode D6 is connected to the source electrode of the NMOS tube NM6,
The cathode of the parasitic diode D6 is connected to the drain electrode of the NMOS tube NM6.
4. protecting circuit to NMOS tube described in 3 any one according to claim 1, which is characterized in that the NMOS tube NM3 packet
Parasitic diode D3 is included, the anode of the parasitic diode D3 is connected to the source electrode of the NMOS tube NM3, the parasitic diode
The cathode of D3 is connected to the drain electrode of the NMOS tube NM3.
5. NMOS tube according to claim 1 protects circuit, which is characterized in that the NMOS tube NM4 includes parasitic two poles
Pipe D4, the anode of the parasitic diode D4 are connected to the source electrode of the NMOS tube NM4, and the cathode of the parasitic diode D4 connects
It is connected to the drain electrode of the NMOS tube NM4；The NMOS tube NM5 includes parasitic diode D5, the anode of the parasitic diode D5
It is connected to the source electrode of the NMOS tube NM5, the cathode of the parasitic diode D5 is connected to the drain electrode of the NMOS tube NM5；Institute
Stating NMOS tube NM7 includes parasitic diode D7, and the anode of the parasitic diode D7 is connected to the source electrode of the NMOS tube NM7,
The cathode of the parasitic diode D7 is connected to the drain electrode of the NMOS tube NM7.
6. protecting circuit to NMOS tube described in 3 any one according to claim 1, which is characterized in that the NMOS tube NM0's
Source electrode and drain electrode is respectively arranged at the left and right sides of the grid of NMOS tube NM0, and the substrate of the NMOS tube passes through N well layer and crystalline substance
Circle substrate isolation setting.
7. NMOS tube according to claim 6 protects circuit, which is characterized in that the source electrode and drain electrode of the NMOS tube NM3
It is respectively arranged at the left and right sides of the grid of NMOS tube NM3.
8. a kind of NMOS tube chip, which is characterized in that include NMOS tube protection as claimed in any one of claims 1 to 7
Circuit.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201820119984.9U CN208226981U (en) | 2018-01-24 | 2018-01-24 | A kind of NMOS tube protection circuit and its chip |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201820119984.9U CN208226981U (en) | 2018-01-24 | 2018-01-24 | A kind of NMOS tube protection circuit and its chip |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN208226981U true CN208226981U (en) | 2018-12-11 |
Family
ID=64533470
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201820119984.9U Active CN208226981U (en) | 2018-01-24 | 2018-01-24 | A kind of NMOS tube protection circuit and its chip |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN208226981U (en) |
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2018
- 2018-01-24 CN CN201820119984.9U patent/CN208226981U/en active Active
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