CN208226553U - A kind of thermal-shutdown circuit - Google Patents
A kind of thermal-shutdown circuit Download PDFInfo
- Publication number
- CN208226553U CN208226553U CN201820716676.4U CN201820716676U CN208226553U CN 208226553 U CN208226553 U CN 208226553U CN 201820716676 U CN201820716676 U CN 201820716676U CN 208226553 U CN208226553 U CN 208226553U
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- CN
- China
- Prior art keywords
- tube
- nmos tube
- pmos tube
- nmos
- pmos
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
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Abstract
The utility model discloses a kind of thermal-shutdown circuits, including the first NMOS tube, the second NMOS tube, third NMOS tube, the 4th NMOS tube, the 5th NMOS tube, the first PMOS tube, the second PMOS tube, third PMOS tube, the 4th PMOS tube, the 5th PMOS tube, the first current source, the second current source and the first triode；The utility model provides a kind of thermal-shutdown circuit; it realizes when chip temperature is more than set temperature; control chip enters overheat protector state; simultaneously; third PMOS tube, the 4th PMOS tube, the second NMOS tube, third NMOS tube and the 5th NMOS tube realize lag function, avoid circuit that thermal oscillation occurs near excess temperature temperature spot.
Description
Technical field
The invention belongs to integrated circuit fields, are related to a kind of thermal-shutdown circuit.
Background technique
Currently, in integrated circuits, chip can be inevitably generated power dissipation at work, so that the temperature of chip
It increases.When chip temperature is excessively high, can stability, reliability to chip cause to damage, therefore thermal-shutdown circuit have weight
The meaning wanted.
Summary of the invention
The purpose of the present invention is to provide a kind of thermal-shutdown circuits, and realize the control when chip temperature is higher than setting
Chip enters temperature protection state, and by the lag function of circuit, avoids circuit that thermal oscillation occurs near warm spot excessively.
To solve the above-mentioned problems, the present invention provides a kind of thermal-shutdown circuit, including the first NMOS tube, the 2nd NMOS
Pipe, third NMOS tube, the 4th NMOS tube, the 5th NMOS tube, the first PMOS tube, the second PMOS tube, third PMOS tube, the 4th PMOS
Pipe, the 5th PMOS tube, the first current source, the second current source and the first triode；
The source electrode of first PMOS tube, the source electrode of the second PMOS tube, the source electrode of third PMOS tube, the 4th PMOS tube source
The source electrode of pole and the 5th PMOS tube is connected with supply voltage；The base area of first triode, the first triode current collection
Pole, the source electrode of the first NMOS tube, the source electrode of the second NMOS tube, the source electrode of third NMOS tube, the 4th NMOS tube source electrode and the 5th
The source electrode of NMOS tube is equably connected；One end of second current source is connected to the ground, the other end and the first PMOS tube
The drain electrode of grid, the first PMOS tube is connected with the grid of the second PMOS tube, the drain electrode of the second PMOS tube, the leakage of the first NMOS tube
The grid of pole, the grid of third PMOS tube and the second NMOS tube is connected to point B, the grid of the first NMOS tube, the first current source
The collector of one end and the first triode is connected to point A, the drain electrode of third PMOS tube, the drain electrode of the second NMOS tube, the 5th NMOS
The grid of the drain electrode of pipe, the grid of the 4th PMOS tube and third NMOS tube is connected to point C, the drain electrode of the 4th PMOS tube, third
The drain electrode of NMOS pipe, the grid of the 5th NMOS tube, the grid of the 5th PMOS tube and the grid of the 4th NMOS tube are connected to point D, the
The drain electrode of five PMOS tube and the drain electrode of the 4th NMOS tube are connected to point Y.
First triode is lateral PNP triode, can be integrated in CMOS technology, and circuit passes through the second current source of selection
Warm spot was arranged in size.Third PMOS tube, the 4th PMOS tube, the second NMOS tube, third NMOS tube and the 5th NMOS tube are realized slow
Stagnant function avoids circuit that thermal oscillation occurs near excess temperature temperature spot.
The invention has the advantages that the electricity of the second current source of selection can be passed through in thermal-shutdown circuit in the present invention
It flows size and excess temperature temperature spot is set, realize that, when chip temperature is higher than setting, control chip enters temperature protection state, while the
Three PMOS tube, the 4th PMOS tube, the second NMOS tube, the 3rd NMOS pipe and the 5th NMOS tube realize that lag function realizes sluggish function
Can, avoid circuit that thermal oscillation occurs near excess temperature temperature spot.
Detailed description of the invention
Fig. 1 is circuit diagram of the invention；
Specific embodiment
Present invention will be further explained below with reference to the attached drawings and examples.Following embodiment is descriptive, is not limit
Qualitatively, this does not limit the scope of protection of the present invention.
As shown in Figure 1, including the first NMOS tube, the second NMOS tube, third NMOS tube, the 4th NMOS pipe, the 5th NMOS
Pipe, the first PMOS tube, the second PMOS tube, third PMOS tube, the 4th PMOS pipe, the 5th PMOS tube, the first current source, the second electricity
Stream source and the first triode；
The source electrode of first PMOS tube, the source electrode of the second PMOS tube, the source electrode of third PMOS tube, the 4th PMOS tube source
The source electrode of pole and the 5th PMOS tube is connected with supply voltage；The base area of first triode, the first triode current collection
Pole, the source electrode of the first NMOS tube, the source electrode of the second NMOS tube, the source electrode of third NMOS tube, the 4th NMOS tube source electrode and the 5th
The source electrode of NMOS tube is equably connected；One end of second current source is connected to the ground, the other end and the first PMOS tube
The drain electrode of grid, the first PMOS tube is connected with the grid of the second PMOS tube, the drain electrode of the second PMOS tube, the leakage of the first NMOS tube
The grid of pole, the grid of third PMOS tube and the second NMOS tube is connected to point B, the grid of the first NMOS tube, the first current source
The collector of one end and the first triode is connected to point A, the drain electrode of third PMOS tube, the drain electrode of the second NMOS tube, the 5th NMOS
The grid of the drain electrode of pipe, the grid of the 4th PMOS tube and third NMOS tube is connected to point C, the drain electrode of the 4th PMOS tube, third
The drain electrode of NMOS pipe, the grid of the 5th NMOS tube, the grid of the 5th PMOS tube and the grid of the 4th NMOS tube are connected to point D, the
The drain electrode of five PMOS tube and the drain electrode of the 4th NMOS tube are connected to point Y.
First triode is lateral PNP triode, can be integrated in CMOS technology, and circuit passes through the second current source of selection
Warm spot was arranged in size.Third PMOS tube, the 4th PMOS tube, the second NMOS tube, third NMOS tube and the 5th NMOS tube are realized slow
Stagnant function avoids circuit that thermal oscillation occurs near excess temperature temperature spot.
Since the base stage of triode, collector voltage difference are negative temperaturecoefficient voltage, when the temperature increases, A point voltage meeting
It reduces, the gate source voltage of NM1 can reduce, so that the leakage current of the first NMOS tube reduces, B point voltage can be above-mentioned, when temperature continues
Rise, when reaching overheat protector point, the leakage current that the first NMOS tube generates is less than the electric current that the second current source is arranged, B point at this time
Voltage rises to high level, and C point voltage is low level, and D point voltage is high level, and Y point voltage is low level, the control of Y point voltage
Chip enters overheat protector state, realizes overheat protector function.Since D point is high level, the 5th NMOS tube is in full
And state, the leakage current that the 5th NMOS tube generates increases the pull-down current of C point, when chip enters overheat protector state, chip
Temperature reduces, and B point voltage can reduce, and the leakage current that third PMOS tube generates increases, and the electric current of the second NMOS tube reduces, and works as third
The leakage current that PMOS tube generates is greater than the leakage current that the second NMOS tube generates and the sum of the leakage current that the 5th NMOS tube generates, C point
It can be just increased to high level, D point voltage is low level at this time, and Y point voltage is high level, and chip exits overheat protector state, by
In the addition that the 5th NMOS is closed, lag function is realized, circuit is avoided and is crossing warm spot generation thermal oscillation.
It is described the invention in detail above in conjunction with attached drawing, but the present invention is not limited solely to above-mentioned specific embodiment party
Formula, those skilled in the art can also make without departing from the purpose of the present invention according to the knowledge having
Various change.
Claims (4)
1. a kind of thermal-shutdown circuit, it is characterised in that including the first NMOS tube, the second NMOS tube, third NMOS tube, the 4th
NMOS tube, the 5th NMOS tube, the first PMOS tube, the second PMOS tube, third PMOS tube, the 4th PMOS tube, the 5th PMOS tube, first
Current source, the second current source and the first triode；
The source electrode of first PMOS tube, the source electrode of the second PMOS tube, the source electrode of third PMOS tube, the 4th PMOS tube source electrode and
The source electrode of 5th PMOS tube is connected with supply voltage；The base area of first triode, the collector of the first triode,
The source electrode of one NMOS tube, the source electrode of the second NMOS tube, the source electrode of third NMOS tube, the source electrode of the 4th NMOS tube and the 5th NMOS tube
Source electrode be equably connected；One end of second current source is connected to the ground, the grid of the other end and the first PMOS tube,
The drain electrode of one PMOS tube is connected with the grid of the second PMOS tube, the drain electrode of the second PMOS tube, the drain electrode of the first NMOS tube, third
The grid of PMOS tube and the grid of the second NMOS tube are connected to point B, the grid of the first NMOS tube, one end of the first current source and
The collector of one triode is connected to point A, the drain electrode of third PMOS tube, the drain electrode of the second NMOS tube, the drain electrode of the 5th NMOS tube,
The grid of 4th PMOS tube is connected with the grid of third NMOS tube, the drain electrode of the 4th PMOS tube, the drain electrode of third NMOS tube,
The grid of the grid of five NMOS tubes, the grid of the 5th PMOS tube and the 4th NMOS tube is connected, the drain electrode of the 5th PMOS tube and
The drain electrode of four NMOS tubes is connected.
2. thermal-shutdown circuit according to claim 1, it is characterised in that: the third PMOS tube, the 4th PMOS tube, second
NMOS tube, third NMOS tube and the 5th NMOS tube realize lag function, avoid circuit that thermal oscillation occurs near excess temperature temperature spot.
3. thermal-shutdown circuit according to claim 1, it is characterised in that: by selecting the size of the second current source to be arranged
Warm temperature spot.
4. thermal-shutdown circuit according to claim 1, it is characterised in that: first triode is PNP triode, is used for
Detection chip temperature.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201820716676.4U CN208226553U (en) | 2018-05-15 | 2018-05-15 | A kind of thermal-shutdown circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201820716676.4U CN208226553U (en) | 2018-05-15 | 2018-05-15 | A kind of thermal-shutdown circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN208226553U true CN208226553U (en) | 2018-12-11 |
Family
ID=64508434
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201820716676.4U Expired - Fee Related CN208226553U (en) | 2018-05-15 | 2018-05-15 | A kind of thermal-shutdown circuit |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN208226553U (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN114185387A (en) * | 2021-10-25 | 2022-03-15 | 西安电子科技大学芜湖研究院 | Low-power-consumption over-temperature protection circuit based on current comparator |
-
2018
- 2018-05-15 CN CN201820716676.4U patent/CN208226553U/en not_active Expired - Fee Related
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN114185387A (en) * | 2021-10-25 | 2022-03-15 | 西安电子科技大学芜湖研究院 | Low-power-consumption over-temperature protection circuit based on current comparator |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| GR01 | Patent grant | ||
| GR01 | Patent grant | ||
| CF01 | Termination of patent right due to non-payment of annual fee | ||
| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20181211 Termination date: 20190515 |