CN102231518B - Surging suppression circuit - Google Patents

Surging suppression circuit Download PDF

Info

Publication number
CN102231518B
CN102231518B CN 201110156185 CN201110156185A CN102231518B CN 102231518 B CN102231518 B CN 102231518B CN 201110156185 CN201110156185 CN 201110156185 CN 201110156185 A CN201110156185 A CN 201110156185A CN 102231518 B CN102231518 B CN 102231518B
Authority
CN
China
Prior art keywords
transistor
connected
resistor
positive
fet
Prior art date
Application number
CN 201110156185
Other languages
Chinese (zh)
Other versions
CN102231518A (en
Inventor
王保均
Original Assignee
广州金升阳科技有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 广州金升阳科技有限公司 filed Critical 广州金升阳科技有限公司
Priority to CN 201110156185 priority Critical patent/CN102231518B/en
Publication of CN102231518A publication Critical patent/CN102231518A/en
Application granted granted Critical
Publication of CN102231518B publication Critical patent/CN102231518B/en

Links

Abstract

本发明公开了一种浪涌抑制电路,包括输入电源正负输入端、输出电源正负输出端、场效应管、第二晶体管、第三晶体管、电容、第一电阻、第二电阻及第三电阻,所述正输入端连接正输出端,所述正输入端通过所述的第三电阻后分别与所述的场效应管的栅极及所述的第三晶体管的集电极连接,所述的正输入端经所述的电容连接至所述的场效应管漏极,所述场效应管的漏极还与负输出端连接,所述负输入端通过所述的第一电阻与所述的场效应管源极相连,所述的第三晶体管的基极连接场效应管的源极,所述的第二晶体管的基极通过所述的第二电阻接负输出端,所述第三晶体管的发射极连接所述的第二晶体管的集电极,所述第二晶体管的发射极连接负输入端。 The present invention discloses a surge suppression circuit comprising positive and negative input terminal of the input power, output power supply negative output terminal, the field effect transistor, the second transistor, a third transistor, a capacitor, a first resistor, a second resistor and a third resistance, the positive input terminal connected to the positive output terminal, said positive input connected to the collector of the gates of the field effect transistor through the rear end of said third resistor and said third transistor, said the positive input terminal connected to the capacitor via the drain of the FET, the drain of the FET is also connected to the negative output terminal of the first resistor and the negative input terminal through said connected to the source of the FET, said third transistor having a base electrode connected to the source electrode of the field effect transistor, said second transistor base of the second resistor connected to the negative output terminal through said third the collector of the second transistor is connected to the emitter of the transistor, the emitter of the second transistor is connected to the negative input terminal. 本发明可以确实有效地抑制开机时浪涌电压或电流的注入。 The present invention may be injected when a surge of voltage or current power actually effectively suppressed.

Description

—种浪涌抑制电路 - kind of surge suppression

技术领域 FIELD

[0001] 本发明涉及电源保护电路,特别涉及电容滤波电路中的浪涌抑制电路。 [0001] The present invention relates to a power supply protection circuit, and more particularly to a capacitive filter circuit surge suppression circuit.

背景技术 Background technique

[0002]目前的各种电器中,大量存在整流电路,如市电经整流、电容滤波,再给开关电源的变换电路供电;再如传统电源,市电经变压器降压后,经整流、电容滤波后给其它电路供电,这类电器在电源开关接通瞬间,由于滤波电容的存在,滤波电容两端电压瞬间从OV充电至额定工作电压,会产生很大的浪涌电压以及浪涌电流,浪涌电流不仅缩短了滤波电容的寿命,同时也对整流电路中的二极管、保险丝、电源中布线、走线都有较大的冲击。 [0002] The various current collector, there are a large number of rectifier circuits, such as rectified mains, capacitor filter, to give the switching converter power supply; Again conventional power source, electricity through the step-down transformer, the rectifier, capacitor to other circuitry, such momentary electrical power switch turned on after filtering, due to the presence of the filter capacitor, filter the instantaneous voltage across the capacitor is charged from OV to a rated working voltage, will have a great surge voltage and the surge current, surge current not only shortens the life of the filter capacitor, but also on the diode rectifier circuit, a fuse, the power supply wiring, traces have a large impact.

[0003] 传统的抑制浪涌电流的方法是在整流电路的回路中,串入合适的负温度系数的热敏电阻(NTC),热敏电阻在常态下其阻值较大,电源开关接通瞬间,热敏电阻阻值较大,限制了对电容的充电电流,从而抑制了浪涌电流,热敏电阻由于发热,其阻值因发热而减小,以减少电阻自身功耗和降低对电路效率的影响。 [0003] The conventional method of suppressing the inrush current in the loop is in the rectifier circuit, the string into a suitable negative temperature coefficient thermistor (the NTC), which is large resistance thermistor in a normal state, the power switch is turned on moment, the thermistor resistance is larger, limiting the charging current to the capacitor, so as to suppress the inrush current, the thermistor due to heat, its resistance decreases due to heat generation, in order to reduce its power consumption and reduce the resistance of the circuit affect efficiency. 这种方法简单可行,但若短时断电,由于热敏电阻冷却时间较长,在热敏电阻未冷却时,若电源开关再次接通或电路重新上电,这时产生的浪涌就会很大,热敏电阻的保护作用会下降,甚至完全失去作用。 This method is simple and feasible, but if the short-term power failure, due to the long cooling time of the thermistor, the thermistor is not cooled when, if the power switch is turned on again or re-circuit, the surge generated at this time will significant protective effect thermistor will decrease or even completely useless. 即使不短时断电,热敏电阻由于其阻值已减小,外部电源有浪涌电压产生时,热敏电阻作用极小,后续电路仍受到浪涌电压的冲击。 Even without short-term power failure, the thermistor resistance is reduced due to the external power supply is generated when the surge voltage, the thermistor acting very small, is still subject to subsequent circuits surge voltage.

[0004] 在小功率应用场合,业界经常用固定电阻代替上述的热敏电阻,固定电阻的取值成了问题,取小了,抑制效果差,取大了,发热严重,影响整机的效率,一般很难在两者之间取舍,而且,一旦电路进入稳态,这一固定电阻抑制浪涌作用已完成,在电路中,仅起发热的负面作用。 [0004] In low-power applications, the industry often replaced with a fixed resistance of the thermistor, the resistance value of the fixed into question, whichever is less, and the effect of suppressing the difference, whichever is greater, and severe fever, affecting the efficiency of the whole generally difficult to choose between the two, and, once the circuit into the steady state, the surge suppression effect of the fixed resistor has been completed, in the circuit, only play a negative role in fever.

[0005] 在现有技术中,比较有效的一种解决方法,参见图1,该电路包括电压输入端Vin-,电压输出端Vout-、M0S管Q1、三极管Q2、电容C、第一电阻R1、第二电阻R2、第三电阻R3,电压输入端Vin-分别与MOS管Ql的源极及三极管Q2的发射极连接,上述的电压输入端还通过第一电阻Rl与MOS管Ql的漏极相连,三极管Q2的集电极连接MOS管Ql的栅极并通过第三电阻R3接地,三极管Q2的基极通过第二电阻R2与MOS管Ql的漏极相连,MOS管Ql的漏极通过电容C接地,MOS管Ql的漏极还与电压输出端Vout-连接。 [0005] In the prior art, a more effective solution, 1, the circuit comprises a voltage Vin- is an input terminal, an output terminal voltage Vout-, M0S tube Q1, transistor Q2, the capacitor C, Groups resistor R1 Referring to FIG. , second resistor R2, a third resistor R3, a voltage input terminal Vin- are respectively connected to the emitter of the source of the MOS transistor Ql and the transistor Q2, the above-described drain voltage input terminal through a first resistor Rl and the MOS transistors Ql a drain connected to the collector of transistor Q2 is connected to the gate of the MOS transistor Ql is grounded through the third resistor R3, transistor Q2 is connected to the base via a second resistor R2 and the drain of the MOS transistor Ql is, the MOS transistor Ql through a capacitor C drain is grounded, MOS tube Ql is further connected to the voltage output terminal Vout-.

[0006] 上述电路还有另外一种等同变换,即将和外部电源连接的关系进行更改:把电源输入端改为外部电源地线接入,原地线改为外部电源正输入;输出地线更改为输出正,输出端口更改为输出地线;输出地线和外部电源地线是两个不同的网络。 [0006] There is another equivalent circuit of the above-described conversion, and about a change in the relationship between the external power source is connected: to the external power supply input ground access, to place an external power source positive input line; output ground changes positive output, the output port is changed to output ground; external power supply ground and the output ground are two different networks.

[0007] 上述方案的工作原理是,当Vin接外部电源时,该电源为负压,若电源开关闭合,由于电容两端电压初始为OV或较低的电压值,外部电源通过地线,经过电容C,分为两路回到Vin-,一路经过电阻Rl回到Vin-,另一路经过电阻R2以及三极管Q2的基极、发射极回到Vin-,这时三极管Q2由于基极到发射极有电流流过,三极管Q2工作,由于Ql为MOS管,其栅极偏置电阻R3取值较大,一般在MΩ级左右,三极管Q2的集电极负载R3由于取值大,三极管Q2直接进入饱和工作状态,使得N沟道MOS管Ql的栅级到源极的电压很低,为三极管Q2的饱和压降,一般为0.7V至0.1V之间,这个电压达不到N沟道MOS管Ql的开启电压,MOS管Ql处于关断状态。 Working Principle [0007] The above-described embodiment is connected to an external power source when the Vin, the power is negative, if the power switch is closed, the voltage across the capacitor due to the initial voltage value OV or lower, the external power supply through the ground, through capacitance C, Back Vin- is divided into two, all the way back through the resistor Rl Vin- is, the other way through the resistor R2 and the base of transistor Q2, emitter back Vin- is, at this time since transistor Q2 base-to-emitter current flows through the transistors Q1, Q2 work, since the MOS transistor Ql to which a gate bias resistor R3 larger values, generally about MΩ stage, the collector of transistor Q2 as the values ​​of the large load R3, transistor Q2 directly into saturated the operating state, so that the gate of the N-channel MOS transistor Ql to the source voltage is low, transistor Q2 saturation voltage, typically between 0.7V to 0.1V, this voltage N-channel MOS transistor reach Ql the turn-on voltage, MOS tube Ql is in an off state.

[0008] 这时,该电路从外部电源吸收的最大电流,发生在电容C两端电压为OV的瞬间,该电流最大值为: [0008] In this case, the maximum current of the circuit from an external power absorbed instant OV occurs in the voltage across the capacitor C of the current maximum is:

Figure CN102231518BD00041

[0010] 从上述公式可以看出,该电路在外部电源闭合时,不对外部电源产生难以控制的充电电流,该电流仅与电阻Rl和R2的取值有关,对电容C充电的电流,随着电容C两端电压升高,而逐步下降,电容C两端电压升高,而Vout的数值进一步下降,即输出电压Vout的绝对值增加,当满足: [0010] As can be seen from the above formula, the circuit is closed when the external power supply, the external power source does not generate a charging current is difficult to control, only the current value of the resistor Rl and R2 related to the charging current of the capacitor C, as the the voltage across the capacitor C rises, gradually decreased, the voltage across the capacitor C increases, and the value Vout further decreases, i.e., the absolute value of the output voltage Vout is increased, when satisfied:

[0011] Vout-Vin ^ 0.7V [0011] Vout-Vin ^ 0.7V

[0012] 当满足上述公式时,即三极管Q2的基极、发射极之间的电压也会低于0.7V,三极管Q2截止,这时外部电源通过R3把电压加到Ql的栅极上,相对而言,栅极电压高于源极电压,MOS管Ql开启,处于导通状态,由于MOS管的内阻很低,这时,Vin和Vout电压差极低,电阻Rl和R2两端电压极低,发热功率很小;而电阻R3由于取值较大,发热量也极低;实现了电路进入稳态时,降低了该电路的功率损耗。 [0012] When the above equation is satisfied, i.e. base of the transistor Q2 is the voltage between the emitter will be less than 0.7V, the transistor Q2 is turned off, then the external power source through a voltage applied to the gate R3 Ql relative , the gate voltage is higher than the source voltage, the MOS transistor Ql is turned on, in the oN state, since the internal resistance of the MOS transistor is low, this time, the voltage difference between Vin and Vout is extremely low, the voltage across resistors Rl and R2 pole low heating power is small; the resistor R3 due to the larger value, the heat is very low; to achieve a steady state the circuit, reducing power loss of the circuit.

[0013] 该电路进入稳态时,若这时Vin-有浪涌电压波动,若Vin-电压的绝对值趋势变小,这时电容C上电压会通过MOS管Ql内部的寄生二极管被外部电源钳位,没有什么影响;若Vin-电压的绝对值趋势变大,本电路可以实现浪涌保护,不会对电路产生较大的冲击电流,原理是:若Vin-电压的绝对值趋势变大瞬间,如图1中电压输入端Vin-边上的箭头所示,由于电容C两端电压不能突变,三极管Q2发射极和Vin-相连接,三极管Q2发射极也会瞬间向下跌落,这时,三极管Q2的发射极至电阻R2与Vout连接点之间的电压差会升高,电压差过0.7V时,电阻R2中会出现电流,三极管Q2的基极、发射极会有电流流过,三极管Q2饱和导通,MOS管Ql同步截止,外部电源的浪涌电压波动只能通过R1、R2对电容C起作用,这样实现外部电源有浪涌电压产生时,本电路提供动态的、实时保护。 [0013] This circuit into the steady state, when the surge voltage fluctuation Vin- case, if the absolute value of the voltage Vin- tendency becomes small, then the capacitor C is an external power supply voltage through the parasitic diode of the MOS transistor Ql internal clamp, no influence; tendency Vin- if the absolute value of the voltage increases, the surge protection circuit may be implemented, no large rush current circuit principle: If the absolute value becomes large voltage Vin- trends moment, the arrow next to the voltage input terminal Vin- As shown in FIG. 1, since the voltage across capacitor C can not be mutated, and the emitter of transistor Q2 is connected to Vin-, the emitter of transistor Q2 will instantly fall down, then , the voltage difference between the emitter to the transistor Q2 is connected to resistor R2 and the point Vout rises, the voltage difference over 0.7V, the current will appear in resistor R2, transistor Q2 base, emitter current will flow through, saturated transistor Q2 is turned on, the MOS tube Ql synchronization off, a surge voltage fluctuation of the external power supply only through R1, R2 acting on the capacitor C, when the power supply is achieved by external surge voltage generated, the present circuit provides dynamic, real-time protection .

[0014] 这个电路在实际试验中,发现对Rl的要求很高,特别是使用在高压的场合,如220VAC的市电经整流后出现峰值近310V的脉动高压,在加电的瞬间,该电压就直接通过电容C加到Rl的两端,Rl的功率余量要较大才行,综合说来,该电路也存在下述不足: [0014] In practical tests this circuit, Rl found very demanding, particularly for use in high pressure applications, such as the pulsating high voltage peaks near 310V mains 220VAC rectified to occur, the instantaneous power of the voltage applied directly to both ends of the capacitor C of Rl, Rl power headroom to a large job to said integrated, the circuit is also the following shortcomings:

[0015] 1、开机的浪涌电流为: [0015] 1, power surge current:

Figure CN102231518BD00042

[0017] 想进一步降低开机时的浪涌电流,Rl要取大, [0017] want to further reduce the inrush current during startup, Rl to take large,

[0018] 2,Rl的取值经常出现两难。 [0018] 2, Rl values ​​often appear dilemma. 取小了,开机时冲击电流(浪涌电流)较大。 Take a small rush current (surge current) is large boot. 取大了,对C的充电慢,电路启动时间长,由于后续电路的耗电,Ql迟迟不能导通。 Whichever is greater, and the slow charging of C, the circuit starts a long time, since the power consumption of the subsequent circuits, Ql, conduction delays. RC回路的充电电流,就是随时间的推移,C两端电压升高,流过Rl的充电电流是越来越小的。 The charging current RC circuit, is over time, C increases the voltage across, charging current flowing through Rl is getting smaller.

[0019] 3、Rl的功率余量要足够,由于体积限制的原因,很多对体积要求严格的场合不好兼容。 [0019] 3, Rl power reserve should be sufficient, due to the volume limitations, a lot of volume demanding occasion not compatible. 发明内容 SUMMARY

[0020] 有鉴如此,本发明的目的在于提供一种浪涌抑制电路,要解决的技术问题是,在背景技术图1的基础上,让Ql在开机时工作在恒流源状态,不存在充电引发的浪涌。 [0020] In view of this, object of the present invention is to provide a surge suppression circuit, the technical problem to be solved in the basic background art in FIG. 1, the constant current source so that Ql to work at power state, there is no charging surge triggered. 结束后工作在完全导通状态,同样实现抑制浪涌的目的。 Working in a fully conductive state, to achieve the same purpose after the surge suppression.

[0021] 为解决上述技术问题,本发明提供一种浪涌抑制电路,包括输入电源正负输入端、输出电源正负输出端、场效应管、第二晶体管、第三晶体管、电容、第一电阻、第二电阻及第三电阻,所述正输入端连接正输出端,所述正输入端通过所述的第三电阻后分别与所述的场效应管的栅极及所述的第三晶体管的集电极连接,所述的正输入端经所述的电容连接至所述的场效应管漏极,所述场效应管的漏极还与负输出端连接,所述负输入端通过所述的第一电阻与所述的场效应管源极相连,所述的第三晶体管的基极连接场效应管的源极,所述的第二晶体管的基极通过所述的第二电阻接负输出端,所述第三晶体管的发射极连接所述的第二晶体管的集电极,所述第二晶体管的发射极连接负输入端。 [0021] To solve the above problems, the present invention provides a surge suppression circuit comprising positive and negative input terminal of the input power, output power supply negative output terminal, the field effect transistor, the second transistor, a third transistor, a capacitor, a first , the second resistor and the third resistor, the positive input terminal connected to the positive output terminal, said positive input terminal of the third gate electrode through said third resistor, respectively, with said FET and said connected to the collector of the transistor, said positive input is connected to the capacitor via the drain of the FET, the drain of the FET is also connected to the negative output terminal, said negative input terminal through the FET source and the first resistor connected to said pole, said third transistor having a base electrode connected to the source electrode of the field effect transistor, said second transistor base electrode connected through said second resistor a collector of the second transistor emitter negative output terminal of the third transistor is connected to the said second transistor is connected to the negative input terminal.

[0022] 所述第二晶体管和第三晶体管均为NPN型晶体管,对应地,所述场效应管为N沟道的功率型MOS管。 [0022] The second and third transistors are NPN-type transistors, correspondingly, the power field effect type MOS transistor is an N-channel tube.

[0023] 所述第二晶体管和第三晶体管的基极和发射极分别并联有电阻。 [0023] The base and the emitter of the second transistor and the third transistor are respectively connected in parallel with a resistor.

[0024] 所述场效应管的栅极和源极之间并联有一稳压管。 [0024] parallel between the gate and source electrodes of the field effect transistor has a regulator.

[0025] 作为本发明的另一种实施方式:一种浪涌抑制电路,包括输入电源正负输入端、输出电源正负输出端、场效应管、第二晶体管、第三晶体管、电容、第一电阻、第二电阻及第三电阻,所述负输入端连接负输出端,所述正输入端连接第二晶体管的发射极并通过第一电阻分别连接第三晶体管的基极和场效应管的源极,所述第二晶体管的基极通过第二电阻连接正输出端,所述第二晶体管的集电极连接第三晶体管的发射极,所述第三晶体管的集电极连接场效应管的栅极并通过第三电阻连接负输入端,所述场效应管的漏极连接正输出端并通过电容连接负输入端。 [0025] As another embodiment of the present invention: one surge suppression circuit comprising positive and negative input terminal of the input power, output power supply negative output terminal, the field effect transistor, the second transistor, a third transistor, a capacitor, a first a resistor, a second resistor and a third resistor connected to the negative input terminal of the negative output terminal, said positive input terminal connected emitter of the second transistor, respectively, and connected via a first resistor and a base of the third transistor FET source, said second transistor having a base electrode connected to the positive output terminal via a second resistor, the emitter connected to the collector of the third transistor of the second transistor, the collector of the third transistor is connected FET and a gate connected to the negative input terminal through a third resistor, the drain of the FET is connected to the positive output terminal and negative input terminal connected through a capacitor.

[0026] 所述第二晶体管和第三晶体管均为PNP型晶体管,对应地,所述场效应管为P沟道的功率型MOS管。 [0026] The second and third transistors are PNP transistors, correspondingly, the power FET is a P-channel type MOS transistor.

[0027] 所述第二晶体管和第三晶体管的基极和发射极分别并联有电阻。 [0027] The base and the emitter of the second transistor and the third transistor are respectively connected in parallel with a resistor.

[0028] 所述场效应管的栅极和源极之间并联有一稳压管。 [0028] parallel between the gate and source electrodes of the field effect transistor has a regulator.

[0029] 本发明与现有技术相比,具有以下有益效果: [0029] Compared with the prior art, it has the following advantages:

[0030] 本发明在开机时,MOS管实现恒流充电,有效抑制浪涌电压的注入,在电路进入稳态后,MOS管完全导通,降低了浪涌抑制电路的功率损耗;负载短路时,提供限流保护功能,外部电源有浪涌电压产生时,本电路提供动态的、实时的限流保护。 Load short-circuit; [0030] The present invention is in the boot, the MOS tube to achieve constant current charge, effectively suppress a surge voltage is injected, after the circuit into the steady state, the MOS tube is fully turned on, reducing the power loss in surge suppression circuit , providing current limit protection, the external power supply surge voltage generator, the present circuit provides dynamic, real-time limit protection.

附图说明 BRIEF DESCRIPTION

[0031] 图1为浪涌抑制现有技术比较有效的一种解决方法的原理图; [0031] FIG. 1 is a schematic diagram of the prior art surge suppression is more effective in a solution;

[0032] 图2为本发明浪涌抑制电路的实施例一原理图; [0032] FIG. 2 is a schematic diagram of a surge suppression circuit schematic embodiment of the present invention;

[0033] 图3为本发明浪涌抑制电路的实施例二原理图; [0033] FIG 3 according to a second suppression circuit schematic embodiment of the present invention, a surge;

具体实施方式[0034] 实施例一 DETAILED DESCRIPTION [0034] Example a

[0035] 如图2所示,一种浪涌抑制电路,包括正输入端Vin+,负输入端Vin-,正输出端Vout+,负输出端Vout-,MOS管Q1、第二晶体管Q2、第三晶体管Q3、电容C、第一电阻R1、第二电阻R2及第三电阻R3,正输入端Vin+连接正输出端Vout+,正输入端Vin+通过第三电阻R3后分别与MOS管Ql的栅极和第三晶体管Q3的集电极连接,正输入端Vin+通过电容C连接至场效应管Ql的漏极,MOS管Ql的漏极还与负输出端Vout-连接,负输入端Vin-通过第一电阻Rl与MOS管Ql源极相连,第三晶体管Q3的基极连接至MOS管Ql的源极与第一电阻Rl的连接点上,第二晶体管Q2的基极通过第二电阻R2接负输出端Vout-,第二晶体管Q2的集电极连接第三晶体管Q3的发射极。 As shown in A surge suppression [0035] The circuit in FIG. 2, it includes a positive input terminal Vin +, Vin- is a negative input terminal, a positive output terminal Vout +, the negative output terminal Vout-, MOS tube Q1, a second transistor Q2, a third the transistors Q3, capacitor C, Groups resistor R1, a second resistor R2 and the third resistor R3, a positive input terminal connected to the positive output terminal Vin + Vout +, the positive input terminal Vin + through the gate electrode of the third resistor R3 and the MOS transistors Ql, respectively, and connected to the collector of the third transistor Q3, the positive input terminal Vin + is connected to the drain of the FET Ql through a capacitor C, the drain of the MOS transistor Ql is also connected to the negative output terminal Vout- negative input terminal via a first resistor Vin- Ql and Rl MOS transistor connected to the source, the third transistor Q3 is connected to the base electrode to the source of the MOS transistor Ql and the connection point of the first resistor Rl, the base of the second transistor Q2 through the second resistor R2 to the negative output terminal Vout-, connected to the collector of the second transistor Q2 and the emitter of the third transistor Q3.

[0036] 上述实施例一的工作原理是,当正输入端Vin+接外部电源时,该电源为正压,若电源开关闭合,由于电容两端电压初始为O或较低的电压值,外部电源通过电源线,经过电容C,分为多路回到电压输入端Vin-,(以下简称输入地),一路经过电容C、第二电阻R2以及第二晶体管Q2的基极、发射极回到输入地,这时第二晶体管Q2由于基极到发射极有电流流过,第二晶体管Q2工作,处于饱和导通状态;M0S管的栅极偏置第三电阻R3取值较大,一般在ΜΩ级左右,晶体管Q2的集电极负载:第三电阻R3和第三晶体管Q3,因为第三电阻R3取值大,第二晶体管Q2直接进入饱和工作状态,使得第三晶体管Q3的发射极等效接输入地,这时N沟道MOS管Ql、第三晶体管Q3和第一电阻Rl组成恒流源电路,恒流源的电流为: [0036] The working principle of the above-described first embodiment is that, when a positive input terminal connected to an external power source when the Vin +, which is a positive power supply, if the power switch is closed, since the initial voltage across the capacitor is O or a lower voltage value, the external power supply through the power line, via a capacitor C, is divided into multiple back voltage input terminal Vin -, (hereinafter referred to as the input), all the way through the capacitor C, a second resistor R2 and a second transistor Q2 base, emitter back to the input , the time since the second transistor Q2 base-to-emitter current flows through the second transistor Q2 work in saturation conduction state; a third gate bias resistor R3 tube M0S larger value, typically ΜΩ about level, transistor Q2 collector load: a third resistor R3 and the third transistor Q3, because of the large value of the third resistor R3, the second transistor Q2 directly to saturated operation, so that the emitter of the third transistor Q3 is connected to the equivalent current input, the N-channel MOS transistor Ql, at this time, the third transistor Q3 and the first constant current source circuit composed of a resistor Rl, a constant current source is:

[0037] [0037]

Figure CN102231518BD00061

[0038] 其中Uq3be为第三晶体管Q3的基极与发射极压降,常见的硅管为0.7V左右,VQ2eE(sat)为第二晶体管Q2的集电极与发射极的饱和压降,常见的硅管为0.15V左右,由公式2可见,流过MOS管Ql的电流与第一电阻Rl的取值成反比,另一部分的电流是经过第三电阻R3、第三晶体管Q3集电极、第三晶体管Q3发射极、第二晶体管Q2集电极、第二晶体管Q2发射极的电流,这个电流由于受第三电阻R3影响,在毫安级左右,不会产生浪涌。 [0038] wherein Uq3be base electrode of the third transistor Q3 and the emitter voltage drop, the common silicon tube is about 0.7V, VQ2eE (sat) is the collector of the second transistor Q2 and the emitter saturation voltage, the common silicon tube of about 0.15V, by equation 2, the value is inversely proportional to the current flowing through the first resistor Rl of the MOS transistor Ql, the other part is the current through the third resistor R3, a collector of the third transistor Q3, the third the emitter of the transistor Q3, the collector of the second transistor Q2, a second current electrode of transistor Q2 emitter, the current due to the influence of the third resistor R3, of about mA level, the surge does not occur.

[0039] 恒流源电路的工作原理简述: Working Principle [0039] The constant current source circuit Description:

[0040] 若某种原因使Iki变大,那么第一电阻Rl两端的电压升高,这时,流过第三晶体管Q3的基极、发射极的电流增大,第三晶体管Q3的集电极电流增大,第三电阻R3的两端电压升高,那么第三晶体管Q3的集电极对输入地(Vin-)的电压降低,即MOS管Ql栅极与输入地的电压同步降低,MOS管Ql的导通电流会降低,从而使Iki回到公式2的电流值上。 [0040] If for some reason the Iki is increased, the voltage rise across the first resistor Rl, this time, flow through the base of the third transistor Q3, the emitter current increases, the collector of the third transistor Q3 current increases, the voltage across the third resistor R3 rises, the collector of the third transistor Q3 decreases to the input (Vin- is) a voltage, i.e., the input gate of the MOS transistor Ql reduced simultaneously ground voltage, MOS transistor Ql conduction current is reduced, so that the current Iki back to equation 2.

[0041] 若某种原因使Iki变小,那么第一电阻Rl两端的电压降低,这时,流过第三晶体管Q3的基极、发射极的电流减小,第三晶体管Q3的集电极电流减小,第三电阻R3的两端电压降低,那么第三晶体管Q3的集电极对输入地(Vin-)的电压升高,即MOS管Ql栅极与输入地的电压同步升高,MOS管Ql的导通电流会增加,从而使Iki上升回到公式2的电流值上。 [0041] If for some reason the Iki small, then the first voltage drop across resistor Rl, then, flows through the base of the third transistor Q3, the emitter current decreases, the collector current of the third transistor Q3 decreases, the voltage across the third resistor R3 is reduced, then the collector of the third transistor Q3 to the input (Vin- is) the voltage rises, i.e., the gate of the MOS transistor Ql synchronized with the input voltage rises ground, MOS transistor Ql conduction current increases, so that the current Iki rise back to equation 2.

[0042] 外部电源通过电源线,经过电容C,经过MOS管Q1、第一电阻Rl回到电压输入端的输入地。 [0042] external power through a power line, via a capacitor C, through the MOS transistor Q1, a first resistor Rl and to the input of the ground voltage input terminal. 还有一路经过第三电阻R3、第三晶体管Q3、第二晶体管Q2回到电压输入端的地线。 There are all the way through the third resistor R3, a third transistor Q3, a second transistor Q2, a ground voltage input terminal.

[0043] 从上述公式2可知,本电路在外部电源闭合时,不对外部电源产生难以控制的充电电流,该电流为恒定的Iki,对电容C充电的电流,随着电容C两端电压升高,一直维持在Iei,电容C两端电压升高,而正输出端Vout+与负输出端Vout-之间电压进一步升高,当满足: [0043] 2 can be seen from the above formula, the circuit is closed when the external power source, no external power is difficult to control the charging current is generated, which is the Iki constant current, the charging current of the capacitor C, as the voltage across the capacitor C rises , has been maintained at Iei, the voltage across the capacitor C rises, and the positive output Vout + is further increased and the voltage between the negative output terminal Vout- of, when satisfied:

[0044] Vin-Vout ( 0.7V [0044] Vin-Vout (0.7V

[0045] 当满足上述公式时,即第二晶体管Q2的基极、发射极之间的电压也会低于0.7V,第二晶体管Q2截止,这时第三晶体管Q3也会截止,外部电源通过电阻R3把电压加到MOS管Ql的栅极上,MOS管Ql完全处于导通状态,由于MOS管Ql的内阻很低,这时,Vin和Vout电压差极低,第一电阻Rl由于取值较小,两端电压较低,发热功率很小;而第三电阻R3由于取值极大,发热量很低;实现了电路进入稳态时,降低了浪涌抑制电路的功率损耗。 [0045] When the above equation is satisfied, i.e., the base of the second transistor Q2, the voltage between the emitter will be less than 0.7V, the second transistor Q2 is turned off, the third transistor Q3 is also turned off at this time, the external power source through applying a voltage to resistor R3 to the gate of the MOS transistor Ql, the MOS transistor Ql is fully in the on state, since the internal resistance of the MOS transistor Ql is low, then, the voltage difference between Vin and Vout is very low, since the first resistor Rl taken value is small, the voltage across the low, the heating power is small; and the third resistor R3 due to the great value, low heat; to achieve a steady state the circuit, surge suppression circuit reduces the power loss.

[0046] 电路进入稳态时,若这时Vin有浪涌电压波动,若Vin+电压升高,这时电容C上电压不会突变,变化的电压通过第二电阻R2会让第二晶体管Q2再次饱和导通,使得MOS管Ql再次工作在恒流状态,对电容C的充电电流再次被限流,这样实现外部电源有浪涌电压产生时,本电路提供动态的、实时保护。 [0046] When the steady state, if Vin surge voltage fluctuation time, if Vin + voltage up circuit, then the voltage on the capacitor C will not be mutated, by varying the voltage of the second resistor R2, the second transistor Q2 will again saturated conduction, so that the constant-current MOS transistor Ql working state again, the charging current of the capacitor C is again limiting, the external power supply is achieved when the surge voltage is generated, the present circuit provides dynamic, real-time protection. 若正输入端Vin+电压降低时,MOS管Ql会处于完全导通,由于外部电源电压降低产生的浪涌危害小,可以不用保护。 If the positive input terminal Vin + voltage decreases, the MOS Ql tube will in a fully turned on, a small surge hazard since the external supply voltage drops produced can not protected.

[0047] 负载短路保护功能的实现原理:当电路进入稳态工作时,若负载发生短路,即相当于电容C短路,即电容C的两端电压会降低,这时,第二电阻R2通过第二晶体管Q2的基极、发射极再次有电流流过,第二晶体管Q2饱和导通,MOS管Ql处于恒流工作,这时电路的总工作电流如公式I所示,所以只要合理选择第一电阻R1,配合电路中的保险丝,就可以合理控制电路的总工作电流,不至于让故障扩大化或引发火灾等。 [0047] The principle circuit protection function: When the circuit enters steady state operation, if the load is short-circuited, the short-circuit is equivalent to a capacitance C, i.e., the voltage across the capacitor C decreases, then, the second resistor R2 through a first two base of transistor Q2, an emitter current flows there again, the second transistor Q2 is saturated conduction, the MOS Ql tube is constant current, then the total operating current of the circuit as shown in formula I, so long as a reasonable choice of the first resistor R1, with the fuse circuit, it can reasonably control the total circuit current, so that the failure will not cause a fire or the like enlargement.

[0048] 本实施例一适用于输入端与输出端不共地的电路。 [0048] The present embodiment applies to an input terminal and an output terminal is not common ground circuit implementations.

[0049] 实施例二 [0049] Second Embodiment

[0050] 如图3所示,与实施例一不同的是,第二晶体管Q2、第三晶体管Q3为PNP型晶体管,MOS管Ql为P沟道的功率型MOS管,电源极性要反过来,其它连接关系不变,电容若使用电解电容等有极性电容,接入时按实际极性正确接入即可。 [0050] As shown in FIG. 3, the first embodiment except that the second transistor Q2, a third transistor Q3 is a PNP type transistor, a power MOS transistor Ql P-channel type MOS transistors, the polarity of the power supply to turn other connection relationship unchanged, if the capacitance electrolytic capacitors using polarized capacitors, which are, according to the actual access when the access to the correct polarity.

[0051] 其工作原理同实施例一所述,这里不再赘述。 [0051] The working principle of the embodiment with a not repeated here. 实施例二适合用于控制正电源输入的电路、输入端与输出端需共地的电路。 According to the second positive power supply input circuit adapted for controlling the input and output terminals of the common ground circuit for an embodiment.

[0052] 此外,上述两个实施例还可以进一步改进,如在第二晶体管Q2、第三晶体管Q3的基极与发射极之间并联电阻,可以调节三极管的饱和、截止灵敏度性能,从而调节本发明电路的工作灵敏度。 [0052] Further, the above two embodiments may be further improved, as in the second transistor Q2, the base of the third transistor Q3 and a resistor connected in parallel between the emitter of transistor saturation can be adjusted, sensitivity cutoff performance, to adjust the present work sensitivity of the circuit to the invention.

[0053] 还可在MOS管Ql栅极和源极之间并联上保护用的稳压管,以防止MOS管Ql栅极和源极被高压击穿。 [0053] The regulator may also be protected in parallel with the MOS transistor Ql between the gate and the source, to prevent the MOS transistor Ql gate and the source is high voltage breakdown.

[0054] 以上仅是本发明的优选实施方式,应当指出的是,上述优选实施方式不应视为对本发明的限制,本发明的保护范围应当以权利要求所限定的范围为准。 [0054] The above are only preferred embodiments of the present invention, it should be noted that the above-described preferred embodiments should not be construed as limiting the present invention, the scope of the present invention reference should be made to the scope defined by the claims. 对于本技术领域的普通技术人员来说,在不脱离本发明的精神和范围内,还可以做出若干改进和润饰,这些改进和润饰也应视为本发明的保护范围,如采用三极管或公知的复合管代替相应的MOS管,具体而言,可用NPN型三极管代替N沟道MOS管、用PNP型三极管代替P沟道MOS管,对应的,三极管的基极B、发射极E、集电极C分别对应MOS管的栅极G、源极S、漏极D。 Those of ordinary skill in the art who, without departing from the spirit and scope of the present invention, can make various improvements and modifications, improvements and modifications should also be regarded as the protection scope of the present invention, such as using a known triode or the composite pipe instead of the corresponding MOS transistor, specifically, the NPN transistor can be used instead of the N-channel MOS transistor, a PNP-type transistor instead of the P-channel MOS transistor, corresponding to the transistor base B, an emitter E, a collector C respectively corresponding to the gate G MOS tube, a source S, a drain D.

Claims (8)

1.一种浪涌抑制电路,其特征在于包括输入电源正负输入端、输出电源正负输出端、场效应管、第二晶体管、第三晶体管、电容、第一电阻、第二电阻及第三电阻,所述正输入端连接正输出端,所述正输入端通过所述的第三电阻后分别与所述的场效应管的栅极及所述的第三晶体管的集电极连接,所述的正输入端经所述的电容连接至所述的场效应管漏极,所述场效应管的漏极还与负输出端连接,所述负输入端通过所述的第一电阻与所述的场效应管源极相连,所述的第三晶体管的基极连接场效应管的源极,所述的第二晶体管的基极通过所述的第二电阻接负输出端,所述第三晶体管的发射极连接所述的第二晶体管的集电极,所述第二晶体管的发射极连接负输入端。 A surge suppression circuit, comprising an input power positive and negative inputs, positive and negative output terminal output power supply, a field effect transistor, the second transistor, a third transistor, a capacitor, a first resistor, a second resistor and a second three resistors, the positive input terminal is connected to the positive output terminal, said positive input respectively connected to the collector and to the gate of the FET of the rear end of the third transistor through said third resistor, the via the positive input terminal of said capacitor is connected to the drain of the FET, the drain of the FET is also connected to the negative output terminal, said negative input terminal of the first resistor and through said the source of said FET is connected to the electrode, said third transistor having a base electrode connected to the source electrode of the field effect transistor, said second transistor base electrode of the second resistor connected to the negative output terminal through said first the collector of the second transistor emitter is connected to the three-transistor, and the emitter of the second transistor is connected to the negative input terminal.
2.根据权利要求1所述的浪涌抑制电路,其特征在于所述的第二晶体管和第三晶体管均为NPN型晶体管,对应地,所述场效应管为N沟道的功率型MOS管。 2. The surge suppression circuit of claim 1, wherein said second and third transistors are NPN-type transistors, correspondingly, the power FET is an N-channel type MOS transistors .
3.根据权利要求1所述的浪涌抑制电路,其特征在于所述第二晶体管和第三晶体管的基极和发射极之间分别并联有电阻。 The surge suppression network of Claim 1, said circuit comprising a resistor are connected in parallel between the base of the second transistor and the third transistor and the emitter.
4.根据权利要求1所述的浪涌抑制电路,其特征在于所述场效应管的栅极和源极之间并联有稳压管。 4. The surge suppression circuit according to claim 1, characterized in that in parallel with a zener diode between the gate and source of the FET.
5.—种浪涌抑制电路,其特征在于包括输入电源正负输入端、输出电源正负输出端、场效应管、第二晶体管、第三晶体管、电容、第一电阻、第二电阻及第三电阻,所述负输入端连接负输出端,所述正输入端连接第二晶体管的发射极并通过第一电阻分别连接第三晶体管的基极和场效应管的源极,所述第二晶体管的基极通过第二电阻连接正输出端,所述第二晶体管的集电极连接第三晶体管的发射极,所述第三晶体管的集电极连接场效应管的栅极并通过第三电阻连接负输入端,所述场效应管的漏极连接正输出端并通过电容连接负输入端。 5.- species surge suppression circuit comprising positive and negative input terminal of the input power, output power supply negative output terminal, the field effect transistor, the second transistor, a third transistor, a capacitor, a first resistor, a second resistor and a second three-resistor, said negative input source connected to the negative output terminal, said positive input terminal connected emitter of the second transistor and a base connected to the third transistor and a field-effect transistor via a first resistor electrode respectively, the second a second base of the transistor through a resistor connected to the positive output terminal, the emitter of the third transistor connected to a collector of the second transistor, the gate of the third FET transistor connected to the collector through a third resistor and connected a negative input terminal, a drain connected to the positive output terminal of the FET and the negative input terminal is connected via a capacitor.
6.根据权利要求5所述的浪涌抑制电路,其特征在于所述的第二晶体管和第三晶体管均为PNP型晶体管,对应地,所述场效应管为P沟道的功率型MOS管。 5 6. The surge suppression circuit according to claim, wherein said second and third transistors are PNP transistors, correspondingly, the power field effect type MOS transistor is a P-channel tube .
7.根据权利要求5所述的浪涌抑制电路,其特征在于所述第二晶体管和第三晶体管的基极和发射极之间分别并联有电阻。 The surge suppression network of Claim 5, wherein the circuit comprising a resistor are connected in parallel between the base of the second transistor and the third transistor and the emitter.
8.根据权利要求5所述的浪涌抑制电路,其特征在于所述场效应管的栅极和源极之间并联有稳压管。 8. The surge suppression circuit according to claim 5, characterized in that in parallel with a zener diode between the gate and source of the FET.
CN 201110156185 2011-06-10 2011-06-10 Surging suppression circuit CN102231518B (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN 201110156185 CN102231518B (en) 2011-06-10 2011-06-10 Surging suppression circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN 201110156185 CN102231518B (en) 2011-06-10 2011-06-10 Surging suppression circuit

Publications (2)

Publication Number Publication Date
CN102231518A CN102231518A (en) 2011-11-02
CN102231518B true CN102231518B (en) 2013-09-25

Family

ID=44844063

Family Applications (1)

Application Number Title Priority Date Filing Date
CN 201110156185 CN102231518B (en) 2011-06-10 2011-06-10 Surging suppression circuit

Country Status (1)

Country Link
CN (1) CN102231518B (en)

Families Citing this family (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103812097B (en) * 2012-11-06 2016-12-21 江苏永昌新能源科技有限公司 Current buffer
CN103208774B (en) * 2013-05-02 2015-12-30 石家庄迅能电子科技有限公司 A kind of intrinsic safety electric source short-circuit protection circuit
CN105322522A (en) * 2014-06-24 2016-02-10 中兴通讯股份有限公司 Method and circuit for restraining surge current of DC electrical source
CN104578843B (en) * 2014-12-22 2017-04-19 广州金升阳科技有限公司 Filter circuit of AC/DC (alternating current/direct current) switching converter
CN105305800B (en) * 2015-11-18 2018-08-28 明纬(广州)电子有限公司 A kind of surge current suppression circuit
CN106598192B (en) * 2016-12-12 2019-05-14 郑州云海信息技术有限公司 A kind of power supply unit, method and power supply system
CN109088535A (en) * 2017-06-14 2018-12-25 上海明石光电科技有限公司 A kind of Switching Power Supply and its soft starting circuit
CN108512409A (en) * 2018-05-31 2018-09-07 西南交通大学 A kind of highpowerpulse load power source soft starting device and start method
CN108963999A (en) * 2018-08-07 2018-12-07 中国航空工业集团公司雷华电子技术研究所 A kind of Inrush current restraining device

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101047323A (en) 2006-03-30 2007-10-03 电力集成公司 Method and apparatus for an in-rush current limiting circuit
CN201726130U (en) 2010-07-27 2011-01-26 长城信息产业股份有限公司;长沙湘计海盾科技有限公司 Direct-current surge suppression circuit

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2000092823A (en) * 1998-09-08 2000-03-31 Toko Inc Current limiting circuit

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101047323A (en) 2006-03-30 2007-10-03 电力集成公司 Method and apparatus for an in-rush current limiting circuit
CN201726130U (en) 2010-07-27 2011-01-26 长城信息产业股份有限公司;长沙湘计海盾科技有限公司 Direct-current surge suppression circuit

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
JP特开2000-92823A 2000.03.31

Also Published As

Publication number Publication date
CN102231518A (en) 2011-11-02

Similar Documents

Publication Publication Date Title
CN204068347U (en) Solar control circuit
CN201656433U (en) Overheat protection circuit and electronic equipment using overheat protection circuit
CN101872971A (en) Reverse-connection preventing circuit, reverse-connection preventing processing method and communication equipment
CN100342647C (en) Circuit for positive power source inputting load electrifying slow starting
CN102158067B (en) Starting circuit for switching power supply
CN202486643U (en) High-bandwidth low-voltage difference linear voltage-stabilizing source, system and chip
CN102290806B (en) LDO (Low Dropout Output) overvoltage protective circuit and LDO (Low Dropout Output) using same
CN101515751B (en) The power supply circuit
CN101207327B (en) Soft starting device of power supply
US9136699B2 (en) Dynamic damper and lighting driving circuit comprising the dynamic damper
CN100502195C (en) Surge restraint circuit
CN101436083B (en) High speed constant flow output drive circuit
CN101826724B (en) Anti-reverse connection circuit of direct current power supply
CN102097928B (en) High voltage starting circuit applied to AC/DC converter
CN201256290Y (en) Protection circuit for suppressing surge current and preventing input voltage reverse connection
CN100569038C (en) LED load protector line
CN102111070A (en) Standby current-reduced regulator over-voltage protection circuit
CN101047323A (en) Method and apparatus for an in-rush current limiting circuit
CN202364112U (en) Starting circuit of control chip of switching-mode power supply
CN201383668Y (en) Over-current protection circuit and motor controller applied to same
CN101034798A (en) Power convertor output protection circuit
CN101594047B (en) Simple power-on surge suppression circuit
CN101728824A (en) Surge protection circuit
CN2498637Y (en) Self set-up voltage stable electric source with overcurrent and overvoltage protector
CN203180783U (en) Boosted circuit

Legal Events

Date Code Title Description
C06 Publication
C10 Request of examination as to substance
C14 Granted