CN109213250A - Undervoltage lockout circuit - Google Patents
Undervoltage lockout circuit Download PDFInfo
- Publication number
- CN109213250A CN109213250A CN201810914408.8A CN201810914408A CN109213250A CN 109213250 A CN109213250 A CN 109213250A CN 201810914408 A CN201810914408 A CN 201810914408A CN 109213250 A CN109213250 A CN 109213250A
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- Prior art keywords
- grid
- pmos tube
- drain electrode
- resistance
- npn pipe
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Classifications
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- G—PHYSICS
- G05—CONTROLLING; REGULATING
- G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
- G05F1/00—Automatic systems in which deviations of an electric quantity from one or more predetermined values are detected at the output of the system and fed back to a device within the system to restore the detected quantity to its predetermined value or values, i.e. retroactive systems
- G05F1/10—Regulating voltage or current
- G05F1/46—Regulating voltage or current wherein the variable actually regulated by the final control device is dc
- G05F1/56—Regulating voltage or current wherein the variable actually regulated by the final control device is dc using semiconductor devices in series with the load as final control devices
- G05F1/565—Regulating voltage or current wherein the variable actually regulated by the final control device is dc using semiconductor devices in series with the load as final control devices sensing a condition of the system or its load in addition to means responsive to deviations in the output of the system, e.g. current, voltage, power factor
- G05F1/567—Regulating voltage or current wherein the variable actually regulated by the final control device is dc using semiconductor devices in series with the load as final control devices sensing a condition of the system or its load in addition to means responsive to deviations in the output of the system, e.g. current, voltage, power factor for temperature compensation
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Electromagnetism (AREA)
- General Physics & Mathematics (AREA)
- Radar, Positioning & Navigation (AREA)
- Automation & Control Theory (AREA)
- Inverter Devices (AREA)
Abstract
The invention discloses a kind of undervoltage lockout circuits.Undervoltage lockout circuit includes first resistor, second resistance, 3rd resistor, the first NMOS tube, the first PMOS tube, the first NPN pipe, the second PMOS tube, the 2nd NPN pipe, the 4th resistance, the 5th resistance, third PMOS tube, the 4th PMOS tube, the second NMOS tube, the 5th PMOS tube, the 6th PMOS tube, third NMOS tube, the first phase inverter, the second phase inverter and third phase inverter.Output can be automatically closed when input supply voltage is too low using the present invention.
Description
Technical field
The present invention relates to technical field of integrated circuits more particularly to undervoltage lockout circuits.
Background technique
In integrated circuit design process, power IC is especially designed, it can be automatic when input supply voltage is too low
Output is closed, devises undervoltage lockout circuit thus.
Summary of the invention
Present invention seek to address that the deficiencies in the prior art, provide a kind of undervoltage lockout circuit.
Undervoltage lockout circuit, including first resistor, second resistance, 3rd resistor, the first NMOS tube, the first PMOS tube,
One NPN pipe, the second PMOS tube, the 2nd NPN pipe, the 4th resistance, the 5th resistance, third PMOS tube, the 4th PMOS tube, the 2nd NMOS
Pipe, the 5th PMOS tube, the 6th PMOS tube, third NMOS tube, the first phase inverter, the second phase inverter and third phase inverter:
One termination supply voltage VCC of the first resistor, one end of another termination second resistance and the first NPN pipe
Base stage and the 2nd NPN pipe base stage and the 4th PMOS tube grid and the 6th PMOS tube grid；It is described
One end of a termination first resistor of second resistance and the base stage of the base stage of the first NPN pipe and the 2nd NPN pipe
With the grid of the 4th PMOS tube and the grid of the 6th PMOS tube, the drain electrode of another termination first NMOS tube and institute
State one end of 3rd resistor；The drain electrode and the one of the second resistance of one termination first NMOS tube of the 3rd resistor
End, other end ground connection；The grid of first NMOS tube connects the output end of the third phase inverter, and drain electrode connects the second resistance
One end and the third phase inverter one end, source electrode ground connection；The grid of first PMOS tube and drain electrode are connected together to be connect again
The collector of the first NPN pipe and the grid of the third PMOS tube, source electrode meet supply voltage VCC；The first NPN pipe
Base stage connects the base stage and the described 4th of one end of the first resistor and one end of the second resistance and the 2nd NPN pipe
The grid of the grid of PMOS tube and the 6th PMOS tube, collector connect grid and the drain electrode and described the of first PMOS tube
The grid of three PMOS tube, emitter connect one end of the 4th resistance and one end of the 5th resistance；Second PMOS tube
Grid and drain electrode be connected together and connect the collector of the 2nd NPN pipe and the grid of the 5th PMOS tube again, source electrode connects electricity
Source voltage VCC；The base stage of the 2nd NPN pipe connects one end of the first resistor and one end of the second resistance and described
The grid of the grid and the 6th PMOS tube of the base stage of one NPN pipe and the 4th PMOS tube, collector connect described second
The grid of PMOS tube and the grid of drain electrode and the third PMOS tube, emitter connect one end of the 4th resistance；Described 4th
The emitter of one termination the 2nd NPN pipe of resistance, the emitter and the 5th resistance of another termination the first NPN pipe
One end；The emitter of one termination the first NPN pipe of the 5th resistance and one end of the 4th resistance, another termination
Ground；The grid of the third PMOS tube connects the collector of the first NPN pipe and grid and the drain electrode of first PMOS tube, leakage
Pole connects the source electrode of the 4th PMOS tube, and source electrode meets supply voltage VCC；The grid of 4th PMOS tube connects the first resistor
One end and the second resistance one end and the first NPN pipe base stage and the 2nd NPN pipe base stage and described
The grid of six PMOS tube, drain electrode connect the grid of second NMOS tube and the grid of drain electrode and the third NMOS tube, and source electrode connects
The drain electrode of the third PMOS tube；The grid of second NMOS tube and drain electrode are connected together connects the leakage of the 4th PMOS tube again
The grid of pole and the third NMOS tube, source electrode ground connection；The grid of 5th PMOS tube connects the collector of the 2nd NPN pipe
Grid and drain electrode with second PMOS tube, drain electrode connect the source electrode of the 6th PMOS tube, and source electrode meets supply voltage VCC；Institute
The grid for stating the 6th PMOS tube connects the base of one end of the first resistor and one end of the second resistance and the first NPN pipe
The grid of the base stage and the 4th PMOS tube of pole and the 2nd NPN pipe, drain electrode meet drain electrode and the institute of the third NMOS tube
The input terminal of the first phase inverter and the input terminal of second phase inverter are stated, source electrode connects the drain electrode of the 5th PMOS tube；It is described
The grid of third NMOS tube connects the drain electrode of the 4th PMOS tube and grid and the drain electrode of second NMOS tube, and drain electrode connects described
The drain electrode of 6th PMOS tube and the input terminal of first phase inverter and the input terminal of second phase inverter, source electrode ground connection；Institute
The input for stating the first phase inverter terminates the drain electrode of the 6th PMOS tube and the drain electrode of the third NMOS tube and described second instead
The input terminal of phase device, output end are the output end UVLO_OUT of undervoltage lockout circuit；The input of second phase inverter terminates institute
The input terminal for stating the drain electrode of the 6th PMOS tube and the drain electrode of the third NMOS tube and first phase inverter, exports described in termination
The input terminal of third phase inverter；The input of the third phase inverter terminates the output end of second phase inverter, output termination institute
State the grid of the first NMOS tube.
The first resistor, the second resistance and the 3rd resistor constitute the first NPN pipe and institute by partial pressure
State the operating point of the 2nd NPN pipe；When supply voltage VCC voltage is lower, because the pipe number of the 2nd NPN pipe is
6 times of the first NPN pipe, so the electric current for then flowing through the 2nd NPN pipe is larger, rear stage by the 3rd PMOS
The telescopic comparator that pipe, the 4th PMOS tube, the second NMOS tube, the 5th PMOS tube, the 6th PMOS tube and third NMOS tube are constituted
High level is exported, then by exporting low level after first inverter, control chip is not exported；Work as supply voltage
When VCC voltage is higher, because of the adjustment effect of the 4th resistance, so that flowing through the electric current of the 2nd NPN pipe than described
One NPN pipe it is small, result in telescopic comparator output low level, control chip normally exports.
Detailed description of the invention
Fig. 1 is the circuit diagram of undervoltage lockout circuit of the invention.
Specific embodiment
The content of present invention is further illustrated below in conjunction with attached drawing.
Undervoltage lockout circuit, as shown in Figure 1, including first resistor 101, second resistance 102,3rd resistor 103, first
NMOS tube 104, the first PMOS tube 105, the first NPN pipe 106, the second PMOS tube 107, the 2nd NPN pipe 108, the 4th resistance 109,
5th resistance 110, third PMOS tube 111, the 4th PMOS tube 112, the second NMOS tube 113, the 5th PMOS tube 114, the 6th PMOS
Pipe 115, third NMOS tube 116, the first phase inverter 117, the second phase inverter 118 and third phase inverter 119:
One termination supply voltage VCC of the first resistor 101, one end of another termination second resistance 102 and described the
The grid and the described 6th of the base stage and the 4th PMOS tube 112 of the base stage of one NPN pipe 106 and the 2nd NPN pipe 108
The grid of PMOS tube 115；One end of the one termination first resistor 101 of the second resistance 102 and the first NPN pipe
Grid and the 6th PMOS tube 115 of the base stage and the 4th PMOS tube 112 of 106 base stage and the 2nd NPN pipe 108
Grid, the drain electrode of another termination first NMOS tube 104 and one end of the 3rd resistor 103；The 3rd resistor 103
Termination first NMOS tube 104 drain electrode and the second resistance 102 one end, other end ground connection；Described first
The grid of NMOS tube 104 connects the output end of the third phase inverter 119, and drain electrode connects one end of the second resistance 102 and described
One end of third phase inverter 103, source electrode ground connection；The grid of first PMOS tube 105 and drain electrode are connected together connects described again
The grid of the collector of one NPN pipe 106 and the third PMOS tube 111, source electrode meet supply voltage VCC；The first NPN pipe
106 base stage connects the base of one end of the first resistor 101 and one end of the second resistance 102 and the 2nd NPN pipe 108
The grid of the grid and the 6th PMOS tube 115 of pole and the 4th PMOS tube 112, collector connect first PMOS tube
The grid of 105 grid and drain electrode and the third PMOS tube 111, emitter connect one end of the 4th resistance 109 and described
One end of 5th resistance 110；The grid of second PMOS tube 107 and drain electrode are connected together connects the 2nd NPN pipe 108 again
The grid of collector and the 5th PMOS tube 114, source electrode meet supply voltage VCC；The base stage of the 2nd NPN pipe 108 meets institute
State the base stage and the described 4th of one end of first resistor 101 and one end of the second resistance 102 and the first NPN pipe 106
The grid of the grid of PMOS tube 112 and the 6th PMOS tube 115, collector connect grid and the leakage of second PMOS tube 107
The grid of pole and the third PMOS tube 114, emitter connect one end of the 4th resistance 109；The one of 4th resistance 109
Terminate the emitter of the 2nd NPN pipe 108, the emitter and the 5th resistance of another termination the first NPN pipe 106
110 one end；The emitter of one termination the first NPN pipe 106 of the 5th resistance 110 and the 4th resistance 109
One end, other end ground connection；The grid of the third PMOS tube 111 connects the collector and described first of the first NPN pipe 106
The grid of PMOS tube 105 and drain electrode, drain electrode connect the source electrode of the 4th PMOS tube 112, and source electrode meets supply voltage VCC；Described
The grid of four PMOS tube 112 meets one end of the first resistor 101 and one end of the second resistance 102 and the first NPN
The grid of the base stage and the 6th PMOS tube 115 of the base stage of pipe 106 and the 2nd NPN pipe 108, drain electrode connect described second
The grid of NMOS tube 113 and the grid of drain electrode and the third NMOS tube 116, source electrode connect the drain electrode of the third PMOS tube 111；
The grid of second NMOS tube 113 and drain electrode are connected together connects the drain electrode and described of the 4th PMOS tube 112 again
The grid of three NMOS tubes 116, source electrode ground connection；The grid of 5th PMOS tube 114 connects the collector of the 2nd NPN pipe 108
Grid and drain electrode with second PMOS tube 107, drain electrode connect the source electrode of the 6th PMOS tube 115, and source electrode connects supply voltage
VCC；The grid of 6th PMOS tube 115 meets one end of the first resistor 101 and one end of the second resistance 102 and institute
The grid of the base stage of the first NPN pipe 106 and the base stage of the 2nd NPN pipe 108 and the 4th PMOS tube 112 is stated, drain electrode connects
The input of the input terminal and second phase inverter 118 of the drain electrode and first phase inverter 117 of the third NMOS tube 116
End, source electrode connect the drain electrode of the 5th PMOS tube 114；The grid of the third NMOS tube 116 connects the 4th PMOS tube 112
The grid and drain electrode of drain electrode and second NMOS tube 113, drain electrode connect the drain electrode and described first of the 6th PMOS tube 115 instead
The input terminal of the input terminal of phase device 117 and second phase inverter 118, source electrode ground connection；The input terminal of first phase inverter 117
Connect the input of the drain electrode of the 6th PMOS tube 115 and the drain electrode of the third NMOS tube 116 and second phase inverter 118
End, output end are the output end UVLO_OUT of undervoltage lockout circuit；The input termination the described 6th of second phase inverter 118
The input terminal of the drain electrode of PMOS tube 115 and the drain electrode of the third NMOS tube 116 and first phase inverter 117, output termination
The input terminal of the third phase inverter 119；The input of the third phase inverter 119 terminates the output of second phase inverter 118
End, output terminate the grid of first NMOS tube 104.
The first resistor 101, the second resistance 102 and the 3rd resistor 103 constitute described first by partial pressure
The operating point of NPN pipe 106 and the 2nd NPN pipe 108；When supply voltage VCC voltage is lower, because described second
The pipe number of NPN pipe 108 is 6 times of the first NPN pipe 106, so then flowing through the electric current of the 2nd NPN pipe 108
It is larger, rear stage by the third PMOS tube 111, the 4th PMOS tube 112, the second NMOS tube 113, the 5th PMOS tube 114,
The telescopic comparator that six PMOS tube 115 and third NMOS tube 116 are constituted exports high level, then anti-by first phase inverter
Low level is exported after phase, control chip does not export；When supply voltage VCC voltage is higher, because the 4th resistance 109
Adjustment effect results in telescopic ratio so that the electric current for flowing through the 2nd NPN pipe 108 is smaller than the first NPN pipe 106
Low level is exported compared with device, control chip normally exports.
It is only the explanation of the preferred embodiment of the present invention, to this technology to the explanation of above-mentioned provided embodiment
It can be realized or used the present invention from the description above for the technical staff in field.It should be pointed out that being led for this technology
For the technical staff in domain, without departing from the technical principles of the invention, several improvement and deformations can also be made, any
Without departing from the innovation and creation within the scope of true spirit, protection scope of the present invention should be regarded as.
Claims (1)
1. undervoltage lockout circuit, it is characterised in that: including first resistor, second resistance, 3rd resistor, the first NMOS
Pipe, the first PMOS tube, the first NPN pipe, the second PMOS tube, the 2nd NPN pipe, the 4th resistance, the 5th resistance, the 3rd PMOS
Pipe, the 4th PMOS tube, the second NMOS tube, the 5th PMOS tube, the 6th PMOS tube, third NMOS tube, the first phase inverter, the second reverse phase
Device and third phase inverter；
One termination supply voltage VCC of the first resistor, one end of another termination second resistance and the first NPN pipe
Base stage and the 2nd NPN pipe base stage and the 4th PMOS tube grid and the 6th PMOS tube grid；It is described
One end of a termination first resistor of second resistance and the base stage of the base stage of the first NPN pipe and the 2nd NPN pipe
With the grid of the 4th PMOS tube and the grid of the 6th PMOS tube, the drain electrode of another termination first NMOS tube and institute
State one end of 3rd resistor；The drain electrode and the one of the second resistance of one termination first NMOS tube of the 3rd resistor
End, other end ground connection；The grid of first NMOS tube connects the output end of the third phase inverter, and drain electrode connects the second resistance
One end and the third phase inverter one end, source electrode ground connection；The grid of first PMOS tube and drain electrode are connected together to be connect again
The collector of the first NPN pipe and the grid of the third PMOS tube, source electrode meet supply voltage VCC；The first NPN pipe
Base stage connects the base stage and the described 4th of one end of the first resistor and one end of the second resistance and the 2nd NPN pipe
The grid of the grid of PMOS tube and the 6th PMOS tube, collector connect grid and the drain electrode and described the of first PMOS tube
The grid of three PMOS tube, emitter connect one end of the 4th resistance and one end of the 5th resistance；Second PMOS tube
Grid and drain electrode be connected together and connect the collector of the 2nd NPN pipe and the grid of the 5th PMOS tube again, source electrode connects electricity
Source voltage VCC；The base stage of the 2nd NPN pipe connects one end of the first resistor and one end of the second resistance and described
The grid of the grid and the 6th PMOS tube of the base stage of one NPN pipe and the 4th PMOS tube, collector connect described second
The grid of PMOS tube and the grid of drain electrode and the third PMOS tube, emitter connect one end of the 4th resistance；Described 4th
The emitter of one termination the 2nd NPN pipe of resistance, the emitter and the 5th resistance of another termination the first NPN pipe
One end；The emitter of one termination the first NPN pipe of the 5th resistance and one end of the 4th resistance, another termination
Ground；The grid of the third PMOS tube connects the collector of the first NPN pipe and grid and the drain electrode of first PMOS tube, leakage
Pole connects the source electrode of the 4th PMOS tube, and source electrode meets supply voltage VCC；The grid of 4th PMOS tube connects the first resistor
One end and the second resistance one end and the first NPN pipe base stage and the 2nd NPN pipe base stage and described
The grid of six PMOS tube, drain electrode connect the grid of second NMOS tube and the grid of drain electrode and the third NMOS tube, and source electrode connects
The drain electrode of the third PMOS tube；The grid of second NMOS tube and drain electrode are connected together connects the leakage of the 4th PMOS tube again
The grid of pole and the third NMOS tube, source electrode ground connection；The grid of 5th PMOS tube connects the collector of the 2nd NPN pipe
Grid and drain electrode with second PMOS tube, drain electrode connect the source electrode of the 6th PMOS tube, and source electrode meets supply voltage VCC；Institute
The grid for stating the 6th PMOS tube connects the base of one end of the first resistor and one end of the second resistance and the first NPN pipe
The grid of the base stage and the 4th PMOS tube of pole and the 2nd NPN pipe, drain electrode meet drain electrode and the institute of the third NMOS tube
The input terminal of the first phase inverter and the input terminal of second phase inverter are stated, source electrode connects the drain electrode of the 5th PMOS tube；It is described
The grid of third NMOS tube connects the drain electrode of the 4th PMOS tube and grid and the drain electrode of second NMOS tube, and drain electrode connects described
The drain electrode of 6th PMOS tube and the input terminal of first phase inverter and the input terminal of second phase inverter, source electrode ground connection；Institute
The input for stating the first phase inverter terminates the drain electrode of the 6th PMOS tube and the drain electrode of the third NMOS tube and described second instead
The input terminal of phase device, output end are the output end UVLO_OUT of undervoltage lockout circuit；The input of second phase inverter terminates institute
The input terminal for stating the drain electrode of the 6th PMOS tube and the drain electrode of the third NMOS tube and first phase inverter, exports described in termination
The input terminal of third phase inverter；The input of the third phase inverter terminates the output end of second phase inverter, output termination institute
State the grid of the first NMOS tube.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201810914408.8A CN109213250A (en) | 2018-08-12 | 2018-08-12 | Undervoltage lockout circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201810914408.8A CN109213250A (en) | 2018-08-12 | 2018-08-12 | Undervoltage lockout circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN109213250A true CN109213250A (en) | 2019-01-15 |
Family
ID=64988395
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201810914408.8A Pending CN109213250A (en) | 2018-08-12 | 2018-08-12 | Undervoltage lockout circuit |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN109213250A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN115220509A (en) * | 2021-04-19 | 2022-10-21 | 圣邦微电子（北京）股份有限公司 | High-threshold-precision undervoltage locking circuit combined with calibration unit |
-
2018
- 2018-08-12 CN CN201810914408.8A patent/CN109213250A/en active Pending
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN115220509A (en) * | 2021-04-19 | 2022-10-21 | 圣邦微电子（北京）股份有限公司 | High-threshold-precision undervoltage locking circuit combined with calibration unit |
| CN115220509B (en) * | 2021-04-19 | 2024-01-30 | 圣邦微电子（北京）股份有限公司 | High-threshold-precision undervoltage locking circuit combined with calibration unit |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| WD01 | Invention patent application deemed withdrawn after publication |
Application publication date: 20190115 |
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| WD01 | Invention patent application deemed withdrawn after publication |