CN208224679U - A kind of array substrate detection circuit - Google Patents
A kind of array substrate detection circuit Download PDFInfo
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- CN208224679U CN208224679U CN201820815800.2U CN201820815800U CN208224679U CN 208224679 U CN208224679 U CN 208224679U CN 201820815800 U CN201820815800 U CN 201820815800U CN 208224679 U CN208224679 U CN 208224679U
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- grid line
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Abstract
Array substrate detection circuit provided by the utility model, by the way that even number grid line lead and odd gates lead are respectively set at left and right sides of array substrate, avoiding lead, to be arranged in array substrate unilateral and lead to that lead is excessively intensive or lead occupied space is larger, reduce the arrangement difficulty of lead, simultaneously the design of narrow frame will not be influenced because lead is arranged in the same side, on the other hand, the odd gates lead of the left and right sides is connected together, even gate lead is also connected to together, it can reduce by two TestPad, be conducive to the design of narrow frame and small-size product, and this measurement circuit design will not influence the accuracy of test.
Description
Technical field
The utility model relates to field of display technology, more particularly to a kind of detection circuit of array substrate.
Background technique
Since human society enters the information age, the life of information display technology and the mankind are with regard to closely bound up, display screen
It has been the quite high a kind of product of popularization since entering the 21 century unlatching intelligent epoch, is widely used in mobile terminal.Display
For device as a kind of mature, convenient and fast input equipment, it is a kind of man-machine interaction mode that today's society is most simple, most popular,
It imparts life, production with brand-new looks, is modern life, a part indispensable in work, gives birth in production
Every field living, which suffers from, to be widely applied.
A liquid crystal display applications class display widest in area is that is produced from the direction of propagation for changing light by liquid crystal cell
The non-active luminescence type display of raw display effect.Current thin film transistor liquid crystal display (TFT-LCD) (TFT-LCD) liquid crystal display
Mainstream, liquid crystal display panel are mainly made of array substrate, liquid crystal, colored filter.TFT technology is nineteen nineties hair
What exhibition was got up, be liquid crystal, inorganic and organic using the large-scale semiconductive completely inegrated circuit manufacturing technology of new material and new process
The basis of thin film electroluminescence flat-panel monitor.
During manufacturing array substrate, to prevent to cause next production link because of array substrate poor short circuit in advance
Waste usually has the detection circuit for phenomena such as can detecting poor short circuit before binding IC in design in array substrate.Tradition
Design scheme be that each detection circuit detects a grid line, but such detection circuit can not efficiently pick out defective products.
Also having and multiple odd number grid lines are controlled using a detection circuit, a detection circuit controls the scheme of multiple even electrode lines, this
Sample can be improved detection efficiency, but this scheme is because of Test Pad(test point) excessively, limitation is bigger, is surveyed using this kind
Examination scheme can be such that the small size of product and narrow frame design becomes difficult, and therefore, the detection of narrow frame or small-size product is only
Traditional measurement circuit design can be taken, the arrangement difficulty of this design scheme, grid lead is also bigger, and is unfavorable for
The design of narrow frame and small-size product.
Utility model content
The purpose of this utility model is to provide a kind of array substrate observation circuit, solved in the prior art narrow frame,
Its grid lead of the array substrate of small size arranges the technical problem that difficulty is big, Test Pad is more.
A kind of array substrate detection circuit provided by the utility model, which is characterized in that the detection circuit includes being located at
It several pixel circuits of array arrangement, a plurality of grid line, multiple data lines and is connect with the grid line in the array substrate
A plurality of grid lead, the grid lead include left area's odd number grid line on the left of the array substrate grid lead,
The grid lead of left area's even number grid line, the grid lead of right area's odd number grid line, right area's even number grid line grid lead, and left area
The grid lead of odd number grid line is connected with the grid lead of right area's odd number grid line, the grid lead and You Qu of left area's even number grid line
The grid lead of even number grid line is connected.
Further, the pixel circuit includes multiple TFT transistors being one another in series.
Further, the pixel circuit further includes pixel electrode, storage capacitance and public electrode.
Further, the array substrate detection circuit further includes VGG pressure-wire, and the VGG pressure-wire is used for described
The grid lead of left area's odd number grid line, the grid lead of left area's even number grid line, right area's odd number grid line grid lead,
The grid lead of right area's even number grid line, the data line, the pixel circuit public electrode output voltage.
Further, the array substrate detection circuit further includes tester, and the tester to array substrate for applying
Add scheduled voltage;The tester include the port VGE, the port VGO, the port VGG, the port VCOM, the port VDR, the port VDG,
The port VDB.
A kind of array substrate detection circuit provided by the utility model, which is characterized in that the detection circuit includes being located at
It several pixel circuits of array arrangement, a plurality of grid line, multiple data lines and is connect with the grid line in the array substrate
A plurality of grid lead, the grid lead include left area's odd number grid line on the left of the array substrate grid lead,
The grid lead of left area's even number grid line, the grid lead of right area's odd number grid line, right area's even number grid line grid lead, and left area
The grid lead of odd number grid line is connected with the grid lead of right area's odd number grid line, the grid lead and You Qu of left area's even number grid line
The grid lead of even number grid line is connected.
Above-mentioned array substrate detection circuit, by the way that even number grid line lead and surprise are respectively set at left and right sides of array substrate
Number grid leads, avoid lead be arranged in array substrate it is unilateral and cause lead excessively intensive or lead occupied space compared with
Greatly, it reduces the arrangement difficulty of lead, while the design of narrow frame will not be influenced because lead is arranged in the same side, it is another
Aspect, the odd gates lead of the left and right sides is connected together, even gate lead is also connected to together, can reduce two
TestPad is conducive to the design of narrow frame and small-size product, and this measurement circuit design will not influence the accurate of test
Property.
Detailed description of the invention
It, below will be right in order to illustrate more clearly of specific embodiment of the present invention or technical solution in the prior art
Specific embodiment or attached drawing needed to be used in the description of the prior art are briefly described, it should be apparent that, it is described below
In attached drawing be that some embodiments of the utility model are not paying creativeness for those of ordinary skill in the art
Under the premise of labour, it is also possible to obtain other drawings based on these drawings.
Fig. 1 is the array substrate detection circuit schematic diagram that the utility model one of which embodiment provides.
Appended drawing reference:
The port 1-VGG;The port 2-VGO;The port 3-VGE;The port 4-VCOM;The port 5-VDR;The port 6-VDG;The end 7-VDB
Mouthful;The grid lead of the right area's even number grid line of 8-;The grid lead of the right area's odd number grid line of 9-;10-VGG pressure-wire;The left area's odd number of 11-
The grid lead of grid line;The grid lead of the left area's even number grid line of 12-;The first tie point of 13-;The second tie point of 14-;15- data
Line.
Specific embodiment
In the description of the present invention, it should be noted that unless otherwise clearly defined and limited, term " is pacified
Dress ", " connected ", " connection " shall be understood in a broad sense, for example, it may be being fixedly connected, may be a detachable connection, or integrally
Connection;It can be mechanical connection, be also possible to be electrically connected;Can be directly connected, can also indirectly connected through an intermediary,
It can be the connection inside two elements.For the ordinary skill in the art, above-mentioned art can be understood with concrete condition
The concrete meaning of language in the present invention.
Fig. 1 is the array substrate detection circuit schematic diagram that the utility model one of which embodiment provides.
Embodiment 1
As shown in Figure 1, a kind of array substrate detection circuit provided in this embodiment, which is characterized in that the detection circuit
Including be located at several pixel circuits of array arrangement in the array substrate, a plurality of grid line, multiple data lines 5 and with it is described
The a plurality of grid lead of grid line connection, the grid lead include the grid of left area's odd number grid line on the left of the array substrate
Pole lead 11, the grid lead 12 of left area's even number grid line, the grid lead 9 of right area's odd number grid line, right area's even number grid line grid
Lead 8, and the grid lead 11 of left area's odd number grid line and the grid lead 9 of right area's odd number grid line pass through 13 phase of the first tie point
Connection, left area's even number grid line grid lead 12 and the grid lead 8 of right area's even number grid line pass through the second tie point 14 and be connected,
The pixel circuit includes multiple TFT transistor and pixel electrode, storage capacitance and public electrode being one another in series;
The array substrate detection circuit further includes VGG pressure-wire 10, and the VGG pressure-wire 10 is used for odd to the left area
Number the grid leads 11 of grid line, the grid lead 12 of left area's even number grid line, right area's odd number grid line grid lead 9,
The grid lead 8 of right area's even number grid line, the data line 5, the pixel circuit public electrode output voltage;
The array substrate detection circuit further includes tester, and the tester is used to apply scheduled electricity to array substrate
Pressure;The tester includes the port VGG 1, the port VGO 2, the port VGE 3, the port VCOM 4, the port VDR 5, the port VDG 6, the end VDB
Mouth 7.
Even number grid line lead and odd gates lead is respectively set in the left and right sides in above-mentioned array substrate, can reduce lead
Arrangement difficulty, and be very suitable for squeezing the design of frame or small-size product, by two tie points by left and right area
Odd gates lead-out wire be connected, the even gate lead-out wire in left and right area be connected, to reduce two TestPad,
Be conducive to the structure design of narrow frame and small-size product, and can satisfy the accuracy of test.
As the alternate embodiments of above-described embodiment, multiple TFT transistors being one another in series be specially 2,3,4 or
4 or more.
Finally, it should be noted that the above various embodiments is only to illustrate the technical solution of the utility model, rather than it is limited
System;Although the present invention has been described in detail with reference to the aforementioned embodiments, but those skilled in the art answer
Work as understanding: it is still possible to modify the technical solutions described in the foregoing embodiments, either to part of or complete
Portion's technical characteristic is equivalently replaced;And these are modified or replaceed, it does not separate the essence of the corresponding technical solution, and this is practical
The range of novel each embodiment technical solution.
Claims (5)
1. a kind of array substrate detection circuit, which is characterized in that the detection circuit includes being located at array in the array substrate
Several pixel circuits, a plurality of grid line, multiple data lines and a plurality of grid lead being connect with the grid line of arrangement, it is described
Grid lead includes that the grid lead of left area's odd number grid line, the grid of left area's even number grid line on the left of the array substrate draw
Line, the grid lead of right area's odd number grid line, right area's even number grid line grid lead, and the grid lead of left area's odd number grid line with
The grid lead of right area's odd number grid line is connected, the grid lead phase of the grid lead of left area's even number grid line and right area's even number grid line
Connection.
2. a kind of array substrate detection circuit according to claim 1, which is characterized in that the pixel circuit includes multiple
The TFT transistor being one another in series.
3. a kind of array substrate detection circuit according to claim 2, which is characterized in that the pixel circuit further includes picture
Plain electrode, storage capacitance and public electrode.
4. a kind of array substrate detection circuit according to claim 3, which is characterized in that the array substrate detection circuit
It further include VGG pressure-wire, the VGG pressure-wire is for grid lead, the left area's even number grid to left area's odd number grid line
The grid lead of line, the grid lead of right area's odd number grid line, the grid lead of right area's even number grid line, the data
The public electrode output voltage of line, the pixel circuit.
5. array substrate detection circuit described in any one of -4 claims according to claim 1, which is characterized in that further include
Tester, the tester are used to apply scheduled voltage to array substrate;The tester include the port VGE, the port VGO,
The port VGG, the port VCOM, the port VDR, the port VDG, the port VDB.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
CN201820815800.2U CN208224679U (en) | 2018-05-30 | 2018-05-30 | A kind of array substrate detection circuit |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
CN201820815800.2U CN208224679U (en) | 2018-05-30 | 2018-05-30 | A kind of array substrate detection circuit |
Publications (1)
Publication Number | Publication Date |
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CN208224679U true CN208224679U (en) | 2018-12-11 |
Family
ID=64506819
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CN201820815800.2U Active CN208224679U (en) | 2018-05-30 | 2018-05-30 | A kind of array substrate detection circuit |
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CN (1) | CN208224679U (en) |
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2018
- 2018-05-30 CN CN201820815800.2U patent/CN208224679U/en active Active
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