CN205139542U - Array baseplate and display device - Google Patents
Array baseplate and display device Download PDFInfo
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- CN205139542U CN205139542U CN201520945361.3U CN201520945361U CN205139542U CN 205139542 U CN205139542 U CN 205139542U CN 201520945361 U CN201520945361 U CN 201520945361U CN 205139542 U CN205139542 U CN 205139542U
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- 239000000758 substrate Substances 0.000 claims abstract description 51
- 230000002093 peripheral effect Effects 0.000 claims abstract description 21
- 239000010409 thin film Substances 0.000 claims description 41
- 239000000463 material Substances 0.000 claims description 3
- 238000000034 method Methods 0.000 description 37
- 238000000059 patterning Methods 0.000 description 27
- 239000004973 liquid crystal related substance Substances 0.000 description 14
- 230000008878 coupling Effects 0.000 description 5
- 238000010168 coupling process Methods 0.000 description 5
- 238000005859 coupling reaction Methods 0.000 description 5
- 230000000694 effects Effects 0.000 description 5
- 206010047571 Visual impairment Diseases 0.000 description 4
- 230000001808 coupling effect Effects 0.000 description 4
- 238000010586 diagram Methods 0.000 description 4
- 239000004065 semiconductor Substances 0.000 description 4
- 238000004519 manufacturing process Methods 0.000 description 2
- 238000002360 preparation method Methods 0.000 description 2
- 229910021417 amorphous silicon Inorganic materials 0.000 description 1
- 238000009826 distribution Methods 0.000 description 1
- 230000005684 electric field Effects 0.000 description 1
- 239000010408 film Substances 0.000 description 1
- 230000010287 polarization Effects 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
- 229920005591 polysilicon Polymers 0.000 description 1
- 230000005855 radiation Effects 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
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Abstract
The embodiment of the utility model provides an array baseplate and display device relates to and shows technical field, can improve phenomenons such as the scintillation that appears, incomplete picture among the prior art. This array substrate includes area of occurrence and peripheral wiring district, the area of occurrence divide into a plurality of regions, it is same NULL electric connection in all pixels of containing in the region is as an organic whole, it is different NULL between the region passes through the switch element and connects, array substrate still includes and every the regional control line that corresponds, the control line is used for for in the one's respective area the NULL provide voltage signal. Be used for jumbo size display device.
Description
Technical Field
The utility model relates to a show technical field, especially relate to an array substrate and display device.
Background
A liquid crystal display (LCD for short) has the characteristics of small volume, low power consumption, no radiation, and the like, and occupies a leading position in the current display market.
In recent years, large-sized, high-resolution liquid crystal displays have become a major trend. Specifically, the liquid crystal display includes a liquid crystal display panel and a backlight source, and the liquid crystal display panel includes an array substrate, a pair of box substrates, and a liquid crystal layer located therebetween. The working principle is that the electric field between the pixel electrode and the common electrode is mainly used for controlling the arrangement state of liquid crystal molecules so as to control the light output quantity of light emitted by the backlight source after passing through the liquid crystal layer, thereby displaying the required display image.
The voltage of the pixel electrode on the array substrate is generally connected through a data line, the common electrode is electrically connected, and the voltage of the common electrode is connected through a common electrode line.
However, the large-sized liquid crystal display has the disadvantages that the uniformity of the common electrode is poor, the resistance is uneven, the voltage of the common electrode is unevenly distributed in the plane, on one hand, the Flicker (Flicker) in the plane is uneven, on the other hand, the direct current residue is generated, and the polarization of the orientation film (PI) finally causes the residual image, thereby affecting the picture quality. In addition, the coupling effect between the common electrode and the data lines on the array substrate can pull the voltage of the common electrode, and because the voltage of the common electrode is not uniform and the effects generated by the pulling effect are different, the red and blue pixel brightness is reduced, the green pixel brightness is increased, and finally the picture is green.
Currently, the method for improving the above problem is to perform a certain compensation modulation on the common voltage. However, the compensation modulation method applied to the large-sized liquid crystal display panel can only improve the influence of the feedthrough voltage (Δ Vp, i.e. the difference between the input common voltage and the actual voltage of the common electrode) on the large-sized panel, and cannot improve the whole panel completely.
SUMMERY OF THE UTILITY MODEL
An embodiment of the utility model provides an array substrate and display device can improve the phenomenon such as scintillation, afterimage, picture turn green that appear among the prior art.
In order to achieve the above object, the embodiments of the present invention adopt the following technical solutions:
in a first aspect, an array substrate is provided, where the array substrate includes a display area and a peripheral wiring area, and the display area is divided into a plurality of areas; common electrodes in all pixels included in the same region are electrically connected into a whole; the common electrodes between different regions are connected through a switch unit; the array substrate further comprises control lines corresponding to the regions, and the control lines are used for providing voltage signals for the common electrodes in the regions.
In a first possible implementation manner of the first aspect, the common electrodes in the same region are electrically connected through a first common electrode line arranged along a first direction and/or a second common electrode line arranged along a second direction; wherein the first direction and the second direction intersect.
With reference to the first aspect or the first possible implementation manner of the first aspect, in a second possible implementation manner, the switch unit includes a first thin film transistor, and the first thin film transistor includes a first gate electrode, a first active layer, a first source electrode, and a first drain electrode; the first source electrode and the first drain electrode are electrically coupled with the common electrode in different regions, respectively.
With reference to the second possible implementation manner of the first aspect, in a third possible implementation manner, the first thin film transistor is disposed between adjacent rows or columns of pixels in different regions.
With reference to the third possible implementation manner of the first aspect, in a fourth possible implementation manner, the pixel includes a second thin film transistor and a pixel electrode, and the second thin film transistor includes a second gate electrode, a second active layer, a second source electrode, and a second drain electrode; the second gate electrode is electrically connected with the gate line, the second source electrode is electrically connected with the data line, and the second drain electrode is electrically connected with the pixel electrode; the array substrate comprises a first common electrode line arranged along a first direction and a second common electrode line arranged along a second direction; wherein the first common electrode line is parallel to the gate line; the first gate electrode, the second gate electrode, the gate line and the first common electrode line are disposed on the same layer.
With reference to the fourth possible implementation manner of the first aspect, in a fifth possible implementation manner, the first source electrode and the first drain electrode are disposed at the same layer as the pixel electrode; or the first source electrode and the first drain electrode are arranged at the same layer as the second source electrode and the second drain electrode; the first source electrode and the first drain electrode are both strip-shaped, one end of each strip-shaped source electrode is connected with the first active layer of the first thin film transistor, and the other end of each strip-shaped source electrode is electrically connected with the first common electrode line in different areas.
With reference to the fourth possible implementation manner of the first aspect, in a sixth possible implementation manner, the second common electrode line is parallel to the data line, and the second common electrode line is disposed in the same layer as the data line, the second source electrode, and the second drain electrode; or the second common electrode line and the pixel electrode are arranged on the same layer.
With reference to the fourth possible implementation manner of the first aspect, in a seventh possible implementation manner, the control line is electrically connected to the first common electrode line or the second common electrode line in the area.
With reference to the seventh possible implementation manner of the first aspect, in an eighth possible implementation manner, the control lines and the data lines are arranged in parallel and in the same layer.
With reference to the fourth possible implementation manner of the first aspect, in a ninth possible implementation manner, the first active layer and the second active layer are disposed in the same layer and are made of the same material.
With reference to the second possible implementation manner of the first aspect, in a tenth possible implementation manner, the first gate is in a stripe shape, extends to the peripheral wiring area, and provides a signal to the first gate through a trace disposed in the peripheral wiring area.
In an eleventh possible implementation manner of the first aspect, the control lines corresponding to the regions immediately adjacent to the peripheral wiring region are disposed in the peripheral wiring region.
In a second aspect, a display device is provided, which includes the array substrate of the first aspect.
The embodiment of the utility model provides an array substrate and display device through dividing the display area into a plurality of regions, makes all public electrode electric connections as an organic whole in every region to make the public electrode in different regions pass through the switch unit and connect, can be selective with the public electrode electric connection in the different regions. Based on this, the common electrodes in the common electrode voltage consistent area can be electrically connected through the control switch unit, and corresponding voltages are respectively input to the common electrodes in the electrically connected areas through the control lines, so that compensation modulation of the common electrodes in different electrically connected areas can be realized, the Feedthough voltages of all the areas are consistent, the voltages of all the common electrodes are enabled to be uniform on the whole, and the problems of flicker, residual image and the like in the prior art are solved. In addition, all the common electrodes in each area are separately arranged in different pixels, so that the coupling effect between the common electrodes and the data lines can be reduced, the effect of pulling the common electrode voltage by the data line voltage can be minimized, and the picture greening phenomenon can be improved.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, it is obvious that the drawings in the following description are only some embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to these drawings without creative efforts.
Fig. 1 is a first schematic structural diagram of an array substrate according to an embodiment of the present invention;
fig. 2 is a schematic structural diagram of an array substrate according to an embodiment of the present invention;
fig. 3 is a schematic structural diagram three of an array substrate according to an embodiment of the present invention;
fig. 4 is a schematic structural diagram of an array substrate according to an embodiment of the present invention;
FIG. 5 is a schematic sectional view of the direction A-A and the direction B-B in FIG. 4.
Reference numerals:
01-a display area; 02-peripheral wiring area; 10-region; 101-a common electrode; 102-first common electrode lines; 103-a second common electrode line; 20-a switching unit; 201-a first thin film transistor; 2011-first gate; 2012-a first source; 2013-a first drain; 30-a control line; 50-a second thin film transistor; 60-pixel electrodes; 70-a grid line; 80-data line.
Detailed Description
The technical solutions in the embodiments of the present invention will be described clearly and completely with reference to the accompanying drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only some embodiments of the present invention, not all embodiments. Based on the embodiments in the present invention, all other embodiments obtained by a person skilled in the art without creative work belong to the protection scope of the present invention.
Unless otherwise defined, technical or scientific terms used herein shall have the ordinary meaning as understood by those skilled in the art. The use of "first," "second," and similar terms in the description and in the claims does not indicate any order, quantity, or importance, but rather is used to distinguish one element from another. The terms "connected," "coupled," or "connected," and the like, are not restricted to physical or mechanical connections, but may include electrical connections, whether direct or indirect.
The embodiment of the present invention provides an array substrate, as shown in fig. 1, the array substrate includes a display area 01 and a peripheral wiring area 02, wherein the display area 01 is divided into a plurality of areas 10; the common electrodes 101 in all the pixels included in the same region 10 are electrically coupled as one body; the common electrode 101 between the different regions 10 is connected through the switching unit 20; the array substrate further comprises a control line 30 corresponding to each region 10, and the control line 30 is used for providing a voltage signal for the common electrode 101 in the region 10.
First, the manner in which the common electrode 101 is electrically coupled in each region 10 is not limited.
Second, the position where the switch unit 20 is provided is not limited, and is preferably set at a position where the display is not affected. Further, the structure of the switching unit 20 is not limited as long as the common electrodes 101 in the different regions 10 connected thereto can be electrically coupled.
Third, for the region 10 near the peripheral wiring region 02, it is preferable that the control line 30 corresponding thereto be provided in the peripheral wiring region 02 to reduce the influence on the display.
The embodiment of the utility model provides an array substrate, through dividing the display area 01 into a plurality of regional 10, make all public electrode 101 electric couplings in every regional 10 as an organic whole to make the public electrode 101 in the different regions 10 connect through switch unit 20, can be selective with the public electrode 101 electric coupling in the different regions 10. Based on this, the common electrodes 101 in the areas where the voltages of the common electrodes 101 are consistent can be electrically connected by controlling the switch unit 20, and corresponding voltages are respectively input to the common electrodes 101 in these electrically connected areas through the control line 30, so that compensation modulation of the common electrodes 101 in different electrically connected areas 10 can be realized, and the feedthrough voltages of all the areas are consistent, thereby making the voltages of all the common electrodes 101 uniform as a whole, and further improving the problems of flicker, afterimage and the like in the prior art. In addition, since all the common electrodes 101 in each region 10 are separately disposed in different pixels, the coupling effect between the common electrodes 101 and the data lines can be reduced, so that the effect of pulling the voltage of the common electrodes 101 by the voltage of the data lines can be minimized, and the picture greening phenomenon can be improved.
Alternatively, as shown in fig. 2 and 3, the common electrodes 101 in the same region 10 are electrically coupled by a first common electrode line 102 disposed along a first direction and/or a second common electrode line 103 disposed along a second direction; wherein the first direction and the second direction intersect.
Specifically, as shown in fig. 2, if each region 10 includes only at least two common electrodes 101 in one row along the first direction, the common electrodes 101 in each region 10 may be electrically coupled only by the first common electrode lines 102.
Of course, if each region 10 includes only at least two common electrodes 101 in one column along the second direction, the common electrodes 101 in each region 10 may be electrically coupled only by the second common electrode lines 103.
As shown in fig. 3, if each of the regions 10 includes a plurality of common electrodes 101 arrayed in a first direction and a second direction, the common electrodes 101 in each of the regions 10 may be electrically coupled in the first direction by first common electrode lines 102 and in the second direction by second common electrode lines 103.
It should be noted that, in the embodiment of the present invention, the first direction is taken as a horizontal direction, and the second direction is taken as a vertical direction for indication, but the embodiment of the present invention is not limited thereto.
Based on the above, as shown in fig. 4 and 5, preferably, the switching unit 20 may include a first thin film transistor 201, and the first thin film transistor 201 includes a first gate electrode 2011, a first active layer (not shown), a first source electrode 2012 and a first drain electrode 2013; wherein the first source 2012 and the first drain 2013 are electrically coupled to the common electrode 101 in different regions 10, respectively.
In the embodiment of the present invention, when power is supplied to the first gate 2011, the first source 2012 and the first drain 2013 can be turned on, so that the first source 2012 and the first drain 2013 are electrically connected to the common electrode 101 in the different regions 10.
First, the shape of the first gate 2011 and the manner of feeding power to the first gate 2011 are not limited as long as the first source 2012 and the first drain 2013 can be turned on by the first gate 2011.
Preferably, the first gate 2011 has a bar shape, and the first gate 2011 extends to the peripheral wiring region 02, and the first gate 2011 is provided with a signal through a trace disposed in the peripheral wiring region 02. Thus, the manufacturing process can be simplified.
Secondly, since the common electrodes 101 in any one of the regions 10 are electrically connected into a whole, for the first source 2012 and the first drain 2013, all the common electrodes 101 in the two corresponding regions 10 can be electrically connected as long as the common electrodes are electrically connected with one of the first common electrode lines 102, the second common electrode lines 103, or the common electrodes 101 in the corresponding region 10.
Further preferably, as shown in fig. 4, the first thin film transistor 201 is disposed between adjacent rows or columns of pixels in different regions 10.
Thus, the influence of the first thin film transistor 201 on the aperture ratio of the array substrate can be avoided.
Further, as shown in fig. 4, the pixel further includes a second thin film transistor 50 and a pixel electrode 60; the second thin film transistor 50 includes a second gate electrode, a second active layer, a second source electrode, and a second drain electrode (none of which are shown); a second gate electrode is electrically coupled to the gate line 70, a second source electrode is electrically coupled to the data line 80, and a second drain electrode is electrically coupled to the pixel electrode 60.
The second thin film transistor 50 may be an amorphous silicon thin film transistor, a low-temperature polysilicon thin film transistor, an oxide thin film transistor, an organic thin film transistor, or the like. The second thin film transistor 50 may be a top gate type or a bottom gate type.
On this basis, referring to fig. 4, when the array substrate includes first common electrode lines 102 disposed along a first direction and second common electrode lines 103 disposed along a second direction, the first common electrode lines 102 are preferably parallel to the gate lines 70; the first gate electrode 2011, the second gate electrode, the gate line 70, and the first common electrode line 102 are disposed at the same layer.
That is, the first gate electrode 2011, the second gate electrode, the gate line 70, and the first common electrode line 102 are formed through one patterning process, so that an increase in the number of patterning processes can be prevented.
Here, in order to avoid the influence of the first common electrode line 102 on the aperture ratio of the array substrate, it may be disposed at a position of the display area 01 where the pixel electrode 60 is not disposed.
Further preferably, the first source 2012 and the first drain 2013 are disposed in the same layer as the pixel electrode 60; alternatively, the first source 2012 and the first drain 2013 are disposed in the same layer as the second source and the second drain.
The first source electrode 2012 and the first drain electrode 2013 are both strip-shaped, one end of each of the strip-shaped first source electrode 2012 and the strip-shaped first drain electrode 2013 is connected to the first active layer of the first thin film transistor 201, and the other end of each of the strip-shaped first source electrode 2012 and the strip-shaped first drain electrode 2013 is electrically connected to the first common electrode lines 102 in different regions 10.
That is, the first source electrode 2012, the first drain electrode 2013 and the pixel electrode 60 are formed by one patterning process, or the first source electrode 2012 and the first drain electrode 2013 and the second source electrode and the second drain electrode are formed by one patterning process. This can avoid an increase in the number of patterning processes.
Further, the first common electrode line 102 is disposed between the first thin film transistor 201 and the pixel electrode 60.
Preferably, referring to fig. 4, the second common electrode line 103 is parallel to the data line 80, and the second common electrode line 103 is disposed at the same layer as the data line 80, the second source electrode and the second drain electrode; alternatively, the second common electrode line 103 is disposed at the same layer as the pixel electrode 60.
That is, the second common electrode line 103 and the data line 80, the second source electrode and the second drain electrode are formed through one patterning process, or the second common electrode line 103 and the pixel electrode 60 are formed through one patterning process. This can avoid an increase in the number of patterning processes.
Preferably, as shown in fig. 4, the control line 30 is electrically coupled to the first common electrode line 102 in the present region 10 to reduce the influence on the display. Of course, the control line 30 may also be electrically coupled to the second common electrode line 103 in the present region 10.
It is further preferred that the control lines 30 are arranged parallel and in the same layer as the data lines 80.
That is, the control line 30 and the data line 80 are formed through one patterning process. This can avoid an increase in the number of patterning processes.
Here, the control line 30 may be disposed between adjacent pixel electrodes 60 to avoid affecting the aperture ratio.
Preferably, the first semiconductor active layer and the second semiconductor active layer are arranged in the same layer and are made of the same material.
That is, the first semiconductor active layer and the second semiconductor active layer are formed through one patterning process. This can avoid an increase in the number of patterning processes.
The embodiment of the utility model provides a still provide a display device, including foretell array substrate.
The display device may be a liquid crystal display device, including a liquid crystal display panel, and may be a product or a component having any display function, such as a liquid crystal display, a liquid crystal television, a digital photo frame, a mobile phone, a tablet computer, and the like.
The embodiment of the present invention further provides a method for manufacturing the array substrate, as shown in fig. 1, the array substrate includes a display area 01 and a peripheral wiring area 02, wherein the display area 01 is divided into a plurality of areas 10; the preparation method comprises the following steps: forming a common electrode 101 in each pixel, the common electrodes 101 in all pixels included in the same region 10 being electrically coupled as one body, and forming a switching unit 20 that connects the common electrodes 101 between the different regions 10; a control line 30 corresponding to each region 10 is formed, and the control line 30 is used to supply a voltage signal to the common electrode 101 in the present region.
The embodiment of the utility model provides a preparation method of array substrate through dividing display area 01 into a plurality of regional 10, makes all common electrode 101 electric couplings in every regional 10 as an organic whole to make the common electrode 101 in different regional 10 connect through switch unit 20, can be selective with the common electrode 101 electric coupling in different regional 10. Based on this, the common electrodes 101 in the areas where the voltages of the common electrodes 101 are consistent can be electrically connected by controlling the switch unit 20, and corresponding voltages are respectively input to the common electrodes 101 in the areas 10 which are electrically connected by the control line 30, so that compensation modulation of the common electrodes 101 in different areas 10 which are electrically connected can be realized, and the feedhigh voltages of all the areas are consistent, thereby making the voltages of all the common electrodes 101 uniform as a whole, and further improving the problems of flicker, afterimage and the like in the prior art. In addition, since all the common electrodes 101 in each region 10 are separately disposed in different pixels, the coupling effect between the common electrodes 101 and the data lines can be reduced, so that the effect of pulling the voltage of the common electrodes 101 by the voltage of the data lines can be minimized, and the picture greening phenomenon can be improved.
Preferably, as shown in fig. 4 and 5, the common electrode 101 is formed in each pixel, and the common electrodes 101 in all the pixels included in the same region 10 are electrically connected to one another, which may be implemented as follows: forming a common electrode 101 located at each pixel, and a first common electrode line 102 along a first direction and a second common electrode line 103 along a second direction, the common electrodes 101 in the same region 10 being electrically coupled together by the first common electrode line 102 and/or the second common electrode line 103; wherein the first direction and the second direction intersect;
the switch unit 20 is formed by the following steps: forming a first thin film transistor 201 between adjacent rows or columns of pixels in different regions 10, the first thin film transistor 201 including a first gate 2011, a first active layer, a first source 2012 and a first drain 2013; wherein the first source 2012 and the first drain 2013 are electrically coupled to the common electrode 101 in different regions 10, respectively.
On this basis, the method further comprises the following steps: a second thin film transistor 50 and a pixel electrode 60 in each pixel are formed, the second thin film transistor 50 including a second gate electrode, a second active layer, a second source electrode, and a second drain electrode, and a gate line 70 electrically coupled to the second gate electrode and a data line 80 electrically coupled to the second source electrode are formed.
The first common electrode line 102 is parallel to the gate line 70, and the first gate 2011, the second gate, the gate line 70 and the first common electrode line 102 are formed by the same patterning process.
It should be noted that, first, the first gate 2011 may have a bar shape, and the first gate 2011 extends to the peripheral wiring region 02, and provides a signal for the first gate 2011 through a trace disposed in the peripheral wiring region 02.
Second, for the region 10 near the peripheral wiring region 02, it is preferable that the control line 30 corresponding thereto be formed in the peripheral wiring region 02 to reduce the influence on the display.
In addition, the control line 30 is preferably electrically coupled to the first common electrode line 102 or the second common electrode line 103 in the present region 10 to reduce the influence on the display.
In the embodiment of the present invention, since the first gate 2011, the second gate, the gate line 70 and the first common electrode line 102 are formed by the same patterning process, the number of patterning processes can be reduced, and the cost can be saved.
Further preferably, the first thin film transistor 201 is formed in synchronization with the second thin film transistor 50 and the pixel electrode 60; the first source electrode 2012 and the first drain electrode 2013 are formed by the same patterning process as the pixel electrode 60; or the first source 2012 and the first drain 2013 are formed by the same patterning process as the second source and the second drain; the first source electrode 2012 and the first drain electrode 2013 are both strip-shaped, and one end of each of the strip-shaped first source electrode 2012 and the strip-shaped first drain electrode 2013 is connected to the first active layer of the first thin film transistor 201, and the other end of each of the strip-shaped first source electrode 2012 and the strip-shaped first drain electrode 2013 is electrically connected to the first common electrode lines 102 in the different.
Thus, an increase in the number of patterning processes can be avoided.
Specifically, the first thin film transistor 201 is formed in synchronization with the second thin film transistor 50 and the pixel electrode 60, and may be: a first gate 2011 and a second gate are formed by a one-time patterning process; forming a first active layer and a second active layer through a one-time composition process; forming a second source electrode and a second drain electrode through a one-time composition process; the first source electrode 2012, the first drain electrode 2013 and the pixel electrode 60 are formed through a single patterning process.
Alternatively, the first thin film transistor 201 is formed in synchronization with the second thin film transistor 50 and the pixel electrode 60, and may be: a first gate 2011 and a second gate are formed by a one-time patterning process; forming a first active layer and a second active layer through a one-time composition process; forming a first source electrode 2012, a first drain electrode 2013, a second source electrode and a second drain electrode through a one-time composition process; the pixel electrode 60 is formed through a one-time patterning process.
Further preferably, as shown in fig. 4, the second common electrode line 103 is parallel to the data line 80, and the second common electrode line 103 and the data line 80, the second source electrode and the second drain electrode are formed through the same patterning process, or the second common electrode line 103 and the pixel electrode 60 are formed through the same patterning process. This can avoid an increase in the number of patterning processes.
Preferably, as shown in fig. 4, the control line 30 is parallel to the data line 80 and formed through the same patterning process. This can avoid an increase in the number of patterning processes.
The embodiment of the utility model provides a still provide a control method of above-mentioned array substrate, include: inputting signals to the switch units 20 in a predetermined range of the array substrate to electrically connect the common electrodes 101 in different regions 10 in the predetermined range; a common voltage signal is input to the common electrode 101 within the predetermined range through at least one control line 30 corresponding to the predetermined range.
First, the predetermined range includes a plurality of regions 10, and the voltage of the common electrode 101 is uniform in the predetermined range.
Second, the number of the predetermined ranges is not limited, and when the predetermined ranges are two or more, the common voltage signal may be input to the common electrode 101 within the predetermined range through the control line 30 corresponding to the predetermined ranges, respectively.
Third, a signal is input to the switching unit 20 to enable the switching unit 20 to be turned on, thereby electrically coupling the common electrodes 101 in the different regions 10.
The embodiment of the utility model provides a control method of array substrate, can be according to the whole distribution condition of common electrode voltage in the array substrate, the different predetermined range is drawn together, the voltage of common electrode 101 in all regions 10 in every predetermined range is unanimous, based on this, through making all common electrode 101 electric connections in the predetermined range get up, and input corresponding common voltage signal to common electrode 101 in this predetermined range through control line 30, alright realize the compensation modulation to common electrode 101 in this predetermined range, on this basis, because common voltage signal is inputted to control line 30 that all accessible correspond with it in every predetermined range, therefore, can make all regional Feedthough voltages unanimous, thereby make all common electrode 101's voltage even on the whole, and then improve scintillation, the afterimage scheduling problem that exists among the prior art.
Preferably, in the case that the switching unit 20 includes the first thin film transistor 201, the input of the signal to the switching unit 20 within the predetermined range of the array substrate may specifically be: a signal is input to the first gate 2011 of the first thin film transistor 201 within a predetermined range of the array substrate.
In this way, when a signal is input to the first gate 2011, the first source 2012 and the first drain 2013 are turned on, so that the common electrode 101 in different regions 10 of the first thin film transistor 201 is electrically connected.
Preferably, the common voltage signal may be input to the common electrode 101 within the predetermined range through all the control lines 30 corresponding to the predetermined range. That is, the same common voltage signal is input to all the control lines 30 corresponding to all the regions 10 included in the predetermined range.
In this way, the voltage of all the common electrodes 101 can be further ensured to be uniform.
The above description is only for the specific embodiments of the present invention, but the protection scope of the present invention is not limited thereto, and any person skilled in the art can easily think of the changes or substitutions within the technical scope of the present invention, and all should be covered within the protection scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the protection scope of the claims.
Claims (13)
1. The array substrate is characterized by comprising a display area and a peripheral wiring area, wherein the display area is divided into a plurality of areas;
common electrodes in all pixels included in the same region are electrically connected into a whole; the common electrodes between different regions are connected through a switch unit;
the array substrate further comprises control lines corresponding to the regions, and the control lines are used for providing voltage signals for the common electrodes in the regions.
2. The array substrate of claim 1, wherein the common electrodes in the same region are electrically coupled through a first common electrode line disposed along a first direction and/or a second common electrode line disposed along a second direction;
wherein the first direction and the second direction intersect.
3. The array substrate of claim 1 or 2, wherein the switching unit comprises a first thin film transistor comprising a first gate electrode, a first active layer, a first source electrode, and a first drain electrode;
the first source electrode and the first drain electrode are electrically coupled with the common electrode in different regions, respectively.
4. The array substrate of claim 3, wherein the first thin film transistors are disposed between adjacent rows or columns of pixels in different ones of the regions.
5. The array substrate of claim 4, wherein the pixel comprises a second thin film transistor and a pixel electrode, the second thin film transistor comprising a second gate electrode, a second active layer, a second source electrode, and a second drain electrode; the second gate electrode is electrically connected with the gate line, the second source electrode is electrically connected with the data line, and the second drain electrode is electrically connected with the pixel electrode;
the array substrate comprises a first common electrode line arranged along a first direction and a second common electrode line arranged along a second direction;
wherein the first common electrode line is parallel to the gate line;
the first gate electrode, the second gate electrode, the gate line and the first common electrode line are disposed on the same layer.
6. The array substrate of claim 5, wherein the first source electrode and the first drain electrode are disposed on the same layer as the pixel electrode; or,
the first source electrode and the first drain electrode are arranged on the same layer as the second source electrode and the second drain electrode;
the first source electrode and the first drain electrode are both strip-shaped, one end of each strip-shaped source electrode is connected with the first active layer of the first thin film transistor, and the other end of each strip-shaped source electrode is electrically connected with the first common electrode line in different areas.
7. The array substrate of claim 5, wherein the second common electrode line is parallel to the data line, and the second common electrode line is disposed on the same layer as the data line, the second source electrode and the second drain electrode; or,
the second common electrode line and the pixel electrode are arranged on the same layer.
8. The array substrate of claim 5, wherein the control line is electrically coupled to the first common electrode line or the second common electrode line in the current region.
9. The array substrate of claim 8, wherein the control lines are disposed in parallel and in the same layer as the data lines.
10. The array substrate of claim 5, wherein the first active layer and the second active layer are disposed in the same layer and are the same material.
11. The array substrate of claim 3, wherein the first gate is bar-shaped, and the first gate extends to the peripheral wiring region, and the first gate is provided with a signal through a trace disposed in the peripheral wiring region.
12. The array substrate of claim 1, wherein the control lines corresponding to the regions immediately adjacent to the peripheral wiring region are disposed in the peripheral wiring region.
13. A display device comprising the array substrate according to any one of claims 1 to 12.
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201520945361.3U CN205139542U (en) | 2015-11-24 | 2015-11-24 | Array baseplate and display device |
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| Application Number | Priority Date | Filing Date | Title |
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| CN201520945361.3U CN205139542U (en) | 2015-11-24 | 2015-11-24 | Array baseplate and display device |
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| CN205139542U true CN205139542U (en) | 2016-04-06 |
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| CN201520945361.3U Expired - Fee Related CN205139542U (en) | 2015-11-24 | 2015-11-24 | Array baseplate and display device |
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| CN (1) | CN205139542U (en) |
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN105278194A (en) * | 2015-11-24 | 2016-01-27 | 京东方科技集团股份有限公司 | Array substrate and preparation method thereof, and display apparatus and control method thereof |
| CN111128025A (en) * | 2019-12-30 | 2020-05-08 | 厦门天马微电子有限公司 | Array substrate, display panel and display device |
| CN112327530A (en) * | 2020-12-01 | 2021-02-05 | 深圳市华星光电半导体显示技术有限公司 | Display panel and display device |
| CN114280854A (en) * | 2021-12-17 | 2022-04-05 | 惠科股份有限公司 | Display panel and display |
| WO2022067932A1 (en) * | 2020-09-29 | 2022-04-07 | Tcl华星光电技术有限公司 | Partitioned display structure, display panel, and organic light emitting diode display panel |
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2015
- 2015-11-24 CN CN201520945361.3U patent/CN205139542U/en not_active Expired - Fee Related
Cited By (11)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN105278194A (en) * | 2015-11-24 | 2016-01-27 | 京东方科技集团股份有限公司 | Array substrate and preparation method thereof, and display apparatus and control method thereof |
| WO2017088449A1 (en) * | 2015-11-24 | 2017-06-01 | Boe Technology Group Co., Ltd. | Array substrate, semiconductor device containing the same, control method thereof, and fabrication method thereof |
| US10180612B2 (en) | 2015-11-24 | 2019-01-15 | Boe Technology Group Co., Ltd | Array substrate, semiconductor device containing the same, control method thereof, and fabrication method thereof |
| CN105278194B (en) * | 2015-11-24 | 2019-06-07 | 京东方科技集团股份有限公司 | A kind of array substrate and preparation method thereof, display device and its control method |
| CN111128025A (en) * | 2019-12-30 | 2020-05-08 | 厦门天马微电子有限公司 | Array substrate, display panel and display device |
| CN111128025B (en) * | 2019-12-30 | 2021-11-26 | 厦门天马微电子有限公司 | Array substrate, display panel and display device |
| WO2022067932A1 (en) * | 2020-09-29 | 2022-04-07 | Tcl华星光电技术有限公司 | Partitioned display structure, display panel, and organic light emitting diode display panel |
| US11984073B2 (en) | 2020-09-29 | 2024-05-14 | Tcl China Star Optoelectronics Technology Co., Ltd. | Partitioned display structure, display panel, and organic light-emitting diode display panel |
| CN112327530A (en) * | 2020-12-01 | 2021-02-05 | 深圳市华星光电半导体显示技术有限公司 | Display panel and display device |
| CN114280854A (en) * | 2021-12-17 | 2022-04-05 | 惠科股份有限公司 | Display panel and display |
| US12019340B2 (en) | 2021-12-17 | 2024-06-25 | HKC Corporation Limited | Display panel and display |
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