CN208189570U - A kind of semiconductor memory structure - Google Patents
A kind of semiconductor memory structure Download PDFInfo
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- CN208189570U CN208189570U CN201820792400.4U CN201820792400U CN208189570U CN 208189570 U CN208189570 U CN 208189570U CN 201820792400 U CN201820792400 U CN 201820792400U CN 208189570 U CN208189570 U CN 208189570U
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Abstract
The utility model provides a kind of semiconductor memory structure, the semiconductor memory structure has the wordline groove of multiplex, wordline is to be formed based on wordline groove in the substrate, since wordline groove is connected to by the first different wordline groove of depth with the second wordline groove level, therefore wordline is asymmetric flush type, using the embedded type word line as the grid of metal-oxide-semiconductor, the distance between metal-oxide-semiconductor source electrode and drain electrode can be increased, so that metal-oxide-semiconductor has longer channel, it effectively prevent short-channel effect.The utility model can increase the effective distance between wordline and wordline under same wordline density, to reduce the coupling between wordline and wordline.The bottom end offset direction of adjacent two wordline is on the contrary, can make the coupling between transistor be substantially reduced in the utility model.
Description
Technical field
The utility model belongs to IC manufacturing field, is related to a kind of semiconductor memory structure.
Background technique
As semiconductor storage unit (such as dynamic random access memory (DRAM)) becomes highly integrated, unit cell exists
Area in semiconductor substrate can correspondingly be gradually reduced, and include the channel in metal-oxide semiconductor (MOS) (MOS) transistor
Length can be also gradually reduced, and the reduction of channel length easily causes the generation of short-channel effect.In order to maintain semiconductor storage unit
It is highly integrated, need to take measures to limit short-channel effect.
Embedded type word line (alternatively referred to as buried gate) provides one kind newly to increase the integration density of semiconductor devices
Selection.Embedded type word line refers to the inside that wordline is embedded in semiconductor substrate, can reduce significantly in wordline and bit line
Between parasitic capacitance, significantly improve semiconductor devices voltage read operation reliability.Fig. 1 is shown as a kind of active area
With the plane figure of wordline array, Fig. 2 is shown as the A-A ' of Fig. 1 to sectional view, wherein isolation structure 101, which is formed in, partly leads
In body substrate 102, multiple active areas 103 are defined in the semiconductor substrate 102, and a plurality of wordline 104 is embedded to semiconductor substrate 102
In, and active area 103 and isolation structure 101 are passed through, matcoveredn 105 is formed above wordline 104.From Figure 2 it can be seen that existing bury
Enter formula wordline using symmetrical structure.
With further increasing for integrated level, also start to face using the semiconductor memory structure of buried gate wordline
Therefore how the problem of short-channel effect provides a kind of new semiconductor memory structure, to prevent using buried gate word
There is short-channel effect in the semiconductor memory structure of line, becomes those skilled in the art's important technology urgently to be resolved and asks
Topic.
Utility model content
In view of the foregoing deficiencies of prior art, the purpose of this utility model is to provide a kind of semiconductor memory knots
Structure, it is highly integrated with device for solving, the existing semiconductor memory structure using buried gate word line structure without
Method effectively prevent the problem of short-channel effect.
In order to achieve the above objects and other related objects, the utility model provides a kind of semiconductor memory structure, comprising:
Substrate；
Wordline groove is formed in the substrate, deeply comprising the first wordline groove with the first depth and with second
Second wordline groove of degree, the first wordline groove and the second wordline groove level connection, first depth are greater than
Second depth；
Wordline is formed by connecting by the first wordline portion and the second wordline portion, and first wordline portion is formed in first word
In line groove, second wordline portion is formed in the second wordline groove, and the wordline is deviateed in the bottom end of the wordline
Central plane, wherein the central plane of the wordline is defined as across the end face center line of the wordline length direction and vertical
Plane in the wordline top surface, the bottom end of the wordline are located at the bottom end of the first wordline groove.
Optionally, the junction in first wordline portion and second wordline portion has re-entrant angle in one.
Optionally, the bottom end offset direction of adjacent two wordline is opposite.
Optionally, the semiconductor memory further includes the isolation structure being formed in the substrate, the isolation structure
Multiple active areas are defined in the substrate, and the wordline passes through the active area and the isolation structure.
Optionally, at least one described active area is passed through by two wordline.
As described above, the semiconductor memory structure of the utility model, has the advantages that (1) the utility model
Semiconductor memory structure have the wordline groove of multiplex, wordline is to be formed based on wordline groove in the substrate, due to word
Line groove is connected to by the first different wordline groove of depth with the second wordline groove level, therefore wordline is asymmetric embedment
Formula can increase the distance between metal-oxide-semiconductor source electrode and drain electrode using the embedded type word line as the grid of metal-oxide-semiconductor, so that
Metal-oxide-semiconductor has longer channel, effectively prevent short-channel effect；(2) the utility model can increase under same wordline density
Add the effective distance between wordline and wordline, to reduce the coupling between wordline and wordline；(3) adjacent in the utility model
The bottom end offset direction of two wordline is on the contrary, make the increase of the distance between a part of adjacent two wordline bottom ends, a part of phase
The distance between adjacent two wordline bottom ends reduce, and test result shows to reduce the distance between adjacent two wordline bottom ends
The case where, device performance influence it is unobvious, and for the distance between adjacent two wordline bottom ends increase the case where, transistor it
Between coupling be substantially reduced.
Detailed description of the invention
Fig. 1 is shown as the plane figure of a kind of active area and wordline array in the prior art.
Fig. 2 is shown as the A-A ' of Fig. 1 to sectional view.
Fig. 3 is shown as the process flow chart of the wordline manufacturing method of the semiconductor memory structure of the utility model.
The surface that the wordline manufacturing method that Fig. 4 is shown as the semiconductor memory structure of the utility model provides is formed with lining
The diagrammatic cross-section of the substrate of bottom protective layer.
Fig. 5 is shown as the planar cloth of active area in the semiconductor memory structure of the utility model, wordline and the first opening
Office's figure.
The wordline manufacturing method that Fig. 6-Fig. 7 is shown as the semiconductor memory structure of the utility model forms multiple first and opens
Schematic diagram of the mouth in the substrate protective layer.
The wordline manufacturing method that Fig. 8 is shown as the semiconductor memory structure of the utility model forms a hard mask layer in institute
It states in the first opening and the schematic diagram of the substrate protective layer surface.
The wordline manufacturing method that Fig. 9 is shown as the semiconductor memory structure of the utility model forms a photoresist layer described
Hard mask layer surface, and form schematic diagram of multiple second openings in the photoresist layer.
Figure 10 is shown as the wordline manufacturing method of the semiconductor memory structure of the utility model with the photoresist layer, described
Collectively as exposure mask, etching obtains the signal of multiple wordline grooves in the substrate for hard mask layer and the substrate protective layer
Figure.
The wordline manufacturing method that Figure 11-Figure 13 is shown as the semiconductor memory structure of the utility model is based on the wordline
Groove forms schematic diagram of a plurality of wordline in the substrate.
The wordline manufacturing method that Figure 14 is shown as the semiconductor memory structure of the utility model forms wordline protective layer and exists
The schematic diagram on the wordline surface.
Component label instructions
101 isolation structures
102 semiconductor substrates
103 active areas
104 wordline
105 protective layers
S1~S6 step
201 substrates
202 substrate protective layers
203 isolation structures
204 active areas
205 hardmask materials
206 photoresist layer
207 first openings
208 substrate protective layer units
209 hard mask layers
210 photoresist layers
211 second openings
212 photoresist units
213 first occlusion parts
214 second occlusion parts
215 wordline grooves
2151 first wordline concave parts
2152 second wordline concave parts
216 wordline
2161 first wordline portions
2162 second wordline portions
217 gate oxides
218 diffusion barrier layers
219 conductive materials
220 wordline protective layers
Re-entrant angle in θ
W1The width of first opening
W2, W4The width of photoresist unit
W3The width of substrate protective layer unit
The central plane of MM ' wordline
NN ' wordline top surface
Specific embodiment
Illustrate the embodiments of the present invention below by way of specific specific example, those skilled in the art can be by this theory
Content disclosed by bright book understands other advantages and effect of the utility model easily.The utility model can also be by addition
Different specific embodiments are embodied or practiced, and the various details in this specification can also be based on different viewpoints and answer
With carrying out various modifications or alterations under the spirit without departing from the utility model.
Fig. 3 is please referred to Figure 14.It should be noted that diagram provided in the present embodiment only illustrates this in a schematic way
The basic conception of utility model is only shown with related component in the utility model rather than when according to actual implementation in schema then
Component count, shape and size are drawn, when actual implementation kenel, quantity and the ratio of each component can arbitrarily change for one kind
Become, and its assembly layout kenel may also be increasingly complex.
Embodiment one
The utility model provides a kind of semiconductor memory structure, please refers to Figure 14, is shown as the semiconductor memory knot
The schematic cross-sectional view of structure, including substrate 201, wordline groove 215 and wordline 216, wherein 215 shape of wordline groove
In substrate 201 described in Cheng Yu, comprising the first wordline groove 2151 with the first depth and with the second wordline of the second depth
Groove 2152, the first wordline groove 2151 with the second wordline groove 2152 is horizontal is connected to (referring to Figure 10), described the
One depth is greater than second depth, and the wordline 216 is formed by connecting by the first wordline portion 2161 and the second wordline portion 2162 (joins
See Figure 13), first wordline portion 2161 is formed in the first wordline groove 2151, and second wordline portion 2162 is formed
In the second wordline groove 2152, the central plane MM ' of wordline groove is deviateed in the bottom end of the wordline groove 215, herein
The central plane MM ' of wordline is defined as the end face center line across the wordline length direction and perpendicular to the wordline top surface
The plane of NN ', the bottom end of the wordline are located at the bottom end of the first wordline groove.
Specifically, the junction in first wordline portion 2161 and second wordline portion 2062 has re-entrant angle θ in one, institute
Metal-oxide-semiconductor can be made when grid of the embedded type word line as metal-oxide-semiconductor by stating the surface area that interior re-entrant angle increases the wordline 216
The distance between source electrode and drain electrode increase, to have longer channel, effectively prevent short-channel effect.And the utility model
The effective distance between wordline and wordline can increased under same wordline density, to reduce the coupling between wordline and wordline
It closes.
In the present embodiment, the bottom end offset direction of adjacent two wordline 216 is on the contrary, make a part of adjacent two wordline bottoms
The distance between end increases, and the distance between a part of adjacent two wordline bottom ends reduce, and test result shows for adjacent two
The case where the distance between wordline bottom end reduces, device performance influence it is unobvious, and between adjacent two wordline bottom ends
Distance the case where increasing, the coupling between transistor is substantially reduced.As an example, showing each word using arrow in Figure 14
The offset direction of line.
The semiconductor memory structure of the utility model can be adapted for dynamic random access memory, referring to Fig. 5, aobvious
Be shown as a kind of plane figure of the semiconductor memory structure of the utility model, Figure 14 presentation be in Fig. 5 BB ' to section.Its
In, the semiconductor memory structure further includes the isolation structure 203 being formed in the substrate 201, the isolation structure 203
Multiple active areas 204 are defined in the substrate 201, the wordline 216 passes through the active area 204 and the isolation structure
203.As an example, at least one described active area 204 is passed through by two wordline 216.The isolation structure 203 can be with
It is shallow trench isolation (STI).
It should be noted that plane figure shown in fig. 5 is merely illustrative, in other embodiments, active area can also be adopted
It, can be in addition, wordline manufactured by the utility model is applicable not only to dynamic random access memory with other arrangement modes
Applied to other semiconductor devices using embedded type word line, the protection scope of the utility model should not be excessively limited herein.
Embodiment two
The present embodiment provides a kind of methods to ask for manufacturing the wordline of semiconductor memory structure described in embodiment one
Refering to Fig. 3, it is shown as the process flow chart of this method.
Referring initially to Fig. 4, step S1 being executed: a substrate 201 being provided, 201 surface of substrate is formed with substrate guarantor
Sheath 202.
Specifically, the substrate 201 can be used but be not limited to silicon (Si), germanium (Ge), germanium silicon (SiGe), silicon-on-insulator
(SOI) the common semiconductor substrate materials such as.The material selection of the substrate protective layer 202 need to make its etch rate with it is subsequent
The etch rate of the hard mask layer 209 of formation is different, so that the asymmetric wordline for obtaining multiplex in the substrate 201 is recessed
Slot.
As an example, being more formed with isolation structure 203 in the substrate 201, the isolation structure 203 is in the substrate
Multiple active areas 204 are defined in 201.The isolation structure 204 can be shallow trench isolation (STI) or other common isolation
Structure.
As an example, Fig. 5 shows a kind of plane figure of active area 204, isolation structure 203, Fig. 4 and subsequent each step
The sectional view presented is illustrated as the BB ' in Fig. 5 to section.The first opening 207 being subsequently formed and word are also shown in Fig. 5
The plane figure of line 216, it is seen then that the wordline 216 being subsequently formed passes through the active area 204 and the isolation structure 203.This reality
It applies in example, at least one described active area 204 is passed through by two wordline 216.
It should be noted that plane figure shown in fig. 5 is merely illustrative, in other embodiments, according to semiconductor memory
The parameter request of device, active area can also use other arrangement modes, should not excessively limit the protection model of the utility model herein
It encloses.
Referring next to Fig. 6 to Fig. 7, step S2 is executed: forming multiple first openings 207 in the substrate protective layer 202
In.
Specifically, about 207 first opening runs through the substrate protective layer 202, to be formed by described first
Multiple substrate protective layer units 208 at 207 interval of opening.As shown in figure 5, if subsequent wordline 216 to be formed is divided into two-by-two
One group, then the position of each first opening 207 is corresponding with the position of wordline 207 described in one group, and every in same group
The wordline 207 it is equal some be located at it is described first opening 207 opened ranges in, another part is located at the substrate protective
In the blocked range of layer unit 208.
Include the following steps: in the substrate protective layer 202 as an example, forming multiple first openings 207
S2-1: as shown in fig. 6, being formed firmly using chemical vapour deposition technique, physical vaporous deposition or other deposition methods
Mask layer 205 is in 202 surface of substrate protective layer.
S2-2: as shown in fig. 6, forming photoresist layer 206 in the hard exposure mask material by spin coating or other coating methods
205 surface of the bed of material.
S2-3: as shown in fig. 6, the figure according to first opening 207 is graphical by the photoresist layer 206.
S2-4: as shown in fig. 7, being made jointly with the hardmask material 205 and the patterned photoresist layer 206
For exposure mask, etching obtains multiple first openings 207 in the substrate protective layer 202.
It should be pointed out that over etching appropriate can be carried out during etching obtains first opening 207,
Etch away a part of substrate material (not being embodied in Fig. 7).
Then referring to Fig. 8, executing step S3: using chemical vapour deposition technique, physical vaporous deposition or other depositions
Method formed a hard mask layer 209 it is described first opening 207 in and 202 surface of the substrate protective layer.
As previously mentioned, the material selection of the substrate protective layer 202 needs to make its etch rate and the hard mask layer 209
Etch rate it is different, to obtain the asymmetric wordline groove of multiplex in the substrate 201.
As an example, the material of the substrate protective layer 202 is selected from silica, silicon nitride, silicon carbide, silicon oxynitride, carbon
The material of the one of which of silicon nitride, carbon silicon oxynitride and the constituted group of boron nitride, the hard mask layer 209 is selected from oxidation
Silicon, silicon nitride, silicon carbide, silicon oxynitride, carbonitride of silicium, carbon silicon oxynitride and one of erosion of the constituted group of boron nitride
Carve material of the selection than being higher than the substrate protective layer.
Again referring to Fig. 9, executing step S4: forming a photoresist layer 210 described hard using spin coating or other coating methods
209 surface of mask layer, and multiple second openings 211 are formed in the photoresist layer 210, to be formed by between second opening
Every multiple photoresist units 212.
Specifically, multiple photoresist units 212 are successively arranged on first opening 207 and the substrate protective
On layer unit 208, the width W of the first opening1The width W of photoresist unit greatly thereon2, and the two of first opening 207
Except the both ends of the prominent photoresist unit thereon in end, the width W of substrate protective layer unit3The light greatly thereon
Hinder the width W of unit4, and the both ends of the prominent photoresist unit thereon in the both ends of the substrate protective layer unit it
Outside, it is made of so that having on the described second substrate 201 being open in 211 opened ranges the hard mask layer 202
The first occlusion part 213 and be superimposed the second occlusion part formed with the hard mask layer 209 by the substrate protective layer 202
214。
As an example, first occlusion part 213 and second occlusion part 214 is of same size.
Again referring to Fig. 10, executing step S5: with the photoresist layer 210, the hard mask layer 209 and the substrate protective
Layer 202 obtains multiple wordline grooves 215 in the substrate collectively as exposure mask, etching.
Specifically, the combination of dry etching, wet etching or the two, the word etched can be used in the etching
Line groove 215 has the first wordline concave part 2151 corresponding with 213 position of the first occlusion part and with described second
The corresponding second wordline concave part 2152 in 214 position of occlusion part.
Since the etch rate of the substrate protective layer 202 is different from the etch rate of the hard mask layer 209, so that institute
It is different from the whole etch rate of second occlusion part 214 to state the first occlusion part 213, thus the first wordline concave part
2151 is different from the depth of the second wordline concave part 2152, show the asymmetric wordline groove of multiplex.
As an example, the etch rate of the substrate protective layer 202 is less than the etch rate of the hard mask layer 209, make
The depth for obtaining the second wordline concave part 2152 is less than the depth of the first wordline concave part 2151.
In the present embodiment, the central plane of wordline groove, and first wordline are deviateed in the bottom end of the wordline groove 215
The intersection of concave part 2151 and the second wordline concave part 2152 constitutes interior re-entrant angle θ.
It please refers to Figure 11-Figure 13 again, executes step S6: a plurality of wordline 216 is formed in described based on the wordline groove 215
In substrate 201.
As an example, forming a plurality of wordline 216 based on the wordline groove 215 includes following step in the substrate 201
It is rapid:
S6-1: as shown in figure 11, gate oxide 217 is formed on 215 surface of wordline groove.
As an example, the material of the gate oxide 217 uses silica, thermal oxide or other deposition methods can be used
It is formed in 215 surface of wordline groove.
S6-2: as shown in figure 11, diffusion barrier layer 218 is continuously formed on 217 surface of gate oxide.
Specifically, the material of the diffusion barrier layer 218 includes but is not limited to titanium nitride (TiN) or tantalum nitride (TaN), use
In reducing or preventing the diffusion between wordline and substrate.
S6-3: as shown in figure 12, deposition conductive material 219 is on 218 surface of diffusion barrier layer and fills the full word
Line groove 215.
Specifically, tungsten (W) or other common wordline materials may be selected in the conductive material 219.
S6-4: as shown in figure 13, carve, make the conductive material 219 lower than 201 upper surface of substrate.It is returning
During quarter, the diffusion barrier layer 218 outside wordline groove 215 is also removed.
As an example, as shown in figure 14, the wordline manufacturing method of the semiconductor memory structure of the utility model further includes
Wordline protective layer 220 is formed 219 surface of wordline the step of.The wordline protective layer 220 can be used to be protected with the substrate
The identical or different material of sheath 202, in the present embodiment, the material of the wordline protective layer 220 preferably uses silicon nitride.
So far, manufacture obtains the wordline 216 in embedment substrate, according to the shape of the wordline groove 215, the wordline
216 include the first wordline portion 2161 for being filled in the first wordline concave part 2151 and are filled in the second wordline groove
The second wordline portion 2162 in portion 2152.
In the present embodiment, the central plane of wordline is deviateed in the bottom end of the wordline 216, wherein the central plane of wordline is fixed
Justice is across the end face center line of the wordline length direction and perpendicular to the plane of wordline top surface.As an example, being adopted in Figure 14
Wordline top surface NN ' is illustrated with dashed lines, and is shown in which the central plane MM ' an of wordline, as seen from the figure, this wordline
Bottom end deviates to the right relative to its central plane MM '.As an example, showing the offset side of each wordline using arrow in Figure 14
To.
In the present embodiment, the bottom end offset direction of adjacent two wordline 216 is opposite (in the offset direction such as Figure 14 of each wordline
Shown in arrow) so that the distance between a part of adjacent two wordline bottom ends increase, between a part of adjacent two wordline bottom ends
Distance reduce, test result show for the distance between adjacent two wordline bottom ends reduce the case where, device performance influence
It is unobvious, and the case where increase for the distance between adjacent two wordline bottom ends, the coupling between transistor is substantially reduced.
In the present embodiment, the junction in first wordline portion 2161 and second wordline portion 2162 has re-entrant angle in one
θ.The interior re-entrant angle increases the surface area of the wordline, when grid of the embedded type word line as metal-oxide-semiconductor, can make MOS
The distance between pipe source electrode and drain electrode increase, to have longer channel, effectively prevent short-channel effect.
The wordline manufacturing method of the present embodiment can be effective between increase wordline and wordline under same wordline density
Distance, to reduce the coupling between wordline and wordline.
In conclusion the semiconductor memory structure of the utility model has the wordline groove of multiplex, wordline is to be based on
Wordline groove is formed in the substrate, since wordline groove is connected by the first different wordline groove of depth and the second wordline groove level
It is logical to form, therefore wordline can increase metal-oxide-semiconductor source using the embedded type word line as the grid of metal-oxide-semiconductor for asymmetric flush type
The distance between pole and drain electrode, so that metal-oxide-semiconductor has longer channel, effectively prevent short-channel effect；The utility model
The effective distance between wordline and wordline can increased under same wordline density, to reduce the coupling between wordline and wordline
It closes；In the utility model, the bottom end offset direction of adjacent two wordline is on the contrary, make between a part of adjacent two wordline bottom ends
Distance increase, the distance between a part of adjacent two wordline bottom ends reduce, and test result shows for adjacent two wordline
The case where the distance between bottom end reduces, device performance influence is unobvious, and for the distance between adjacent two wordline bottom ends
The case where increase, the coupling between transistor are substantially reduced.So the utility model effectively overcome it is in the prior art various
Disadvantage and have high industrial utilization value.
The above embodiments are only illustrative of the principle and efficacy of the utility model, and not for limitation, this is practical new
Type.Any person skilled in the art can all carry out above-described embodiment under the spirit and scope without prejudice to the utility model
Modifications and changes.Therefore, such as those of ordinary skill in the art without departing from the revealed essence of the utility model
All equivalent modifications or change completed under mind and technical idea, should be covered by the claim of the utility model.
Claims (5)
1. a kind of semiconductor memory structure characterized by comprising
Substrate；
Wordline groove is formed in the substrate, comprising the first wordline groove with the first depth and with the second depth
Second wordline groove, the first wordline groove and the second wordline groove level connection, first depth are greater than described
Second depth；
Wordline is formed by connecting by the first wordline portion and the second wordline portion, and it is recessed that first wordline portion is formed in first wordline
In slot, second wordline portion is formed in the second wordline groove, and the center of the wordline is deviateed in the bottom end of the wordline
Plane, wherein the central plane of the wordline is defined as the end face center line across the wordline length direction and perpendicular to institute
The plane of wordline top surface is stated, the bottom end of the wordline is located at the bottom end of the first wordline groove.
2. semiconductor memory structure according to claim 1, it is characterised in that: first wordline portion and described second
The junction in wordline portion has re-entrant angle in one.
3. semiconductor memory structure according to claim 1, it is characterised in that: the bottom end deviation side of adjacent two wordline
To opposite.
4. semiconductor memory structure according to claim 1, it is characterised in that: the semiconductor memory further includes shape
Isolation structure in substrate described in Cheng Yu, the isolation structure define multiple active areas in the substrate, and the wordline is worn
Cross the active area and the isolation structure.
5. semiconductor memory structure according to claim 1, it is characterised in that: at least one described active area is by two
Wordline described in item passes through.
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| CN201820792400.4U CN208189570U (en) | 2018-05-25 | 2018-05-25 | A kind of semiconductor memory structure |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110534480A (en) * | 2018-05-25 | 2019-12-03 | 长鑫存储技术有限公司 | Semiconductor memory structure and its wordline manufacturing method |
| CN111755423A (en) * | 2019-03-28 | 2020-10-09 | 华邦电子股份有限公司 | Embedded word line structure |
-
2018
- 2018-05-25 CN CN201820792400.4U patent/CN208189570U/en active Active
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110534480A (en) * | 2018-05-25 | 2019-12-03 | 长鑫存储技术有限公司 | Semiconductor memory structure and its wordline manufacturing method |
| CN111755423A (en) * | 2019-03-28 | 2020-10-09 | 华邦电子股份有限公司 | Embedded word line structure |
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