CN209658233U

CN209658233U - Magnetic RAM

Info

Publication number: CN209658233U
Application number: CN201920477730.9U
Authority: CN
Inventors: 平尔萱; 朱一明
Original assignee: Changxin Memory Technologies Inc
Current assignee: Changxin Memory Technologies Inc
Priority date: 2019-04-10
Filing date: 2019-04-10
Publication date: 2019-11-19
Anticipated expiration: 2029-04-10

Abstract

A kind of magnetic RAM, the magnetic RAM include: substrate, and the substrate surface is formed with conductive contact pad；Positioned at the magnetic storage layer of the substrate surface, the magnetic storage layer includes at least two straton accumulation layers stacked positioned at substrate surface, it include the multiple magnetic memory cells being connect with the conductive contact pad for extending vertically through each sub- accumulation layer in the magnetic storage layer, the magnetic memory cell includes magnetic tunnel junction, includes at least one magnetic tunnel junction in each sub- accumulation layer；It is formed with multiple access transistors in the substrate, is corresponded with the magnetic memory cell, the grid of the access transistor is arranged around channel region, and the drain electrode of the access transistor is connected to the conductive contact pad.Above-mentioned magnetic RAM performance with higher.

Description

Magnetic RAM

Technical field

The utility model relates to memory technology field more particularly to a kind of magnetic RAMs.

Background technique

Magnetic RAM (MARM) is based on silicon-based complementary oxide semiconductor (CMOS) and magnetic tunnel junction (MTJ) Integrating for technology, is a kind of non-volatile memory, it possesses the high-speed read-write ability of Static RAM, and dynamic The high integration of random access memory.

Referring to FIG. 1, being the structural schematic diagram of existing magnetic RAM.

The magnetic RAM includes an access transistor 110 and magnetic tunnel junction 120, the magnetic tunnel junction 120 include fixing layer 121, tunnel layer 122 and free layer 123.The drain electrode 111 of the access transistor 110 is connected to described The free layer 123 of the fixing layer 121 of magnetic tunnel junction 120, the magnetic tunnel junction 120 is connected to bit line 130；The access is brilliant The source electrode 112 of body pipe 110 is connected to source line 140.

When magnetic RAM works normally, the direction of magnetization of free layer 123 be can change, and fixing layer 121 The direction of magnetization remains unchanged.The resistance of magnetic RAM and the opposite magnetization direction of free layer 123 and fixing layer 121 have It closes.When the direction of magnetization of free layer 123 changes relative to the direction of magnetization of fixing layer 121, magnetic RAM Resistance value accordingly changes, corresponding to different storage information.

In existing technology node, the magnetic tunnel junction density in magnetic RAM unit area is larger, In During etching forms magnetic tunnel junction, it is easy that magnetic tunnel junction is caused to damage, influences chip yield.

Utility model content

Technical problem to be solved in the utility model is to reduce the damage of the magnetic tunnel junction in magnetic RAM.

To solve the above-mentioned problems, the utility model provides a kind of magnetic RAM, comprising: substrate, the base Bottom surface is formed with conductive contact pad；Positioned at the magnetic storage layer of the substrate surface, the magnetic storage layer includes being located at base At least two straton accumulation layers that bottom surface stacks, the interior magnetic storage layer includes extending vertically through leading with described for each sub- accumulation layer Multiple magnetic memory cells of electrical contact pad connection, the magnetic memory cell includes magnetic tunnel junction, in each sub- accumulation layer Including at least one magnetic tunnel junction；Multiple access transistors are formed in the substrate, one by one with the magnetic memory cell It is correspondingly connected with, the grid of the access transistor is arranged around channel region, and the drain electrode of the access transistor is connected to described lead Electrical contact pad.

Optionally, the magnetic tunnel junction random arrangement of the multiple magnetic memory cell is in each sub- accumulation layer.

Optionally, the magnetic tunnel junction of adjacent magnetic storage unit is located in different sub- accumulation layers.

Optionally, the magnetic tunnel junction in each sub- accumulation layer is arranged with random basis or array format.

Optionally, in same sub- accumulation layer, the spacing at least partly between adjacent magnetic tunnel knot is deposited greater than magnetic random Minimum spacing between storage unit.

Optionally, in the magnetic storage layer, the spacing between adjacent magnetic storage unit is a；In same sub- accumulation layer, Minimum spacing between adjacent magnetic tunnel knot isN is the number of plies of the sub- accumulation layer in the magnetic storage layer.

Optionally, each magnetic memory cell further includes conductive column, and the conductive column is located in the magnetic memory cell of place Above and/or under magnetic tunnel junction in square sub- accumulation layer, it is electrically connected with the magnetic tunnel junction.

Optionally, the substrate includes the dielectric layer of substrate and the covering substrate surface, and the access transistor is formed In the substrate surface, including source electrode, channel region, drain electrode and the circular channel region arranged straight up from substrate surface The grid of setting, the gate dielectric layer between the grid and the channel region.

Optionally, the access transistor is located at immediately below the magnetic memory cell.

Optionally, the access transistor includes fin formula field effect transistor, plane around gate transistor and vertically At least one of type ring gate transistor.

It include that at least two straton accumulation layers, each son is deposited in the magnetic storage layer of the magnetic RAM of the utility model It include at least one magnetic tunnel junction in reservoir, therefore, for same density of memory cells, the magnetic tunnel that is located on the same floor It ties quantity to reduce, increases the spacing between the magnetic tunnel junction in same sub- accumulation layer, be conducive to increase and form magnetic tunnel junction Process window, reduce as etching ion reflections damaged caused by magnetic tunnel junction side wall, to improve the magnetism of formation The quality of tunnel knot, improves the performance of memory, and can be further improved unit storage density.

Further, it is formed with access transistor of the grid around channel region in the magnetic RAM, due to grid Polar ring is arranged around channel region, and the channel length of the transistor in unit area can be improved, can substantially reduce access transistor Size, the minimum spacing between each storage unit is reduced, to improve the storage density of memory.

Further, sub- accumulation layer can be rationally arranged according to the spacing between the storage unit of memory to be formed The number of plies, reasonably adjust in same sub- accumulation layer, the minimum spacing between adjacent magnetic tunnel knot, utmostly to reduce etching During forming magnetic tunnel junction, damaged caused by magnetic tunnel junction.

Detailed description of the invention

Fig. 1 is the structural schematic diagram of existing magnetic RAM；

Fig. 2 to Fig. 3 is that the structure of the forming process of the magnetic RAM of one specific embodiment of the utility model is shown It is intended to；

Fig. 4 to Figure 13 is the structure of the forming process of the magnetic RAM of another specific embodiment of the utility model Schematic diagram；

Figure 14 to Figure 15 is the structural schematic diagram of the magnetic RAM of another specific embodiment of the utility model；

Figure 16 to Figure 19 is the structural schematic diagram of the magnetic RAM of another specific embodiment of the utility model；

Figure 20 is the structural schematic diagram of the magnetic RAM of another specific embodiment of the utility model；

Figure 21 is the structural schematic diagram of the magnetic RAM of another specific embodiment of the utility model.

Specific embodiment

With reference to the accompanying drawing to the specific embodiment party of magnetic RAM provided by the utility model and forming method thereof Formula elaborates.

Please refer to Fig. 2 to Fig. 3 be one specific embodiment of the utility model in, the forming process of magnetic RAM Structural schematic diagram.

Referring to FIG. 2, providing a substrate 200, the first metal layer 212 and medium for being located at 200 surface of substrate are formed Layer 211；Magnetic tunnel junction structure layer 220 is formed in the first metal layer 212 and 211 deposition surface of dielectric layer.

Referring to FIG. 3, carrying out figure to the magnetic tunnel junction structure layer 220 (please referring to Fig. 2) by exposure etching technics Shape, shape magnetic tunnel junction cylinder 221 arranged into an array.It is adjacent since the storage density to memory has higher requirement The distance between magnetic tunnel junction cylinder 221 is smaller, and the groove dimensions for needing to etch are smaller.Using plasma etching technics pair The magnetic tunnel junction structure layer 220 performs etching, and etches ion during bombardment, is easy to be reflected onto adjacent magnetic tunnel On 221 side wall of road knot cylinder, easy pair of magnetic tunnel junction cylinder 221 causes to damage, and influences memory performance and chip is good Rate.

Etching ion reflections can be reduced by increasing the spacing between magnetic tunnel junction cylinder 221 for magnetic tunnel The damage of cylinder 221 is tied, but the area that will lead to chip increases, the decline of the integrated level of memory.

Based on the above issues, it the utility model proposes a kind of new magnetic RAM and forming method thereof, uses Two steps or the above depositing-etching step of two steps, magnetic tunnel junction are distributed in multiple sub- accumulation layers, in each depositing-etching In step, the magnetic tunnel junction number needed to form is reduced, and so as to increase the distance between adjacent magnetic tunnel knot, is increased Etching window reduces the damage to magnetic tunnel junction cylinder, improves chip yield and memory performance, and will not reduce storage The integrated level of device.Also, in the case where equally etching spacing, by forming the sub- accumulation layer of multilayer, it is capable of increasing memory Storage density.

The forming method of the magnetic RAM includes: offer substrate, and the substrate surface is formed with conductive contact Pad；The magnetic storage layer for connecting the conductive contact pad is formed on the substrate, is included in perpendicular to substrate surface direction heap Folded at least two straton accumulation layers, the magnetic memory cell in the magnetic storage layer includes magnetic tunnel junction, each sub- accumulation layer Including at least one magnetic tunnel junction.Below in conjunction with attached drawing, new magnetic RAM and forming method thereof is carried out detailed Explanation.

Fig. 4 to Figure 13 is please referred to, is the knot of the forming process of the magnetic RAM of one concrete mode of the utility model Structure schematic diagram.In the specific embodiment, array of magnetic memory cells is formed using depositing-etching step twice.

Referring to FIG. 4, substrate 400 please be provided, 400 surface of substrate is formed with conductive contact pad 412 and first medium Layer 411.

The substrate 400 be semiconductor substrate, can for monocrystalline substrate, single-crystal germanium substrate, silicon-on-insulator substrate or Germanium substrate on insulator etc. can also be formed with doped region, semiconductor devices etc. in the substrate 400.It can be according to storage The specific design and actual demand of device reasonably select the material and structure of substrate 400, are not limited thereto.

In a specific embodiment, the substrate 400 includes substrate and the dielectric layer for covering the substrate surface, institute It states substrate surface and is formed with access transistor, the conductive structure for being connected to the access transistor is formed in the dielectric layer. The access transistor can use any transistor arrangement, can for buried grid structure transistor, ring grid field effect transistor with And at least one of various types of transistor arrangements such as planar structure transistor.The multiple each access transistor with it is described Multiple each magnetic memory cells are arranged with identical array format.

400 surface of substrate is formed with conductive contact pad 412, and the conductive contact pad 412 is subsequent to shape for connecting At magnetic memory cell.The conductive contact pad 412 is also connect with the conductive structure in the substrate 400, to be connected to State the drain electrode of the access transistor in substrate 400.

The first medium layer 411 is as the isolation structure between conductive contact pad 412.411 He of first medium layer The forming method of the conductive contact pad 412 includes: to deposit first medium layer 411 on 400 surface of substrate, etches described the One dielectric layer 411 forms through-hole in the first medium layer 411, then fills conductive material in the through-hole and carry out flat Smoothization forms the conductive contact pad 412.

In another specific embodiment, the forming method of the first medium layer 411 and conductive contact pad 412 includes: After 400 surface of substrate deposits the first metal material layer, first metal material layer is patterned, forms figure The conductive contact pad 412 of shape；Form the first medium material layer for covering the substrate 400 and the conductive contact pad 412 Later, the first medium material layer is planarized, the surface of the exposure conductive contact pad 412 forms described first Dielectric layer 411.

According to the arrangement position and density of the storage unit of magnetic RAM to be formed, the conductive contact is set The arranging density of pad 412 and position.In the specific embodiment, the spacing between adjacent conductive engagement pad 412 is to be formed Horizontal spacing in memory between adjacent magnetic storage unit.

Referring to FIG. 5, forming the first magnetic tunnel junction in the first medium layer 411 and 412 surface of conductive contact pad Structure layer 500.

The first magnetic tunnel junction structure layer 500 includes fixing layer, tunnel layer and the free layer of bottom-up stacking, It is not specifically illustrated in Fig. 5.

Referring to FIG. 6, forming the first Patterned masking layer 600 on 500 surface of the first magnetic tunnel junction structure layer.Institute The material for stating the first Patterned masking layer 600 can be the mask materials such as photoresist, silica.First Patterned masking layer 600 for defining the positions and dimensions of the first magnetic tunnel junction in the first sub- accumulation layer.

Referring to FIG. 7, being exposure mask with first Patterned masking layer 600, the magnetic tunnel junction structure layer 500 is etched (please referring to Fig. 6) forms the first magnetic tunnel junction 501 for being located at partially electronically conductive 412 surface of engagement pad.

In the specific embodiment, first magnetic tunnel junction 501 only is formed on partially electronically conductive 412 surface of engagement pad, Therefore the spacing between adjacent first magnetic tunnel junction 501 can be greater than the minimum between final magnetic memory cell to be formed Spacing, so as to reduce during etching magnetic tunnel junction structure layer 500, the first magnetic of etching ion pair of reflection Property tunnel knot 501 side wall cause damage a possibility that, to improve the quality of the first magnetic tunnel junction 501 of formation.

It can be randomly provided in respective accumulation layer according to the number of plies of the sub- accumulation layer of the magnetic storage layer of memory to be formed Magnetic tunnel junction quantity so that each sub- accumulation layer in formed at least one magnetic tunnel junction so that each accumulation layer Interior, the spacing between at least partly adjacent magnetic tunnel junction is greater than the spacing between storage unit, to a certain extent can Reduction is formed during magnetic tunnel junction, the quantity of the magnetic tunnel junction impaired due to ion reflections.

It is damaged to utmostly reduce magnetic tunnel junction, the magnetic tunnel junction in consecutive storage unit can be made It is respectively positioned in different sub- accumulation layers, so that the minimum spacing in each sub- accumulation layer between magnetic tunnel junction is greater than storage unit Between minimum spacing.

In a specific embodiment, the number of memory cells of memory to be formed is A, using n times depositing-etching Technique forms array of magnetic memory cells, then, the quantity of the magnetic tunnel junction formed each time can be closest to the whole of A/n Number.In other specific embodiments, the quantity of the magnetic tunnel junction formed every time can also be set according to the actual situation, it is only necessary to At least there are two the storages that the spacing between magnetic tunnel junction is greater than memory to be formed in the sub- accumulation layer to be formed every time Minimum spacing between unit.

In the specific embodiment, the quantity of first magnetic tunnel junction 501 of formation is A/2, and A is even number.At it In his specific embodiment, if A is odd number, the quantity of the magnetic tunnel junction formed twice can be respectivelyWith

Referring to FIG. 8, removal first Patterned masking layer 600 (please referring to Fig. 6), in adjacent first magnetic tunnel junction Second dielectric layer 800 is filled between 501.

The material of the second dielectric layer 800 can be the insulating dielectric materials such as silica, silicon oxynitride.Described first After dielectric layer 411 and 412 surface of conductive contact pad deposition second medium material layer, it is with first magnetic tunnel junction 501 Stop-layer planarizes the second medium material layer, forms the second dielectric layer 800.

Referring to FIG. 9, the second medium 800 is etched, the conduction between adjacent 501 position of the first magnetic tunnel junction 412 surface of engagement pad forms through-hole；Filling connects the first conductive column 900 of the conductive contact pad 412 in the through-hole.Institute State the surface that through-hole exposes other conductive contact pads 412.

The second dielectric layer 800, the first magnetic tunnel junction 501 and the first conductive column are covered referring to FIG. 10, being formed 900 the second magnetic tunnel junction structure layer 1000；Second graph is formed on 1000 surface of the second magnetic tunnel junction structure layer Change mask layer 1001, the second graphical mask layer 1001 is used to define the second magnetic tunnel being located in the second sub- accumulation layer The positions and dimensions of knot.

Figure 11 is please referred to, with the second graphical mask layer 1001 (please referring to Figure 10) for exposure mask, etching described second Magnetic tunnel junction structure layer 1000 (please referring to Figure 10) forms the second magnetic tunnel junction 1002；The second magnetic tunnel junction 1002 it Between fill third dielectric layer 1100.

In the specific embodiment, the quantity of second magnetic tunnel junction 1002 is A/2.

The second graphical mask layer 1001 (please referring to Figure 10) and the first Patterned masking layer 600 (please referring to Fig. 6) Graph position no overlap so that first magnetic tunnel junction 501 and the second magnetic tunnel junction 1002 are perpendicular to base No overlap on the direction on 400 surface of bottom.

Spacing between the second adjacent magnetic tunnel junction 1002 is larger, therefore is etching the second magnetic tunnel junction structure layer During 1000 form second magnetic tunnel junction 1002, etching ion reflections can be reduced to the second magnetic tunnel junction It is damaged caused by 1002.

Figure 12 is please referred to, the third dielectric layer 1100 is etched, forms the logical of exposure first magnetic tunnel junction 501 The second conductive column 1200 is filled in hole in the through-hole.

Second conductive column 1200 is electrically connected with the first magnetic tunnel junction 501 of lower layer.It is subsequent in the third medium 1100 surface of layer form the bit line connecting with each second conductive column 1200 and the second magnetic tunnel junction 1001.

Where the first sub- accumulation layer and second magnetic tunnel junction 1001 where first magnetic tunnel junction 501 Second straton accumulation layer constitutes the magnetic storage layer for being located at 400 surface of substrate.Each magnetic storage in the magnetic storage layer Unit includes a magnetic tunnel junction and the conductive column for connecting the magnetic tunnel junction top or bottom.

Figure 13 is please referred to, is the position view of each magnetic memory cell in magnetic storage layer in present embodiment. Figure 12, for the diagrammatic cross-section of the secant AA ' along Figure 13.Wherein, the circle in Figure 13 where number 1 and 2 respectively represents and has The storage unit of first magnetic tunnel junction 501 and the second magnetic tunnel junction 1002, first magnetic tunnel junction 501 and described Two magnetic tunnel junction 1002 are located in different sub- accumulation layers.

In the specific embodiment, each magnetic memory cell is arranged according to the form of rectangular array unit.It is each The magnetic tunnel junction of capable and each column is alternately distributed in the first sub- accumulation layer and the second sub- accumulation layer, so that in each sub- accumulation layer Magnetic tunnel junction also arranged according to array format.

In the magnetic storage layer, the spacing between adjacent magnetic storage unit is a (between consecutive storage unit central axis Distance).By taking the second sub- accumulation layer as an example, have between the second adjacent magnetic tunnel junction 1002 in the second sub- accumulation layer Two kinds of spacing, respectively d1 and d2, wherein d2=2a,It is all larger than a.

Therefore, the first sub- accumulation layer and the second sub- accumulation layer are sequentially formed by depositing-etching step twice, each time During etching forms magnetic tunnel junction, at least partly adjacent magnetic tunnel knot in same sub- accumulation layer can be improved Between minimum spacing, so as to reduce as etch ion reflections damage caused by magnetic tunnel junction side wall, improve most End form at memory performance.

In other specific embodiments, three or more than four sub- accumulation layers can also be formed, is further decreased each The quantity of magnetic tunnel junction in sub- accumulation layer, thus between increasing the minimum between the adjacent magnetic tunnel knot in each sub- accumulation layer Away from.In the forming process of different sub- accumulation layers, the Patterned masking layer with different graphic, each Patterned masking layer is respectively adopted The interior graph position no overlap for being used to define magnetic tunnel junction.

Quantity and the position of the magnetic tunnel junction in each sub- accumulation layer can be randomly provided；It can also be according to certain Quantity and the position of the magnetic tunnel junction in each sub- accumulation layer is arranged in rule, so that the magnetic tunnel junction point in each sub- accumulation layer Cloth is more regular, and the magnetic tunnel junction density in each sub- accumulation layer is more uniform, so that memory is during the work time, by described The even heat that magnetic tunnel junction generates is distributed in each sub- storage, avoids the problem that local temperature rise is too fast.

In specific embodiment of the present utility model, in the magnetic storage layer of memory to be formed, adjacent magnetic is deposited Minimum spacing between storage unit is a；When the magnetic tunnel junction in consecutive storage unit is located in different sub- accumulation layers When, it can utmostly reduce the damage to magnetic tunnel junction.When forming each sub- accumulation layer, the Patterned masking layer of use Minimum spacing between adjacent pattern can beThe minimum spacing between magnetic tunnel junction formed isWherein n For the number of plies for the sub- accumulation layer that magnetic storage layer includes.

For example, being located on the same floor interior magnetic in the case where forming three straton accumulation layers using depositing-etching step three times Minimum spacing between property tunnel knot can increase toWhen using four depositing-etching steps four straton accumulation layers of formation In the case where, the minimum spacing being located on the same floor between interior magnetic tunnel junction can increase to 2a.

Figure 14 and Figure 15 are please referred to, is in another specific embodiment of the utility model, using depositing-etching step three times The storage unit schematic diagram of the magnetic RAM of formation, Figure 15 are the diagrammatic cross-section of the secant BB ' along Figure 14.

In the specific embodiment, in the magnetic storage layer that is formed in substrate 1500, including three straton accumulation layers.Wherein compile Circle where numbers 1,2 and 3 respectively indicates magnetic with the first magnetic tunnel junction 1501, the second magnetic tunnel junction 1502 and third The storage unit of tunnel knot 1503, the first magnetic tunnel junction 1501, the second magnetic tunnel junction 1502 and third magnetic tunnel junction 1503 are sequentially located at first in the sub- accumulation layer of third.

In the specific embodiment, each storage unit of memory is arranged according to the form of diamond shape array element. Magnetic tunnel junction in the storage unit of every a line is sequentially distributed to be stored in the first sub- accumulation layer, the second sub- accumulation layer and third Layer, so that the magnetic tunnel junction in each sub- accumulation layer is also arranged according to array format, the magnetic tunnel junction in each sub- accumulation layer Quantity is close, is evenly distributed.

In the case that minimum spacing is a between the storage unit of the magnetic RAM, using deposition-quarter three times Step is lost, so that the array of magnetic memory cells formed has three sub- accumulation layers.By taking the first sub- accumulation layer as an example, the first son is deposited In reservoir, there are three types of different spacing, respectively c1, c2 and c3 for tool between the first adjacent magnetic tunnel junction 1501；When adjacent When minimum spacing between storage unit is a, c1=3a,C3=2a, minimum spacing areGreater than magnetism Minimum spacing a in memory cell array between each magnetic memory cell.

Figure 16, Figure 17 and Figure 18 are please referred to, is in another specific embodiment of the utility model, using four deposition-quarters The storage unit schematic diagram for the magnetic RAM that step is formed is lost, Figure 17 is the diagrammatic cross-section of the secant CC ' along Figure 16, Figure 18 is the diagrammatic cross-section of the secant DD ' along Figure 16, and Figure 18 is the diagrammatic cross-section of the secant EE ' along Figure 16.

It include four straton accumulation layers in the magnetic storage layer that is formed in substrate 1700 in the specific embodiment, wherein Circle in Figure 16 where number 1,2,3 and 4 is respectively used to indicate there is the first magnetic tunnel junction 1701, the second magnetic tunnel junction 1702, the storage unit of third magnetic tunnel junction 1703 and the 4th magnetic tunnel junction 1704, the first magnetic tunnel junction 1701, Two magnetic tunnel junction 1702, third magnetic tunnel junction 1703 and the 4th magnetic tunnel junction 1704 are sequentially located at first to fourth son In accumulation layer.

In the specific embodiment, each storage unit is arranged according to rectangular array unit, the storage of every a line Magnetic tunnel junction in unit, which is respectively separated, to be distributed in two sub- accumulation layers, and the magnetic tunnel in the storage unit of adjacent rows Knot is located in different sub- accumulation layers.Such as the magnetic tunnel junction of the storage unit of the first row is located at the storage of third In layer and the second sub- accumulation layer, and the magnetic tunnel junction of the storage unit of the second row is located at the first sub- accumulation layer and the 4th son In accumulation layer, every three row is consistent with the distribution situation of the magnetic tunnel junction of the storage unit of the first row.When consecutive storage unit it Between minimum spacing be a when, the minimum spacing by taking third straton accumulation layer as an example, between adjacent third magnetic tunnel junction 1703 E=2a.

In other specific embodiments, the spread pattern of storage unit can not also be limited, it can be according to certain rule Array arrangement, can also be with random distribution.Equally, the arrangement position of the magnetic tunnel layer in each sub- accumulation layer can also at random or be pressed It is arranged according to array.

In the forming process of above-mentioned memory, by depositing-etching step at least twice, sequentially form at least two layers The sub- accumulation layer of storage unit is each formed with the magnetic tunnel junction of storage unit in each sub- accumulation layer.Therefore it at least can be improved Spacing between same sub- accumulation layer inner part adjacent magnetic tunnel knot, so that being reduced when etching magnetic tunnel junction structure layer Etching ion is damaged by reflection and caused by magnetic tunnel junction side wall, is increased process window, is improved finally formed memory Performance.

Also, as the quantity for forming sub- accumulation layer increases, between the adjacent magnetic tunnel knot in same sub- accumulation layer Minimum spacing increases.Can be according to the minimum spacing between the storage unit of memory to be formed, and form better quality Magnetic tunnel junction needed for etch minimum spacing, the quantity of the sub- display layer is rationally set, do not change memory storage it is close Under the premise of degree, the performance of memory is improved to greatest extent.

Specific embodiment of the present utility model also provides the magnetic RAM formed using the above method.

Figure 12 and Figure 13 are please referred to, is the structural representation of the magnetic RAM of one specific embodiment of the utility model Figure.Figure 12 is the diagrammatic cross-section of the secant AA ' along Figure 13.

The magnetic RAM includes: substrate 400, and 400 surface of substrate is formed with conductive contact pad 412；Position Magnetic storage layer in 400 surface of substrate, the magnetic storage layer include at least two stratons stacked positioned at substrate surface Accumulation layer, the interior magnetic storage layer includes the multiple magnetism connecting with the conductive contact pad for extending vertically through each sub- accumulation layer Storage unit, the magnetic memory cell include magnetic tunnel junction, include at least one magnetic tunnel junction in each sub- accumulation layer.

The magnetic tunnel junction includes fixing layer, tunnel layer and the free layer stacked.

Multiple access transistors are also formed in the substrate 400, are connected one to one with the magnetic memory cell, institute Stating access transistor includes at least one of planar ransistor, embedding grid type transistor and ring gate type transistor.

In the specific embodiment, first medium layer 411 is formed between adjacent conductive engagement pad 412.Described first is situated between Matter layer 411 uses insulating materials, as the separation layer between conductive contact pad 412.The magnetic storage layer includes that two stratons are deposited Reservoir is formed with the first magnetic tunnel junction 501 in the first sub- accumulation layer, is formed with the second magnetic tunnel junction in the second sub- accumulation layer 1002, the first magnetic tunnel junction 501 and the second magnetic tunnel junction 1002 do not belong to different storage units.

It further include being connect with the conductive contact pad 412 and the second magnetic tunnel junction 1002 in the first sub- accumulation layer First conductive column 900 is formed with second dielectric layer 800 between first conductive column 900 and the first magnetic tunnel junction 501.

It further include the second conductive column 1200 being connect with first magnetic tunnel junction 501 in the second sub- accumulation layer, Third dielectric layer 1100 is formed between second conductive column 1200 and the second magnetic tunnel junction 1002.

In Figure 13, the circle at the place of number 1 and 2 respectively represents the first magnetic tunnel junction 501 and the second magnetic tunnel junction Storage unit where 1002.In the specific embodiment, each magnetic memory cell according to rectangular array unit form into Row arrangement.Every a line and the magnetic tunnel junction of each column are spaced apart in the first sub- accumulation layer and the second sub- accumulation layer, so that often Magnetic tunnel junction in one sub- accumulation layer is also arranged according to array format.In each sub- accumulation layer, have between adjacent magnetic tunnel knot There are two types of spacing, respectively d1 and d2.When the minimum spacing between consecutive storage unit is a, d1=2a,

Figure 14 and Figure 15 are please referred to, the structure for the magnetic RAM of another specific embodiment of the utility model is shown It is intended to.Figure 15 is the diagrammatic cross-section of the secant BB ' along Figure 14.

In the specific embodiment, the magnetic RAM includes substrate 1500 and is formed in the substrate 1500 On magnetic storage layer, the magnetic storage layer includes the three straton accumulation layers upward from 1500 surface of substrate, the of the bottom The first magnetic tunnel junction 1501 is formed in one sub- accumulation layer, in the second sub- accumulation layer of the first son storage layer surface It is formed with the second magnetic tunnel junction 1502, is formed with third magnetic in the sub- accumulation layer of third of the second son storage layer surface Property tunnel knot 1503；First magnetic tunnel junction 1501, the second magnetic tunnel junction 1502 and third magnetic tunnel junction 1503 It is located in different storage units.Each sub- accumulation layer is also formed with conductive column, the conductive column connection upper layer or/lower layer Magnetic tunnel junction in sub- accumulation layer.It is isolated between conductive column and magnetic tunnel junction in same sub- accumulation layer by dielectric layer.

In Figure 15, number 1,2 and 3 respectively represent first magnetic tunnel junction 1501, the second magnetic tunnel junction 1502 with And the storage unit where third magnetic tunnel junction 1503.In the specific embodiment, in each sub- accumulation layer, adjacent magnetism There are three kinds of spacing, respectively c1, c2 and c3 between tunnel knot.When the minimum spacing between consecutive storage unit is a, c1 =3a,C3=2a, minimum spacing areThe minimum spacing being all larger than in memory cell array between storage unit a。

Figure 16, Figure 17 and Figure 19 are please referred to, is the magnetic RAM in another specific embodiment of the utility model Storage unit schematic diagram, Figure 17 is the diagrammatic cross-section of the secant CC ' along Figure 16, and Figure 18 is that secant DD ' is cutd open along Figure 16 Face schematic diagram, Figure 19 are the diagrammatic cross-section of the secant EE ' along Figure 16.

It include four in the magnetic storage layer formed in the substrate 1700 of magnetic RAM in the specific embodiment Straton battle array layer, wherein the circle in Figure 16 where number 1,2,3 and 4, it is magnetic to respectively represent the first magnetic tunnel junction 1701, second Storage unit where tunnel knot 1702, third magnetic tunnel junction 1703 and the 4th magnetic tunnel junction 1704, first magnetic Property tunnel knot 1701, the second magnetic tunnel junction 1702, third magnetic tunnel junction 1703 and the 4th magnetic tunnel junction 1704 are successively In first to fourth sub- accumulation layer.

In the specific embodiment, each storage unit is arranged according to rectangular array unit, the storage of every a line Magnetic tunnel junction in unit, which is respectively separated, to be distributed in two sub- accumulation layers, and the magnetic tunnel in the storage unit of adjacent rows Knot is located in different sub- accumulation layers.Such as the magnetic tunnel junction of the storage unit of the first row is located at the storage of third In layer and the second sub- accumulation layer, and the magnetic tunnel junction of the storage unit of the second row is located at the first sub- accumulation layer and the 4th son In accumulation layer, every three row is consistent with the distribution situation of the magnetic tunnel junction of the storage unit of the first row.

When the minimum spacing between consecutive storage unit is a, by taking third straton accumulation layer as an example, adjacent third is magnetic Minimum spacing e=2a between tunnel knot 1703, greater than the minimum spacing between consecutive storage unit.

In the magnetic RAM in other specific embodiments, the array of magnetic memory cells includes n-layer heap Folded sub- accumulation layer, the spacing between adjacent magnetic storage unit are a, when the magnetic tunnel junction in consecutive storage unit distinguishes position When in different sub- accumulation layers, in same sub- accumulation layer, the minimum spacing between adjacent magnetic tunnel knot isn≥2。

It, can be according to the son of the magnetic storage layer of memory to be formed in other specific embodiments of the utility model The number of plies of accumulation layer is randomly provided the quantity of the magnetic tunnel junction in respective accumulation layer, so that being formed extremely in each sub- accumulation layer A few magnetic tunnel junction, so that the spacing between at least partly adjacent magnetic tunnel junction, which is greater than, deposits in each accumulation layer Spacing between storage unit, can reduce to be formed during magnetic tunnel junction to a certain extent, is damaged due to ion reflections Magnetic tunnel junction quantity.

It is damaged to utmostly reduce magnetic tunnel junction, the magnetic tunnel junction in consecutive storage unit can be made It is respectively positioned in different sub- accumulation layers, so that the minimum spacing in each sub- accumulation layer between magnetic tunnel junction is all larger than storage list Minimum spacing between member.Magnetic tunnel junction distribution in each sub- accumulation layer is more regular, the magnetic tunnel in each sub- accumulation layer When knot density is more uniform, memory is distributed in each son during the work time, by the even heat that the magnetic tunnel junction generates Storage, avoids the problem that local temperature rise is too fast.

In other specific embodiments, the spread pattern of the storage unit of memory, each storage can not also be limited Unit can be arranged according to certain rule array, can also be with random distribution.Equally, the row of the magnetic tunnel layer in each sub- accumulation layer Column position can also arrange at random or according to array.

Compared with magnetic RAM of all magnetic tunnel junction in same layer, the magnetic random of the utility model is deposited The magnetic tunnel junction of reservoir is distributed at least two straton accumulation layers, in same sub- accumulation layer at least partly between magnetic tunnel junction Spacing increase, can effectively improve the process window to form magnetic tunnel junction, reduce etching ion by reflection and to magnetic tunnel It is damaged caused by road knot side wall, to be conducive to improve the quality of the magnetic tunnel junction formed, improves the magnetic random storage The performance of device.

Figure 20 is please referred to, is the structural schematic diagram of the memory of another specific embodiment of the utility model.

In the specific embodiment, it is formed with ring gate type transistor in the substrate 2000 of the memory, it is brilliant as access Body pipe.

Specifically, the substrate 2000 includes substrate 2001 and is formed on the substrate 2001 and deposits access transistor 2002, and the separation layer 2003 between each access transistor 2002.

The access transistor 2002 is vertical type ring gate transistor (Vertial Gate All Around FET), packet The source electrode 2004 arranged straight up from 2001 surface of substrate, channel region 2005 and drain electrode 2006 are included, around the channel region The grid 2007 of 2005 settings, and the gate dielectric layer 2008 between the grid 2007 and the channel region 2005.

The substrate 2000 further includes the dielectric layer 2009 for covering the separation layer 2003 and access transistor 2002, described The first electrical contacts 2010 for connecting the drain electrode 2006 are also formed in dielectric layer 2009.

2000 surface of substrate is formed with conductive contact pad 2013, and the conductive contact pad 2013 connects with first electricity 2010 connection of touching.The conductive contact pad 2013 is formed in a dielectric layer 2012.

Accumulation layer 2020 is formed with above the substrate 2000, the accumulation layer 2020 includes the first sub- 2021 He of accumulation layer Second sub- accumulation layer 2022, the accumulation layer 2020 include extending vertically through the storage unit of each sub- accumulation layer, the magnetic storage Unit includes the conductive column 2033 of magnetic tunnel junction 2031,2032 and the magnetic tunnel junction above and or below.At other In specific embodiment, the accumulation layer 2020 can also include three layers or more of sub- accumulation layer.

Be each formed with an access transistor 2002 in substrate 2000 below each storage unit, and each storage unit with Electrical connection is formed between the drain electrode 2006 of access transistor 2002 below.

Storage unit in the accumulation layer 2020 can be arranged according to the array format of certain rule, such as can be with It is distributed according to diamond shape array element formal distribution or according to rectangular array unit form.

In the specific embodiment, the magnetic tunnel junction of storage unit can be distributed in random distribution or according to array In the first sub- accumulation layer 2021 and the second sub- accumulation layer 2022.In a specific embodiment, the first sub- accumulation layer Magnetic tunnel junction 2031 in 2021 is with the distribution of rectangular array unit form；Magnetic tunnel junction in second sub- accumulation layer 2022 2032 with the distribution of rectangular array unit form.

In other specific embodiments, the magnetic tunnel junction 2031 in the first sub- accumulation layer 2021 is with diamond shape array Unit form distribution；Magnetic tunnel junction 2032 in second sub- accumulation layer 2022 is with diamond shape array element formal distribution.

In other specific embodiments, magnetic tunnel junction 2031 and the second son in the first sub- accumulation layer 2021 are deposited Magnetic tunnel junction 2032 in reservoir 2022 can also be with random distribution.

In the specific embodiment, a kind of exemplary construction of the access transistor 2002 is only gived.It is specific at other In embodiment, the access transistor 2002 can also have circular grid structure, such as the access transistor 2002 may be used also Think fin formula field effect transistor (FinFET) or plane around gate transistor (Lateral Gate All Around FET)。

The fin formula field effect transistor (FinFET) includes the fin for being formed in the protrusion of substrate surface, across the fin The grid in portion, top and side wall of the grid around channel region；Source electrode and drain electrode is located in the fin of grid two sides.

The plane includes the channel region for being suspended on substrate surface around grid structure, positioned at substrate surface, is separately connected The source electrode and drain electrode of channel region two sides, around the grid of the channel region.

In other specific embodiments, the access transistor of other structures, such as embedding grid type transistor can also be used Deng to reduce the size of memory transistor.

In the specific embodiment, 2020 surface of accumulation layer is also formed with second dielectric layer 2024, and described second is situated between The third contact portion 2023 for connecting each storage unit is formed in matter layer 2024；2023 surface of second dielectric layer is formed with position Line (Bit Line) 2030, with the third contact portion 2023.

Spacing between the storage unit of memory is not only limited by the process window that etching forms magnetic tunnel junction, also Size by the access transistor below storage unit is limited.In above-mentioned specific embodiment, by each storage of memory The magnetic tunnel junction of unit is distributed in multiple sub- accumulation layers, and each sub- accumulation layer independently forms, and therefore, is guaranteeing each storage unit For interior magnetic tunnel junction in the vertical direction under the premise of no overlap, the spacing between magnetic tunnel junction in each sub- accumulation layer can To be arranged according to the limitation of minimum process window, so as to improve between the minimum between finally formed each storage unit Away to improve the storage density of memory.

Further, intrabasement access transistor uses ring gate type transistor, can substantially reduce ring gate transistor Size enables the minimum spacing between each storage unit to be reduced, to improve the storage density of memory.

The conduct of embedding grid type transistor can also be formed in other specific embodiments, in the substrate of the memory to deposit Transistor is taken, the grid of the access transistor is located in the substrate, and the source electrode and drain electrode of the access transistor distinguishes position In the grid two sides and bottom is higher than the top portions of gates.

Figure 21 is please referred to, is the structural schematic diagram of the memory of another specific embodiment of the utility model.

Specifically, the substrate 2100 includes substrate 2101, the substrate 2101 includes active area and encirclement active area Isolation structure 2102.In a specific embodiment, the isolation structure 2102 can be fleet plough groove isolation structure.

The access transistor is formed in the active area of the substrate 2101, and the access transistor includes being embedded in institute The grid 2103 in substrate 2101 is stated, source electrode 2105 and drain electrode 2106 are located at the substrate 2101 of 2103 two sides of grid It is interior, and bottom is higher than the top of the grid 2103.It is formed with separation layer 2107 at the top of the grid 2103, with the substrate 2101 surfaces flush.Gate dielectric layer 2104 is formed between the grid 2103 and the substrate 2101.

In the specific embodiment, two adjacent transistors are formed in each active area, i.e., there are two be embedded in for formation Grid 2104 in the substrate 2101, adjacent transistor share same source electrode.Specifically, the source electrode 2105 is positioned at adjacent Between two grids 2104, drain electrode 2106 is located at 2104 outside of grid.

The substrate 2100 further includes the first medium layer 2108 for covering 2101 surface of substrate, the conductive contact pad 2113 are formed in the first medium layer 2108.The connection drain electrode 2106 is also formed in the first medium layer 2108 First electrical contacts 2109, and the second electrical contacts 2110 of the connection grid 2103, second electrical contacts 2110 For connecting source line (Source Line).

The conductive contact pad 2113 on 2100 surface of substrate, connect with first electrical contacts 2109.The substrate 2100 tops are formed with accumulation layer 2120, and the accumulation layer 2120 includes the first sub- accumulation layer 2121 and the second sub- accumulation layer 2122, the accumulation layer 2120 includes extending vertically through the storage unit of each sub- accumulation layer, and the magnetic memory cell includes magnetism Tunnel knot 2131,2132 and the conductive column 2133 of the magnetic tunnel junction above and or below.In other specific embodiments In, the accumulation layer 2120 can also include three layers or more of sub- accumulation layer.

In another specific embodiment, an access crystal can also be only formed in each active area of substrate 2101 Pipe, including the grid being embedded in active area, source electrode and drain electrode positioned at grid two sides, the drain electrode and the conductive contact pad 2113 connections, to be connected to the magnetic tunnel junction 2131.

In the specific embodiment, 2120 surface of accumulation layer is also formed with second dielectric layer 2124, and described second is situated between The third contact portion 2123 for connecting each storage unit is formed in matter layer 2124；2123 surface of second dielectric layer is formed with position Line (Bit Line) 2130, connect with the third contact portion 2123.

The intrabasement access transistor uses embedding grid type transistor, can substantially reduce the size of transistor, so that Minimum spacing between each storage unit can be reduced, to improve the storage density of memory.And adjacent transistor it Between can share the minimum spacing further reduced between each storage unit with source electrode.

The above is only the preferred embodiment of the utility model, it is noted that for the common skill of the art Art personnel can also make several improvements and modifications without departing from the principle of this utility model, these improvements and modifications Also it should be regarded as the protection scope of the utility model.

Claims

1. a kind of magnetic RAM characterized by comprising

Substrate, the substrate surface are formed with conductive contact pad；

Positioned at the magnetic storage layer of the substrate surface, the magnetic storage layer includes at least two layers stacked positioned at substrate surface Sub- accumulation layer, the interior magnetic storage layer includes the multiple magnetic connecting with the conductive contact pad for extending vertically through each sub- accumulation layer Property storage unit, the magnetic memory cell includes magnetic tunnel junction, includes at least one magnetic tunnel in each sub- accumulation layer Knot；

It is formed with multiple access transistors in the substrate, connects one to one with the magnetic memory cell, the access is brilliant The grid of body pipe is arranged around channel region, and the drain electrode of the access transistor is connected to the conductive contact pad.

2. magnetic RAM according to claim 1, which is characterized in that the magnetism of the multiple magnetic memory cell Tunnel knot random arrangement is in each sub- accumulation layer.

3. magnetic RAM according to claim 1, which is characterized in that the magnetic tunnel of adjacent magnetic storage unit Knot is located in different sub- accumulation layers.

4. magnetic RAM according to claim 1, which is characterized in that magnetic tunnel junction in each sub- accumulation layer with Random basis or array format arrangement.

5. magnetic RAM according to claim 1, which is characterized in that in same sub- accumulation layer, at least partly phase Spacing between adjacent magnetic tunnel junction is greater than the minimum spacing between magnetic random storage unit.

6. magnetic RAM according to claim 1, which is characterized in that in the magnetic storage layer, adjacent magnetic Spacing between storage unit is a；In same sub- accumulation layer, the minimum spacing between adjacent magnetic tunnel knot isN is institute State the number of plies of the sub- accumulation layer in magnetic storage layer.

7. magnetic RAM according to claim 1, which is characterized in that each magnetic memory cell further includes conduction Column, the conductive column are located in sub- accumulation layer square above and/or under the magnetic tunnel junction in the magnetic memory cell of place, and described Magnetic tunnel junction electrical connection.

8. magnetic RAM according to claim 1, which is characterized in that the substrate includes described in substrate and covering The dielectric layer of substrate surface, the access transistor is formed in the substrate surface, including arranges straight up from substrate surface Source electrode, channel region, drain electrode and around the channel region setting grid, between the grid and the channel region Gate dielectric layer.

9. magnetic RAM according to claim 1, which is characterized in that the access transistor is located at the magnetism Immediately below storage unit.

10. magnetic RAM according to claim 1, which is characterized in that the access transistor includes fin field Effect transistor, plane are around at least one of gate transistor and vertical type ring gate transistor.