CN208188715U - The LDO circuit of high PSRR quick response - Google Patents
The LDO circuit of high PSRR quick response Download PDFInfo
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- CN208188715U CN208188715U CN201820827256.3U CN201820827256U CN208188715U CN 208188715 U CN208188715 U CN 208188715U CN 201820827256 U CN201820827256 U CN 201820827256U CN 208188715 U CN208188715 U CN 208188715U
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Abstract
The utility model relates to a kind of LDO circuits of high PSRR quick response.Including error amplifier, resistance R1, R2, metal-oxide-semiconductor Mp, M1, M2, M3, capacitor C1, CL, the first input end of error amplifier is connected to reference voltage source, second input terminal of error amplifier and one end of R1, one end of R2 connects, the other end of the load pipe end and R1 of error amplifier, the first end of M2, the second end of Mp, one end of CL is connected, and the output end as LDO circuit, the output end of error amplifier and one end of C1, the control terminal of M2 connects, the first end of M1 is connected with the first end of Mp is connected to VDD, the second end of M1 and the control terminal of M1, the control terminal of Mp, the second end of M3 connects, the second end of M2 and the other end of C1, the first end of M3, which is connected and is connected through a current source with the other end of R2, to be connected to The control terminal of GND, M3 are connected to bias voltage input, and the other end of CL is connected to GND.The utility model has high PSRR, quick response and low in energy consumption.
Description
Technical field
The utility model is applied in the Sigma-delta modulator applied to incremental, and in particular to a kind of high power supply
Inhibit the LDO circuit than quick response.
Background technique
With the rapid development of information technology, New Generation of Portable communication equipment can band within the shorter time, narrower
On width and smaller power consumption gets off to transmit more information.This just connects between natural world and digital processing chip it
More stringent requirements are proposed for modulus/D/A converting circuit.Them are not only needed to work in higher frequency, it is also necessary to have higher
Signal-to-noise ratio.The one kind of clutter as noise on power supply, affects digital-to-analogue/analog-digital converter performance.In power management chip
In, low pressure difference linear voltage regulator (LDO) often is connected behind DC-DC converter, ripple is adjusted by LDO to provide clean electricity
Simulation/RF block of the potential source to noise-sensitive.And without capacitive LDO due to the removal of output end bulky capacitor, so that system is in high frequency
The power supply rejection ratio of section is worse compared to traditional structure, therefore how to improve and grind without capacitive power supply rejection ratio as LDO
Another research hotspot studied carefully.
The power supply rejection ratio (PSRR) of traditional LDO is not high enough, and the method for improving power supply rejection ratio mainly has: in power supply electricity
RC filter is accessed after pressure, is reduced the ripple of supply voltage, is increased the series of LDO to improve the gain of system or cascade two
A LDO improves power supply rejection ratio.Access RC filter will lead to the increase of LDO pressure drop, while resistance and capacitor will occupy
Biggish chip area increases cost, is not suitable for system on chip；Increase the series of LDO to improve gain, can effectively mention
The power supply rejection ratio of senior middle school's low-frequency range, but the raising of gain can bring the reduction of loop bandwidth to influence whether that the transient state of system is rung
Answer characteristic；Cascading two LDO simultaneously then will increase the power consumption of system, greatly reduce the efficiency of LDO.
The utility model proposes a kind of LDO circuits of high PSRR quick response, the Sigma- applied to incremental
In delta modulator, circuit structure is clearly simple, and power supply rejection ratio can be effectively improved when quick response, realizes
Low-power consumption.
Summary of the invention
The purpose of this utility model is to provide a kind of LDO circuits of high PSRR quick response, and the circuit is fast
Power supply rejection ratio and low in energy consumption is improved while speed response, meets answering in the Sigma-delta modulator of incremental
Use performance.
To achieve the above object, the technical solution of the utility model is: a kind of LDO electricity of high PSRR quick response
Road, including error amplifier, resistance R1, R2, metal-oxide-semiconductor Mp, M1, M2, M3, capacitor C1, CL, the first of the error amplifier are defeated
Enter end and is connected to reference voltage source, one end connection of one end, R2 of the second input terminal and R1 of error amplifier, error amplifier
Load pipe end be connected with one end of the other end of R1, the first end of M2, the second end of Mp, CL, and as entire LDO circuit
Output end, one end of the output end of error amplifier and C1, the control terminal of M2 connect, the first end and the first end phase of Mp of M1
It is connected to VDD, the second end of M1 and control terminal, the control terminal of Mp, the second end of M3 of M1 connect, and the second end of M2 and C1's is another
One end, M3 first end be connected and be connected through a current source with the other end of R2 and be connected to GND, the control terminal of M3 is connected to partially
Voltage input end is set, the other end of CL is connected to GND.
In an embodiment of the utility model, Mp is power tube in LDO circuit.
In an embodiment of the utility model, M1, M2 constitute negative feedback network.
In an embodiment of the utility model, R1, R2 constitute feedback network.
In an embodiment of the utility model, the error amplifier includes the first to the 5th metal-oxide-semiconductor, the first metal-oxide-semiconductor
The load pipe end that first end, the first end of the second metal-oxide-semiconductor are connected as error amplifier, the second end of the first metal-oxide-semiconductor, first
The control terminal of metal-oxide-semiconductor, the control terminal of the second metal-oxide-semiconductor, which are connected, is connected to the second end of third metal-oxide-semiconductor, the second end of the second metal-oxide-semiconductor with
The second end of 4th metal-oxide-semiconductor is connected to the output end of error amplifier, and the control terminal of third metal-oxide-semiconductor is as error amplifier
First input end, the first end of third metal-oxide-semiconductor is connected with the first end of the 4th metal-oxide-semiconductor is connected to the second end of the 5th metal-oxide-semiconductor, and the 4th
Second input terminal of the control terminal of metal-oxide-semiconductor as error amplifier, the first end of the 5th metal-oxide-semiconductor are connected to GND, the 5th metal-oxide-semiconductor
Control terminal as bias current inputs.
It in an embodiment of the utility model, further include one for providing the biasing circuit of bias voltage, bias current.
Compared to the prior art, the utility model has the following beneficial effects: the utility model is while quick response
Power supply rejection ratio and low in energy consumption is improved, the application performance in the Sigma-delta modulator of incremental is met.
Detailed description of the invention
Fig. 1 is the structure chart of the quick response LDO of high PSRR.
Fig. 2 is the whole electrograph of high PSRR quick response LDO.
Fig. 3 is the line regulation simulation curve figure of high PSRR quick response LDO.
Fig. 4 is the PSRR simulation curve figure of high PSRR quick response LDO.
Fig. 5 is the load transient response simulation curve figure of high PSRR quick response LDO.
Specific embodiment
With reference to the accompanying drawing, the technical solution of the utility model is specifically described.
The utility model provides a kind of LDO circuit of high PSRR quick response, including error amplifier, resistance
R1, R2, metal-oxide-semiconductor Mp, M1, M2, M3, capacitor C1, CL, the first input end of the error amplifier are connected to reference voltage source,
One end of second input terminal of error amplifier and R1, R2 one end connect, the load pipe end of error amplifier and R1's is another
End, the first end of M2, the second end of Mp, CL one end be connected, and the output end as entire LDO circuit, error amplifier
Output end and the control terminal of one end of C1, M2 connect, the first end of M1 is connected with the first end of Mp is connected to VDD, the second of M1
End is connect with the control terminal of M1, the control terminal of Mp, the second end of M3, second end and the other end of C1, the first end phase of M3 of M2
It connects and is connected through a current source with the other end of R2 and be connected to GND, the control terminal of M3 is connected to bias voltage input, CL's
The other end is connected to GND.
Mp is power tube in LDO circuit.M1, M2 constitute negative feedback network.R1, R2 constitute feedback network.
The error amplifier includes the first to the 5th metal-oxide-semiconductor, the first end of the first end of the first metal-oxide-semiconductor, the second metal-oxide-semiconductor
The load pipe end being connected as error amplifier, the second end of the first metal-oxide-semiconductor, the control terminal of the first metal-oxide-semiconductor, the second metal-oxide-semiconductor
Control terminal be connected and be connected to the second end of third metal-oxide-semiconductor, the second end of the second metal-oxide-semiconductor connect work with the second end of the 4th metal-oxide-semiconductor
For the output end of error amplifier, first input end of the control terminal of third metal-oxide-semiconductor as error amplifier, third metal-oxide-semiconductor
First end is connected with the first end of the 4th metal-oxide-semiconductor is connected to the second end of the 5th metal-oxide-semiconductor, and the control terminal of the 4th metal-oxide-semiconductor is as error
Second input terminal of amplifier, the first end of the 5th metal-oxide-semiconductor are connected to GND, and the control terminal of the 5th metal-oxide-semiconductor is defeated as bias current
Enter end.
The LDO circuit of the high PSRR quick response of this example further includes one for providing bias voltage, biased electrical
The biasing circuit of stream.
The following are the specific implementation processes of the utility model.
High PSRR quick response LDO in the utility model carries out emulation using SMIC0.18 μm of CMOS technology and tests
Card, wherein input voltage is 1.8V-3.3V, output voltage 1.6V, load capacitance 10pF, using the error amplifier of mutation
Inhibit the error amplifier to the amplification of power supply noise to replace traditional error amplifier, in power tube grid end and error
The power supply rejection ratio that feedback loop improves LDO in the utility model is accessed between amplifier out, is met in increment
Application performance in the Sigma-delta modulator of type.
In full frequency band, the power supply rejection ratio of traditional LDO is mainly put by the loop gain of LDO, output end load and error
The influence of the power supply rejection ratio of big device and reference voltage, power supply rejection ratio are not high enough.Application based on LDO in the utility model
Background, output end load are the capacitors of fixed value, increase loop gain, can effectively improve the power supply rejection ratio of low-frequency range, lead to
Crossing improves the power supply rejection ratio of error amplifier and reference voltage can also improve the voltage rejection ratio of LDO to a certain extent.And
Without in capacitive LDO, the power supply rejection ratio of high band is because become poorer without output end bulky capacitor, it is therefore desirable to improve
Circuit structure improves the power supply rejection ratio of LDO high band.
Fig. 1 is the structure chart of the high PSRR quick response LDO designed in the utility model.In figure, EA is load
The error amplifier being connected with output voltage is managed, metal-oxide-semiconductor Mp is power tube, and M2, M3 constitute negative feedback network, connect with diode
M1 pipe co- controlling power tube grid end voltage, resistance R1, R2 constitute feedback network.It compares with conventional structure, uses herein
The error amplifier of one mutation, the load pipe of error amplifier are connected with output end, effectively reduce input voltage ripple
By being amplified after error amplifier；It still joined in design and feedback loop constituted by metal-oxide-semiconductor M2 and M3, work as input voltage
When variation, influence of the input voltage to output voltage is effectively reduced by feedback loop adjusting.Simultaneously power tube grid end with
Diode is connected, and diode is directly connected with input voltage, so that the gate source voltage VGS of power tube is without mains voltage ripple
It influences, effectively improves the power supply rejection ratio of the medium-high frequency section of circuit.
Next the working principle for analyzing LDO first, to load from underloading to for heavy duty variation, when load is by light
Load sports when overloaded, and load current increases, and output voltage reduces, and by resistance R1, R2, samples output voltage variation, warp
Error amplifier amplification is crossed, output voltage error amplifier increases, and by common source configuration M2, common gate structure M3 makes power tube grid
Voltage is held to reduce, output electric current becomes larger, and output voltage restores to stablize.The source of metal-oxide-semiconductor M2 is connected with output voltage, at this time grid end
Voltage reduces, so that the electric current moment for flowing through M3 pipe becomes much larger, further speeds up the variation of power current.When load is from again
It carries mutation and arrives underloading situation similarly.
When supply voltage slightly increases, the drain-source current of power tube increases, and output electric current increases, and output voltage is drawn
Height flows through the increase of M2 pipe current, and the electric current for flowing through sampling resistor increases, and error amplifier output voltage reduces so that M2 is managed
The electric current of son further increases, it is assumed that bias current is not influenced by power supply, then M3 tube current reduces at this time, and because M1 pipe is
Diode connection, so power tube grid end voltage is raised at this time, output electric current reduces, and output voltage restores stationary value.Fig. 2 gives
The integrated circuit figure of high PSRR quick response LDO is gone out, left-hand component is biasing circuit in figure, for providing biased electrical
Pressure, bias current.
It is illustrated in figure 3 the simulation curve figure of the line regulation of the LDO, when load current is between 0A, 500uA, 1mA
Variation, input voltage from 1.8V-3.3V change, output voltage variation for be respectively 0.685mV, 0.711mV, 0.775mV according to
Line regulation calculation formula, it can be deduced that the line regulation of the LDO are as follows: 0.253mV/V, 0.263mV/V, 0.287mV/V.
The quiescent current of the LDO is only are as follows: 41.3uA.It, can from figure such as the PSRR simulation curve figure that Fig. 4 is the utility model LDO
It arrives, the PSRR minimum of the LDO can achieve -82dB, still have -49.33dB in 200kHZ.Fig. 5 is the load transient response of the LDO
Simulation curve figure, it can be seen from the figure that when load capacitance changes during the sampling period, the load transient response time of system
About 313ns.
The utility model devises the LDO circuit in a Sigma-delta modulator applied to incremental.This is practical
High PSRR quick response LDO in novel carries out simulating, verifying using SMIC0.18 μm of CMOS technology, wherein input electricity
Pressure is 1.8V-3.3V, and output voltage 1.6V, load capacitance 10pF are replaced traditional using the error amplifier of mutation
Error amplifier inhibits the error amplifier to the amplification of power supply noise, in power tube grid end and error amplifier output
Between access feedback loop improve the power supply rejection ratio of LDO in the utility model, improve electricity while quick response
Source inhibit than and it is low in energy consumption, meet the application performance in the Sigma-delta modulator of instrument amplifier.Finally to total
Design circuit has carried out emulation testing, the result after giving test.
It is the preferred embodiment of the utility model above, it is all to change according to made by technical solutions of the utility model, it is produced
Function without departing from technical solutions of the utility model range when, belong to the protection scope of the utility model.
Claims (6)
1. a kind of LDO circuit of high PSRR quick response, which is characterized in that including error amplifier, resistance R1, R2,
Metal-oxide-semiconductor Mp, M1, M2, M3, capacitor C1, CL, the first input end of the error amplifier are connected to reference voltage source, and error is put
One end of second input terminal of big device and R1, R2 one end connect, the other end of the load pipe end of error amplifier and R1, M2
First end, the second end of Mp, CL one end be connected, and the output end as entire LDO circuit, the output end of error amplifier
It is connect with the control terminal of one end of C1, M2, the first end of M1 is connected with the first end of Mp is connected to VDD, the second end of M1 and M1's
Control terminal, the control terminal of Mp, the connection of the second end of M3, the second end of M2 are connected and pass through with the first end of the other end of C1, M3
One current source is connected with the other end of R2 is connected to GND, and the control terminal of M3 is connected to bias voltage input, and the other end of CL connects
It is connected to GND.
2. the LDO circuit of high PSRR quick response according to claim 1, which is characterized in that Mp is in LDO circuit
In be power tube.
3. the LDO circuit of high PSRR quick response according to claim 1, which is characterized in that M1, M2 constitute negative
Feedback network.
4. the LDO circuit of high PSRR quick response according to claim 1, which is characterized in that R1, R2 constitute anti-
Present network.
5. the LDO circuit of high PSRR quick response according to claim 1, which is characterized in that the error is put
Big device includes the first to the 5th metal-oxide-semiconductor, and the first end of the first metal-oxide-semiconductor, the first end of the second metal-oxide-semiconductor are connected amplifies as error
The load pipe end of device, the second end of the first metal-oxide-semiconductor, the control terminal of the first metal-oxide-semiconductor, the control terminal of the second metal-oxide-semiconductor, which are connected, is connected to the
The second end of the second end of three metal-oxide-semiconductors, the second end of the second metal-oxide-semiconductor and the 4th metal-oxide-semiconductor is connected to the output of error amplifier
End, first input end of the control terminal of third metal-oxide-semiconductor as error amplifier, the first end of third metal-oxide-semiconductor and the 4th metal-oxide-semiconductor
First end, which is connected, is connected to the second end of the 5th metal-oxide-semiconductor, second input terminal of the control terminal of the 4th metal-oxide-semiconductor as error amplifier,
The first end of 5th metal-oxide-semiconductor is connected to GND, and the control terminal of the 5th metal-oxide-semiconductor is as bias current inputs.
6. the LDO circuit of high PSRR quick response according to claim 5, which is characterized in that further include a use
In offer bias voltage, the biasing circuit of bias current.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201820827256.3U CN208188715U (en) | 2018-05-31 | 2018-05-31 | The LDO circuit of high PSRR quick response |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201820827256.3U CN208188715U (en) | 2018-05-31 | 2018-05-31 | The LDO circuit of high PSRR quick response |
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| CN208188715U true CN208188715U (en) | 2018-12-04 |
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| CN201820827256.3U Expired - Fee Related CN208188715U (en) | 2018-05-31 | 2018-05-31 | The LDO circuit of high PSRR quick response |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108733118A (en) * | 2018-05-31 | 2018-11-02 | 福州大学 | A kind of high PSRR quick response LDO |
| CN110017905A (en) * | 2019-05-22 | 2019-07-16 | 福州大学 | The reading circuit and its control method of high performance infrared thermopile sensor |
-
2018
- 2018-05-31 CN CN201820827256.3U patent/CN208188715U/en not_active Expired - Fee Related
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108733118A (en) * | 2018-05-31 | 2018-11-02 | 福州大学 | A kind of high PSRR quick response LDO |
| CN110017905A (en) * | 2019-05-22 | 2019-07-16 | 福州大学 | The reading circuit and its control method of high performance infrared thermopile sensor |
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| GR01 | Patent grant | ||
| CF01 | Termination of patent right due to non-payment of annual fee | ||
| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20181204 |