CN208156542U - A kind of biasing circuit and the integration module based on GaAs PHEMT technique - Google Patents
A kind of biasing circuit and the integration module based on GaAs PHEMT technique Download PDFInfo
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- CN208156542U CN208156542U CN201820545750.0U CN201820545750U CN208156542U CN 208156542 U CN208156542 U CN 208156542U CN 201820545750 U CN201820545750 U CN 201820545750U CN 208156542 U CN208156542 U CN 208156542U
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Abstract
The utility model embodiment discloses a kind of biasing circuit and the integration module based on GaAs PHEMT technique.Wherein, biasing circuit includes：L grades of bias units；The output end of i-stage bias unit is electrically connected with the input terminal of (i-1)-th grade of bias unit；The input terminal of L grades of bias units is electrically connected with supply voltage output end；The 1st grade of output end of bias unit is electrically connected with the output end of biasing circuit；Every grade of bias unit includes the divider resistance being connected in series and at least one N-type transistor；The grid of each N-type transistor is electrically connected with drain electrode；Relationship of the output voltage and input voltage of any level-one bias unit at 1/2 power, the setting of L grades of bias units can reduce influence of the supply voltage to bias circuit output voltage.Technical solution provided by the embodiment of the utility model can solve the problems, such as that the bias voltage of the biasing circuit output of existing GaAs PHEMT technique is influenced vulnerable to supply voltage.
Description
Technical field
The utility model embodiment is related to technical field of radio frequency integrated circuits more particularly to a kind of biasing circuit and is based on
The integration module of GaAs PHEMT technique.
Background technique
Biasing circuit can provide determining voltage bias or current offset for the functional module in integrated circuit, guarantee function
It can module normal work.But the output signal of existing biasing circuit is easy to be influenced by technique, supply voltage, temperature.It is special
It is not in some applications, mains voltage variations range is larger, and fluctuating biggish supply voltage is becoming influence biasing circuit just
The principal element of perseverance energy.
In RF communication system, because of the counterfeit modulation doping heterojunction field effect transistor of GaAs (GaAs)
(pseudomorphic high-electron-mobility transistor, PHEMT) technique has ultrahigh speed, low-power consumption
And the technological design radio frequency front end chip is widely used in the advantages of low noise, the producer.But since the technique can only realize one kind
Type field-effect tube, can not be the same with CMOS technology, realization two kinds of field-effect tube of p-type and N-type on same silicon substrate, therefore
Under GaAs PHEMT technique, influence of the supply voltage to bias voltage can not be avoided using bootstrap configuration.In mains fluctuations
Under biggish occasion, fluctuation is also also easy to produce using the bias voltage that the biasing circuit of GaAs PHEMT technique exports.
Utility model content
The utility model provides a kind of biasing circuit and the integration module based on GaAs PHEMT technique, existing to solve
The problem of bias voltage of the biasing circuit output of GaAs PHEMT technique is influenced vulnerable to supply voltage.
In a first aspect, the utility model embodiment provides a kind of biasing circuit, including：
L grades of bias units, L are the positive integer greater than 1；
The output end of i-stage bias unit is electrically connected with the input terminal of (i-1)-th grade of bias unit, and i is and to be less than greater than 1
Or the positive integer equal to L；The input terminal of L grades of bias units is electrically connected with supply voltage output end；1st grade of bias unit it is defeated
Outlet is electrically connected with the output end of the biasing circuit；
Every grade of bias unit includes the divider resistance being connected in series and at least one N-type transistor；The first of divider resistance
Connecting pin is electrically connected with the input terminal of this grade of bias unit, and second connection end is electrically connected with the output end of this grade of bias unit, and
It is electrically connected with the drain electrode of first N-type transistor at least one described N-type transistor；At least one described N-type transistor
In the last one N-type transistor source electrode ground connection；Wherein, the grid of each N-type transistor is electrically connected with drain electrode.
Optionally, the N-type transistor is the counterfeit modulation doping heterojunction field effect transistor of GaAs GaAs technique
PHEMT transistor.
Second aspect, the utility model embodiment additionally provide a kind of integration module based on GaAs PHEMT technique, packet
Include biasing circuit described in the utility model any embodiment.
Technical solution provided by the embodiment of the utility model, biasing circuit include multistage bias unit, afterbody biasing
The input terminal of unit connects supply voltage output end, the input of the output end connection prime bias unit of the bias unit of rear class
End, until the output end of the 1st grade of bias unit connects the output end of entire biasing circuit, multistage bias unit connection can be more than enough
Influence caused by bias voltage of the secondary fluctuation for weakening supply voltage to biasing circuit, and every grade of bias unit includes series connection
Divider resistance and at least one N-type transistor, the grid of each N-type transistor and drain electrode electrical connection, then each N-type transistor
It is equivalent to a diode, and first N-type transistor at least one N-type transistor passes through drain electrode and divider resistance electricity
Connection, the last one N-type transistor are grounded by source electrode, and each N-type transistor work is in the saturated condition.Any level-one biasing
For the output voltage and input voltage of unit at the relationship of 1/2 power, biasing circuit provided in this embodiment can be by above-mentioned more
The accumulation of grade bias unit, can be greatly lowered the influence for the bias voltage that supply voltage exports biasing circuit, in power supply
When voltage fluctuation is larger, bias voltage can provide stable voltage supply also for various functional modules, solve existing
The problem of bias voltage of the biasing circuit output of GaAs PHEMT technique is influenced vulnerable to supply voltage.
Detailed description of the invention
Fig. 1 is a kind of structural schematic diagram of biasing circuit provided by the embodiment of the utility model；
Fig. 2 is the equivalent circuit diagram of the 2nd grade of bias unit provided by the embodiment of the utility model；
Fig. 3 is the bias voltage of biasing circuit provided by the embodiment of the utility model with mains voltage variations schematic diagram.
Specific embodiment
The utility model is described in further detail with reference to the accompanying drawings and examples.It is understood that herein
Described specific embodiment is used only for explaining the utility model, rather than the restriction to the utility model.It further needs exist for
It is bright, part relevant to the utility model is illustrated only for ease of description, in attached drawing rather than entire infrastructure.
The utility model embodiment provides a kind of biasing circuit, is provided by the embodiment of the utility model with reference to Fig. 1, Fig. 1
A kind of structural schematic diagram of biasing circuit, the biasing circuit include：
L grades of bias units, L are the positive integer greater than 1；
The output end of i-stage bias unit is electrically connected with the input terminal of (i-1)-th grade of bias unit, and i is and to be less than greater than 1
Or the positive integer equal to L；The input terminal V of L grades of bias unitsinLIt is electrically connected with supply voltage output end VDD；1st grade of biasing is single
The output end V of memberO1With the output end V of biasing circuitOElectrical connection；
Every grade of bias unit includes the divider resistance being connected in series and at least one N-type transistor；The first of divider resistance
Connecting pin is electrically connected with the input terminal of this grade of bias unit, and second connection end is electrically connected with the output end of this grade of bias unit, and
It is electrically connected with the drain electrode of first N-type transistor at least one N-type transistor；It is last at least one N-type transistor
The source electrode ground connection of one N-type transistor；Wherein, the grid of each N-type transistor is electrically connected with drain electrode.
As shown in Figure 1, biasing circuit provided in this embodiment includes the 1st grade of bias unit, the 2nd grade of bias unit, according to this
Analogize, until L grades of bias units, the input terminal of previous stage bias unit are electrically connected with the output end of rear stage bias unit,
With reference to Fig. 1, the input terminal V of the 1st grade of bias unitin1With the output end V of the 2nd grade of bias unitO2Electrical connection, it is assumed that i can take not
It is 1, but is no more than the positive integer of L, then the output end of i-stage bias unit and the input terminal of (i-1)-th grade of bias unit is electrically connected
It connects, to form cascade bias unit structure, optionally, L is at least 2, i.e. biasing circuit includes at least two-stage bias unit,
And the input terminal V of L grades of bias unitsinLObtain operating voltage from supply voltage output end VDD, the 1st grade of bias unit it is defeated
Outlet VO1Then with the output end V of biasing circuitOElectrical connection forms the entire biasing circuit in the present embodiment.
Every grade of bias unit all includes concatenated divider resistance and at least one N-type transistor, and the number of N-type transistor can
Think one, or it is multiple, for example, the 1st grade of biasing circuit may include divider resistance R1With a N-type transistor M11, such as
Shown in Fig. 1, certainly, the 1st grade of biasing circuit can also include multiple N-type transistors, and the present embodiment is in every grade of bias unit
The number of N-type transistor is without limiting, as shown in Figure 1, the 2nd grade of biasing circuit may include branch pressure voltage R2With two N-types
Transistor M21And M22, divider resistance R2The first connecting pin and the 2nd grade of biasing circuit input terminal Vin2Electrical connection, the second connection
End and first N-type transistor M in multiple N-type transistors21Drain electrode electrical connection, first N-type transistor M21Source electrode with
Second N-type transistor M22Drain electrode electrical connection, second N-type transistor M22Source electrode ground connection, thus formed divider resistance with
Multiple concatenated structures of N-type transistor, wherein the drain and gate of each N transistor npn npn is electrically connected, and is equivalent to diode.Ginseng
Fig. 2 is examined, Fig. 2 is the equivalent circuit diagram of the 2nd grade of bias unit provided by the embodiment of the utility model, branch pressure voltage R2Pass through two
Concatenated diode ground connection.
In addition, every grade of bias unit may be concatenated divider resistance and at least one P-type transistor, then divider resistance
Second connection end be electrically connected with the source electrode of first P-type transistor at least one P-type transistor；At least one p-type is brilliant
The grounded drain of the last one P-type transistor in body pipe, for example, if this grade of bias unit includes concatenated divider resistance and two
A P-type transistor, the second connection end of divider resistance are electrically connected with the source electrode of first P-type transistor, first P-type transistor
Drain electrode be electrically connected with the source electrode of second P-type transistor, the grounded drain of second P-type transistor, all P-type transistors
Grid and source electrode electrical connection be equivalent to diode.Cascade bias unit described in the present embodiment can be prevented by multistage pressure stabilizing
Only mains fluctuations generate excessive influence to bias circuit output voltage, this biasing circuit realizes that simply versatility is stronger.
But in RF communication system, because GaAs PHEMT technique has the excellent of ultrahigh speed, low-power consumption and low noise
Point, the producer mostly uses the various functional circuits of the technological design, and because GaAs PHEMT technique is only able to achieve the transistor of N-type
Structure when then realizing biasing circuit provided in this embodiment using GaAs PHEMT technique is only capable of that N is arranged in bias unit
Transistor npn npn.Optionally, N-type transistor is PHEMT transistor.PHEMT transistor is a kind of using on GaAs (GaAs)
The radio frequency GaAs Power transistor of the special epitaxial layer manufacture of growth, PHEMT transistor are being used for cellular phone and radio frequency tune
It can be realized low-voltage, efficient performance when on modulator-demodulator.Because entire functional circuit is all using GaAs PHEMT work
Skill, then form biasing circuit described in the present embodiment on the basis of the technique, and simple process saves cost of manufacture.
Biasing circuit provided by the embodiment of the utility model, biasing circuit include multistage bias unit, afterbody biasing
The input terminal of unit connects supply voltage output end, the input of the output end connection prime bias unit of the bias unit of rear class
End, until the output end of the 1st grade of bias unit connects the output end of entire biasing circuit, multistage bias unit connection can be more than enough
Influence caused by bias voltage of the secondary fluctuation for weakening supply voltage to biasing circuit, and every grade of bias unit includes series connection
Divider resistance and at least one N-type transistor, the grid of each N-type transistor and drain electrode electrical connection, then each N-type transistor
It is equivalent to a diode, and first N-type transistor at least one N-type transistor passes through drain electrode and divider resistance electricity
Connection, the last one N-type transistor are grounded by source electrode, and each N-type transistor work is in the saturated condition.Any level-one biasing
For the output voltage and input voltage of unit at the relationship of 1/2 power, biasing circuit provided in this embodiment can be by above-mentioned more
Adding up for grade bias unit, can be greatly lowered the influence for the bias voltage that supply voltage exports biasing circuit, in power supply
When voltage fluctuation is larger, bias voltage can provide stable voltage supply also for various functional modules, solve existing
The problem of bias voltage of the biasing circuit output of GaAs PHEMT technique is influenced vulnerable to supply voltage.
Optionally, P grades of bias units include the divider resistance and P PHEMT transistor being connected in series, P to be greater than or
Equal to 1, and it is less than or equal to the positive integer of N.I.e. the number of current bias unit can be identical with the series of current bias unit,
As shown in Figure 1, settable 1st grade of bias unit includes 1 PHEMT transistor, the 2nd grade of bias unit includes 2 PHEMT crystalline substances
Body pipe, and so on, L grades of bias units include L PHEMT transistor.Biasing circuit output end V in order to preventOOutput
Bias voltage is too low, and bias unit series is higher, and the number of the PHEMT transistor of setting is more, to guarantee that every grade of biasing is single
The voltage value of first output voltage is not too low, and to a certain extent, PHEMT transistor is equivalent to partial pressure pipe, prevents divider resistance two
Overtension is held, the bias voltage that biasing circuit is exported drives related circuit.
In order to more clearly describe the relationship of biasing circuit output bias voltage and supply voltage, the serial calculations of following progress
Number derives.Operating voltage setting and saturation state by PHEMT transistor, it was known that electric current of the PHEMT transistor in saturation region
IDSATWith gate source voltage VGSRelationship is：
Wherein, q indicates electronic charge, WD/ L indicates the breadth length ratio of PHEMT transistor, μoIndicate electron mobility, VGT
Indicate grid source threshold voltage, n2DIndicate the concentration of two-dimensional electron gas, concentration and the PHEMT transistor of the two-dimensional electron gas
GaAs PHEMT technique is related.
The then output voltage Vo and input voltage V of the 1st grade of bias unitin1Relationship be：
Vin1=VO+IDSAT·R1
Derivation can obtain：
Wherein：
Then
In the present embodiment, the 2nd grade of bias unit is by resistance R2The PHEMT transistor M being connect with 2 grid leak poles21、M22String
Connection.
With same principle described in the 1st grade of bias unit, then
It can further prove：
In the present embodiment, L grades of bias units are by resistance RnThe PHEMT transistor M being connect with L grid leak poleL1、
ML2、……、MLLSeries connection.
With same principle described in the 1st grade of bias unit, then
And so on：
Show referring to the bias voltage that Fig. 3, Fig. 3 are biasing circuits provided by the embodiment of the utility model with mains voltage variations
It is intended to.V in figureDDIndicate supply voltage, VOIt indicates the bias voltage of biasing circuit output, is respectively illustrated in Fig. 3 and work as biased electrical
When road includes 1 grade, 2 grades and L grades of bias units, bias voltage VOWith supply voltage VDDChange curve, from the figure 3, it may be seen that with
Bias unit series is incremented by, and influence of the supply voltage to the bias voltage that biasing circuit output end exports is smaller and smaller.Work as biasing
When unit series increases to L, the bias voltage of biasing circuit output end output is basically unchanged.
Optionally, one or more performance parameters of each PHEMT transistor in every level-one bias unit are identical.It is optional
, performance parameter includes the breadth length ratio W of electronic charge q, transistorD/ L, electron mobility μo, grid source threshold voltage VGTWith
And the concentration n of two-dimensional electron gas2D.With reference to the above-mentioned derivation process that counts it is found that if each PHEMT in every level-one bias unit is brilliant
One or more performance parameters of body pipe are identical, then derivation process is easy to simplify, bias voltage V because parameter is identicalOAnd power supply
Voltage VDDBetween relationship be also easier to obtain, convenient for the design of entire biasing circuit.Certainly, if in all grades of bias units
One or more performance parameters of PHEMT transistor are identical, are more favorable for obtaining the stronger biasing circuit of stability.Likewise,
For convenient for bias circuit, optionally, the resistance value of the divider resistance of every grade of bias unit is all the same.
The present embodiment additionally provides a kind of integration module based on GaAs PHEMT technique, including the utility model is arbitrarily real
Biasing circuit described in example is applied, biasing circuit can provide reliable biased electrical for the integration module based on GaAs PHEMT technique
Pressure.
Note that above are only the preferred embodiment and institute's application technology principle of the utility model.Those skilled in the art's meeting
Understand, the utility model is not limited to specific embodiment described here, is able to carry out for a person skilled in the art various bright
Aobvious variation is readjusted, be combined with each other and is substituted without departing from the protection scope of the utility model.Therefore, although passing through
Above embodiments are described in further detail the utility model, but the utility model is not limited only to the above implementation
Example can also include more other equivalent embodiments in the case where not departing from the utility model design, and the utility model
Range is determined by the scope of the appended claims.
Claims (3)
1. a kind of biasing circuit, which is characterized in that including：
L grades of bias units, L are the positive integer greater than 1；
The output end of i-stage bias unit is electrically connected with the input terminal of (i-1)-th grade of bias unit, and i is and to be less than or wait greater than 1
In the positive integer of L；The input terminal of L grades of bias units is electrically connected with supply voltage output end；The output end of 1st grade of bias unit
It is electrically connected with the output end of the biasing circuit；
Every grade of bias unit includes the divider resistance being connected in series and at least one N-type transistor；First connection of divider resistance
End be electrically connected with the input terminal of this grade of bias unit, second connection end is electrically connected with the output end of this grade of bias unit, and with institute
State the drain electrode electrical connection of first N-type transistor at least one N-type transistor；In at least one described N-type transistor
The source electrode of the last one N-type transistor is grounded；Wherein, the grid of each N-type transistor is electrically connected with drain electrode.
2. biasing circuit according to claim 1, it is characterised in that：
The N-type transistor is the counterfeit modulation doping heterojunction field effect transistor PHEMT transistor of GaAs GaAs technique.
3. a kind of integration module based on GaAs PHEMT technique, which is characterized in that including any one of the claims 1-2 institute
The biasing circuit stated.
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108334150A (en) * | 2018-04-17 | 2018-07-27 | 江苏卓胜微电子股份有限公司 | A kind of biasing circuit and the integration module based on GaAs PHEMT techniques |
| CN114721455A (en) * | 2022-03-16 | 2022-07-08 | 苏州悉芯射频微电子有限公司 | Bypass switch bias voltage generation circuit |
| CN114924605A (en) * | 2022-05-13 | 2022-08-19 | 苏州悉芯射频微电子有限公司 | Laminated ESD Power Clamp bias voltage generation circuit |
-
2018
- 2018-04-17 CN CN201820545750.0U patent/CN208156542U/en active Active
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108334150A (en) * | 2018-04-17 | 2018-07-27 | 江苏卓胜微电子股份有限公司 | A kind of biasing circuit and the integration module based on GaAs PHEMT techniques |
| CN114721455A (en) * | 2022-03-16 | 2022-07-08 | 苏州悉芯射频微电子有限公司 | Bypass switch bias voltage generation circuit |
| CN114721455B (en) * | 2022-03-16 | 2023-06-20 | 苏州悉芯射频微电子有限公司 | Bypass switch bias voltage generating circuit |
| CN114924605A (en) * | 2022-05-13 | 2022-08-19 | 苏州悉芯射频微电子有限公司 | Laminated ESD Power Clamp bias voltage generation circuit |
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