CN208141379U - The layout structure of dedicated IC chip - Google Patents
The layout structure of dedicated IC chip Download PDFInfo
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- CN208141379U CN208141379U CN201820492851.6U CN201820492851U CN208141379U CN 208141379 U CN208141379 U CN 208141379U CN 201820492851 U CN201820492851 U CN 201820492851U CN 208141379 U CN208141379 U CN 208141379U
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Abstract
The utility model embodiment proposes a kind of layout structure of dedicated IC chip, it is respectively formed the first input and output region and the second input and output region in the first edge of dedicated IC chip and opposite second edge, first input and output region and the second input and output region respectively include the input-output unit of multiple parallel arrangeds, and wherein phase-locked loop is set to the first input and output region or the second input and output region.The utility model embodiment in terms of existing technologies, saves the area in the input and output region of chip two sides, and phase-locked loop is not take up the region area for calculating kernel, to avoid the area of waste chip calculating kernel.
Description
Technical field
The utility model relates to integrated circuit fields, more particularly to a kind of layout structure of dedicated IC chip.
Background technique
Block chain technology is the structure verification and storing data using block chain type, wherein the data cell of verifying and storage is adopted
With digital signature encryption mode, realize the recipient of data cell to confirm the source of data cell and the integrality of data cell,
And data are protected, prevent data cell to be tampered or forge.Block chain technology can be used for cloud computing, Internet of Things, e-commerce,
The various fields such as authentication, file storage, financial transaction, digital cash, wherein digital cash field generallys use SHA-256
Secure hash algorithm (Secure Hash Algorithm, SHA) is digitally signed.
Block chain dedicated IC chip (also known as asic chip) is calculating most basic, most crucial in block Chain System
Equipment.The block chain dedicated IC chip category that SHA-256 algorithm ultrahigh speed computes repeatedly is realized for digital cash field
In the full custom chip for being directed to SHA-256 algorithm, generally include to calculate kernel and communication interface modules.
As shown in Figure 1, the prior art is when designing this dedicated IC chip, it is usually that the input of interface module is defeated
(I/O) cell distribution is in the surrounding of chip out, be simply input output unit include several electrostatic protections (ESD) pipe and it is several and
Or logic unit, complicated input-output unit then may include the circuit of hundreds of or even up to ten thousand scales.It is distributed in chip
The input-output unit of surrounding constitutes the input and output region of annular, and in input and output region, annular electric supply power supply line is
Each input-output unit power supply, power supply line form complete annular electric supply circuit by the metal layer of different layers, and one complete
Annular electric supply loop strong ESD protection can be provided simultaneously.However, this cloth that input-output unit is arranged in chip surrounding
Office's structure needs to occupy the fringe region of chip surrounding, reduces the region area for calculating kernel；In addition, complete in order to guarantee
Annular electric supply circuit, the phase-locked loop (PLL) of chip, which is generally disposed at, to be calculated in kernel, is further wasted chip and is calculated kernel
Region area.When the region area for improving chip calculating kernel is also dedicated IC chip design, what emphasis considered is asked
Topic.
Utility model content
To solve the above-mentioned problems, one aspect according to the present utility model proposes a kind of dedicated IC chip
Layout structure, including：
It is arranged in the first input and output region of the first edge of the dedicated IC chip, first input is defeated
Region includes input-output unit out；
The second input for being arranged in the second edge opposite with the first edge of the dedicated IC chip is defeated
Region out, second input and output region includes input-output unit；
It wherein, include phase-locked loop in first input and output region or the second input and output region.
In some embodiments, first input and output region and the second input and output region respectively include it is multiple simultaneously
The input-output unit of row arrangement.
In some embodiments, the phase-locked loop is set to first input and output region or the second input and output
Combined one end of the input-output unit of multiple parallel arrangeds in region.
In some embodiments, the layout structure further includes defeated to first input and output region and the second input
The independent power supply circuit or middle position that region powers respectively out.
In some embodiments, the power supply circuit or middle position are used for the power supply side in chip input and output
With the power supply of starlike connection type between first input and output region and the second input and output region.
In some embodiments, the layout structure further comprises calculating kernel area；The calculating kernel area
Intermediate region between first input and output region and the second input and output region.
In some embodiments, the kernel area that calculates includes the array that multiple logic unit blocks form, described more
The array of a logic unit block composition includes symmetrical two column, and multirow is arranged in each column, and every row arranges a logic unit block,
Wherein logic unit block is in the structure of thin-and-long.
In some embodiments, the logic unit block includes the first arithmetic element and the second arithmetic element, and described the
One arithmetic element is for executing first time operation, and second arithmetic element is for executing second of operation.
In some embodiments, first arithmetic element is connected to second arithmetic element, wherein described first
The result that arithmetic element executes first time operation executes second of operation for second arithmetic element.
In some embodiments, first arithmetic element and the second arithmetic element respectively include M level production line operation
Unit, the M level production line arithmetic element is arranged using end to end thin-and-long, and the 1st grade of flowing water of the second arithmetic element
Line arithmetic element and the M level production line arithmetic element of the first arithmetic element join end to end, and M is the integer greater than 1.
In some embodiments, the M level production line arithmetic element respectively includes computing module and memory module, described
Computing module is for executing pipeline operations at different levels, and the memory module is for saving operation results at different levels.
In some embodiments, in the M level production line arithmetic element junior's pipeline operation unit computing module
It is connected with the memory module of higher level's pipeline operation unit.
In some embodiments, first arithmetic element and the second arithmetic element are for executing SHA-256 operation.
In some embodiments, the M level production line arithmetic element includes 64 level production line arithmetic elements.
In some embodiments, the logic unit block receives the operational data that the input-output unit is sent, and holds
Row data operation, and operation result is exported to the input-output unit.
The layout structure for the dedicated IC chip that utility model the utility model embodiment proposes eliminates existing skill
The area in the input and output region of chip the right and left in art also saves to provide strong ESD protection and forms annular electric supply
Area needed for circuit, and phase-locked loop is set in the input and output region of chip, is also not take up the region for calculating kernel
Area, the chip area of saving are completely used for calculating kernel, to avoid the area of waste chip calculating kernel.
Detailed description of the invention
Fig. 1 is the schematic diagram of the layout structure of the dedicated IC chip of the prior art；
Fig. 2 is the schematic diagram according to the layout structure of the dedicated IC chip of an embodiment of the present invention；
Fig. 3 is the schematic diagram according to the layout structure of the dedicated IC chip of another embodiment of the utility model；
Fig. 4 is the schematic diagram according to the layout structure of the dedicated IC chip of another embodiment of the utility model；
Fig. 5 is the schematic diagram according to the layout structure of the dedicated IC chip of another embodiment of the utility model；
Fig. 6 is the schematic diagram according to the layout structure of the dedicated IC chip of another embodiment of the utility model；
Fig. 7 is the structural representation according to the logic unit block of the dedicated IC chip of an embodiment of the present invention
Figure.
Fig. 8 is the flow diagram according to the layout method of the dedicated IC chip of an embodiment of the present invention；
Fig. 9 is illustrated according to the process of the layout method of the dedicated IC chip of another embodiment of the utility model
Figure；
Figure 10 is illustrated according to the process of the layout method of the dedicated IC chip of another embodiment of the utility model
Figure；And
Figure 11 is the structural schematic diagram according to the electronic equipment of an embodiment of the present invention.
Specific embodiment
For the purpose of this utility model, technical solution and advantage is more clearly understood, below in conjunction with specific embodiment, and
Referring to attached drawing, the utility model is further described.The utility model embodiment for ease of description, the utility model are attached
It is shown merely for illustrating the necessary parts of the utility model aim in figure.
Fig. 2 is the schematic diagram according to the layout structure of the dedicated IC chip of an embodiment of the present invention.Such as Fig. 2
Shown, the layout structure of dedicated IC chip described in the utility model embodiment includes：It is arranged in the first edge of chip
Region input and output (I/O) 12 and be arranged in chip the second edge opposite with the first edge input and output (I/
O) region 13.Two independent input and output regions 12 and 13 respectively include input and output (I/O) unit 120.Input and output (I/
O) unit 120 can be one or more parallel arrangeds.
Kernel area 11 is calculated between independent input and output (I/O) region 12 and 13, including for executing
The logic unit block array of data operation.Logic unit block can execute the Encryption Algorithm of SHA series or other data are calculated
Method, including but not limited to SHA-256 algorithm.
In some embodiments, the layout structure further includes distinguishing the independent input and output region 12 and 13
The independent power supply circuit of power supply.Specifically, the power supply circuit is used for power supply side and institute in chip input and output
It states between input and output region 12 and 13 with the power supply of starlike connection type.To region independent input and output (I/O) 12 and 13 points
Annular electric supply circuit in the prior art Gong electricity be different from, strong ESD protection is provided, a degree of ESD to chip is only provided
Protection, but eliminate chip the right and left input and output region and annular electric supply needed for circuit area.
The layout structure for the dedicated IC chip that the utility model embodiment proposes eliminates chip in the prior art
The area in the input and output region of the right and left is also saved to provide strong ESD protection and is formed needed for annular electric supply circuit
Area, the chip area of saving be completely used for calculate kernel, thus avoid waste chip calculate kernel area.
Fig. 3 is the schematic diagram according to the layout structure of the dedicated IC chip of another embodiment of the utility model.Such as
Shown in Fig. 3, the layout structure of dedicated IC chip described in the utility model embodiment includes：It is arranged in the first side of chip
Region input and output (I/O) 12 of edge and be arranged in chip the second edge opposite with the first edge input and output
(I/O) region 13.Two independent input and output regions 12 and 13 respectively include input and output (I/O) unit 120.Input and output
(I/O) unit 120 can be one or more parallel arrangeds.
It wherein, further include phase-locked loop (PLL) 130 in the input and output region 12.In some embodiments, locking phase
Circuit 130 is set to combined one end of the input-output unit 120 of multiple parallel arrangeds.
Kernel area 11 is calculated between independent input and output (I/O) region 12 and 13, including for executing
The logic unit block array of data operation.Logic unit block can execute the Encryption Algorithm of SHA series or other data are calculated
Method, including but not limited to SHA-256 algorithm.
In some embodiments, the layout structure further includes distinguishing the independent input and output region 12 and 13
The independent power supply circuit of power supply or middle position.Specifically, the power supply circuit or middle position are used to input in chip
With the power supply of starlike connection type between the power supply side of output and the input and output region 12 and 13.It is defeated to independent input
Region (I/O) 12 and 13 powers respectively out is different from the strong ESD protection of annular electric supply circuit in the prior art offer, only offer pair
A degree of ESD of chip is protected, but is eliminated needed for the input and output region and annular electric supply of chip the right and left
Circuit area.For example, one PD of setting is the region 12 or 13 input and output (I/O) in region input and output (I/O) 12 or 13
Interior all I/O unit power supplies, are supplied to opposite end I/O unit for the voltage on PAD by conductor wire.
The layout structure for the dedicated IC chip that the utility model embodiment proposes eliminates chip in the prior art
The area in the input and output region of the right and left is also saved to provide strong ESD protection and is formed needed for annular electric supply circuit
Area, and phase-locked loop is set in the input and output region of chip, is also not take up the region area for calculating kernel, is saved
Chip area be completely used for calculate kernel, thus avoid waste chip calculate kernel area.
Fig. 4 is the schematic diagram according to the layout structure of the dedicated IC chip of another embodiment of the utility model.Such as
Shown in Fig. 4, the layout structure of dedicated IC chip described in the utility model embodiment includes：It is arranged in the first side of chip
Region input and output (I/O) 12 of edge and be arranged in chip the second edge opposite with the first edge input and output
(I/O) region 13.Two independent input and output regions 12 and 13 respectively include input and output (I/O) unit 120.Input and output
(I/O) unit 120 can be one or more parallel arrangeds.
It wherein, further include phase-locked loop (PLL) 130 in the input and output region 13.In some embodiments, locking phase
Circuit 130 is set to combined one end of the input-output unit 120 of multiple parallel arrangeds.
Kernel area 11 is calculated between independent input and output (I/O) region 12 and 13, including for executing
The logic unit block array of data operation.Logic unit block can execute the Encryption Algorithm of SHA series or other data are calculated
Method, including but not limited to SHA-256 algorithm.
In some embodiments, the layout structure further includes distinguishing the independent input and output region 12 and 13
The independent power supply circuit of power supply or middle position.Specifically, the power supply circuit or middle position are used to input in chip
With the power supply of starlike connection type between the power supply side of output and the input and output region 12 and 13.It is defeated to independent input
Region (I/O) 12 and 13 powers respectively out is different from the strong ESD protection of annular electric supply circuit in the prior art offer, only offer pair
A degree of ESD of chip is protected, but is eliminated needed for the input and output region and annular electric supply of chip the right and left
Circuit area.
The layout structure for the dedicated IC chip interface module that the utility model embodiment proposes eliminates existing skill
The area in the input and output region of chip the right and left in art also saves to provide strong ESD protection and forms annular electric supply
Area needed for circuit, and phase-locked loop is set in the input and output region of chip, is also not take up the region for calculating kernel
Area, the chip area of saving are completely used for calculating kernel, to avoid the area of waste chip calculating kernel.
Fig. 5 is the schematic diagram according to the layout structure of the dedicated IC chip of another embodiment of the utility model.Such as
Shown in Fig. 5, the layout structure 10 of dedicated IC chip described in the utility model embodiment mainly includes：It is arranged in chip
Region input and output (I/O) 12 of first edge and be arranged in chip the second edge opposite with the first edge input
Export region (I/O) 13.Two independent input and output regions 12 and 13 respectively include input and output (I/O) unit 120.Input
Exporting (I/O) unit 120 can be one or more parallel arrangeds.
It wherein, further include phase-locked loop (PLL) 130 in the input and output region 13.Locking phase is only schematically shown in figure
Circuit 130 is set to input and output region 13, it also can be set in input and output region 12 certainly.
The layout structure further comprises calculating kernel area 11, calculates kernel area 11 and is arranged in the input and output
Intermediate region between region 12 and 13.Calculating kernel area 11 includes the array being made of multiple logic unit blocks 110.Logic
For cell block 110 using the structure of thin-and-long, the array being made of multiple logic unit blocks 110 includes symmetrical two
N row is arranged in column, each column, and every row arranges that a logic unit block 110, i.e., entire array are disposed with 2N logic unit block in total.
Region input and output (I/O) 12 and 13 respectively includes one or more input and output (I/O) unit, only illustrates in figure
Property show region input and output (I/O) 12 include input and output (I/O) unit 120_1 and 120_2, the region input and output (I/O)
13 include input and output (I/O) unit 120_3.In actual implementation, input that region input and output (I/O) 12 and 13 is respectively arranged
Output (I/O) unit can be not limited to quantity shown in Fig. 5.
In some embodiments, region input and output (I/O) 12 can also include control unit 140, input and output (I/
O) region 13 can also include linear voltage stabilization (LDO) unit 150.Control unit 140 is used to send data to logic unit block 110
And order, and receive the data and operating result of the feedback of logic unit block 110.Control unit 140 further comprises to logic list
The data that first block 110 is fed back carry out the function of further data processing.Linear voltage stabilization (LDO) unit 150 is used for phase-locked loop
(PLL) unit 130 and input-output unit 120_1,120_2 and 120_3 provide voltage.Control unit 140 is located at input and output
The centre of unit 120_1,120_2 or with input-output unit 120_1,120_2 adjoin, be located at input-output unit 120_1,
One side of 120_2.Here the position of control unit 140 is only exemplary explanation, and other modes are also protected by correlation.
Logic unit block 110 is the most crucial module for determining chip operational capability and power consumption for executing data operation.Often
A logic unit block receives the operational data that input and output (I/O) unit is sent, and executes individual operation, and export operation knot
The operation result of fruit, lower logical cell block is sent to input and output (I/O) unit by higher level's logic unit block.This is practical new
Logic unit block can execute the Encryption Algorithm or others data algorithm of SHA series in type embodiment, including but not limited to
SHA-256 algorithm.
In some embodiments, in the array that the logic unit block 110 forms, each column 57 rows of arrangement, i.e. N=57,
But the logic unit block number that each column is arranged in actual implementation can be according to the operational performance index allocation of chip, implementation without being limited thereto
Example.
Logic unit block in dedicated IC chip is configured to thin-and-long structure by the utility model embodiment, is conducive to
The smooth transmitting of logic unit block internal arithmetic data, and by the layout of logic unit block array two column multirows of composition, so that core
The calculating kernel area of piece is realized as far as possible close to the layout of square, avoids the waste of chip area, and pass through each column
The layout of multirow realizes the multiple logic unit blocks of each column, enhances the operational capability of chip.
Fig. 6 is the schematic diagram according to the layout structure of the dedicated IC chip of another embodiment of the utility model.Such as
Shown in Fig. 6, on the basis of embodiment shown in Fig. 5, each logic unit block 110 further comprises the first arithmetic element 201 and
Two arithmetic elements 202, first arithmetic element 201 and the second arithmetic element 202 respectively execute once-through operation, first fortune
It calculates unit 201 and executes a part of the result of first time operation as the input data of the second arithmetic element 202, for described the
Two arithmetic elements 202 execute second of operation.
The first arithmetic element 201 and the second arithmetic element 202 can execute adding for SHA series in the utility model embodiment
Close algorithm or other data algorithms, including but not limited to SHA-256 algorithm.
Fig. 7 is the structural representation according to the logic unit block of the dedicated IC chip of an embodiment of the present invention
Figure.First arithmetic element 201 and the second arithmetic element 202 are respectively included for M level production line needed for executing once-through operation
(PIPELINE) arithmetic element, M are the integer greater than 1.It is only wrapped in Fig. 3 with the first arithmetic element 201 and the second arithmetic element 202
Include execute SHA-256 operation 64 level production line arithmetic element 301_1~301_64 for illustrate, be embodied
In M level production line arithmetic element included by the first arithmetic element 201 and the second arithmetic element 202 series according to the calculation of execution
Depending on method.As shown in fig. 7, every level production line arithmetic element 301 includes computing module 401 and memory module 402, computing module
401 for executing the same level pipeline operation, and memory module 402 saves the operation result of the same level.
The 64 level production line arithmetic elements that first arithmetic element 201 and the second arithmetic element 202 respectively include join end to end,
1st level production line arithmetic element of the second arithmetic element 202 and the 64th level production line arithmetic element of the first arithmetic element 201 are first
Tail is connected, i.e. in the 64 level production line arithmetic elements that the first arithmetic element 201 and the second arithmetic element 202 respectively include, junior
The computing module 401 of pipeline operation unit is connect with the memory module 402 of higher level's pipeline operation unit, receives higher level's flowing water
Some of the operation result of line arithmetic element as the same level operational data.1st level production line operation of the second arithmetic element 202
The computing module 401 of unit is connect with the memory module 402 of the 64th level production line arithmetic element of the first arithmetic element 201, is connect
Receive a part of the operation result of the first arithmetic element 201 as the input data of the second arithmetic element 202.First arithmetic element
201 and second arithmetic element 202 pipeline operation units at different levels between using end to end thin-and-long arrange, may be implemented
The smooth transmitting of SHA-256 operational data twice.
First arithmetic element 201 receives the operational data that input and output (I/O) unit is sent, and successively executes first time SHA-
64 level production line operations of 256 operations, and export the operation of first time SHA-256 as a result, pass to the second arithmetic element 202 after
The continuous 64 level production line operations for executing second of SHA-256 operation, and export final operation result and return to input and output (I/O)
Unit.
In the utility model embodiment, since there are M level production line operation, every level production line operation lists for each arithmetic element
Member all individually obtain clock signal, therefore in logic unit block each arithmetic element the 1st level production line arithmetic element and M
The clock signal of level production line arithmetic element disunity.In order to overcome the clock signal of pipeline operation units at different levels to be difficult to
Operation result data are sent to control list by the afterbody pipeline operation unit of unified problem, the second arithmetic element 202
Member, rather than the first arithmetic element 201 is fed back to, but the remaining operation that do not complete, control unit are completed by control unit
After completing remaining operation, final operation result return is handled.
Here in conjunction with attached Figures 5 and 6 to the first arithmetic element 201_3 of the left side logic unit block 110_3 in attached drawing 7 and
Two arithmetic element 202_3 carry out working principle explanation.I/O unit is sent out by control unit to the first arithmetic element 201_3 first
Calculating task is sent, which can be sent to logic unit block 110_3 by logic unit block 110_1 and 110_2, can also
Calculating task is directly sent to logic unit block 110_3.The first arithmetic element 201_3 of logic unit block 110_3 receives
Calculating task, executes 64 level production line operations of first time SHA-256 operation, and operation result is sent to the second arithmetic element
202_3 executes 64 level production line operations of second of SHA-256 operation.Second arithmetic element 202_3 is by operation result by patrolling
It collects cell block 110_2 and 110_1 and is sent to the remaining operation that do not complete of control unit completion, control unit completes remaining operation
Afterwards, final operation result return is handled.Operation result directly can also be sent control unit by the second arithmetic element 202_3.
In some embodiments, the layout structure further includes distinguishing the independent input and output region 12 and 13
The independent power supply circuit of power supply or middle position.Specifically, the power supply circuit or middle position are used to input in chip
With the power supply of starlike connection type between the power supply side of output and the input and output region 12 and 13.It is defeated to independent input
Region (I/O) 12 and 13 powers respectively out is different from the strong ESD protection of annular electric supply circuit in the prior art offer, only offer pair
A degree of ESD of chip is protected, but is eliminated needed for the input and output region and annular electric supply of chip the right and left
Circuit area.For example, one PD of setting is the region 12 or 13 input and output (I/O) in region input and output (I/O) 12 or 13
Interior all I/O unit power supplies, are supplied to opposite end I/O unit for the voltage on silicon wafer pin PAD by conductor wire.
Fig. 8 is the flow diagram according to the layout method of the dedicated IC chip of an embodiment of the present invention.
As shown in figure 8, the layout method of the utility model embodiment includes the following steps：
Step S11 forms the first input and output region, first input in the first edge of dedicated IC chip
Output area includes input-output unit；
Step S12 forms second in the second edge opposite with the first edge of the dedicated IC chip
Input and output region, second input and output region includes input-output unit.
In the utility model embodiment, first input and output region and the second input and output region may include one
Or the input-output unit of multiple parallel arrangeds.
In some embodiments, the layout method further includes：
Step S13 is respectively arranged independent power supply electricity for first input and output region and the second input and output region
Road or middle position.
In some embodiments, the power supply circuit or middle position are used for the power supply side in chip input and output
With the power supply of starlike connection type between first input and output region and the second input and output region.
The layout method for the dedicated IC chip that the utility model embodiment proposes eliminates chip in the prior art
The area in the input and output region of the right and left is also saved to provide strong ESD protection and is formed needed for annular electric supply circuit
Area, the chip area of saving be completely used for calculate kernel, thus avoid waste chip calculate kernel area.
Fig. 9 is illustrated according to the process of the layout method of the dedicated IC chip of another embodiment of the utility model
Figure.As shown in figure 9, the layout method of the utility model embodiment includes the following steps：
Step S21 forms the first input and output region, first input in the first edge of dedicated IC chip
Output area includes input-output unit；
Step S22 forms second in the second edge opposite with the first edge of the dedicated IC chip
Input and output region, second input and output region includes input-output unit；
Phase-locked loop is arranged in first input and output region in step S23.
In some embodiments, the layout method further includes：
Step S24 is respectively arranged independent power supply electricity for first input and output region and the second input and output region
Road or middle position.
In some embodiments, the step S23 includes that phase-locked loop is set to first input and output region
In multiple parallel arrangeds input-output unit combined one end.
In some embodiments, the power supply circuit or middle position are used for the power supply side in chip input and output
With the power supply of starlike connection type between first input and output region and the second input and output region.
The layout method for the dedicated IC chip that the utility model embodiment proposes eliminates chip in the prior art
The area in the input and output region of the right and left is also saved to provide strong ESD protection and is formed needed for annular electric supply circuit
Area, and phase-locked loop is set in the input and output region of chip, is also not take up the region area for calculating kernel, is saved
Chip area be completely used for calculate kernel, thus avoid waste chip calculate kernel area.
Figure 10 is illustrated according to the process of the layout method of the dedicated IC chip of another embodiment of the utility model
Figure.As shown in Figure 10, the layout method of the utility model embodiment includes the following steps：
Step S31 forms the first input and output region, first input in the first edge of dedicated IC chip
Output area includes input-output unit；
Step S32 forms second in the second edge opposite with the first edge of the dedicated IC chip
Input and output region, second input and output region includes input-output unit；
Phase-locked loop is arranged in second input and output region in step S33.
In some embodiments, the layout method further includes：
Step S34 is respectively arranged independent power supply electricity for first input and output region and the second input and output region
Road or middle position.
In some embodiments, the step S33 includes that phase-locked loop is set to second input and output region
In multiple parallel arrangeds input-output unit combined one end.
In some embodiments, the power supply circuit or middle position are used for the power supply side in chip input and output
With the power supply of starlike connection type between first input and output region and the second input and output region.
In some embodiments, the layout method further comprises that setting calculates kernel area, the calculating kernel
Intermediate region of the region between first input and output region and the second input and output region.The calculating kernel area
Array including multiple logic unit blocks composition, the array of the multiple logic unit block composition include symmetrical two column,
Multirow is arranged in each column, and every row arranges a logic unit block, and wherein logic unit block is in the structure of thin-and-long.
In some embodiments, the logic unit block includes the first arithmetic element and the second arithmetic element, and described the
One arithmetic element is for executing first time operation, and second arithmetic element is for executing second of operation.
In some embodiments, first arithmetic element is connected to second arithmetic element, wherein described first
The result that arithmetic element executes first time operation executes second of operation for second arithmetic element.
In some embodiments, first arithmetic element and the second arithmetic element respectively include M level production line operation
Unit, the M level production line arithmetic element is arranged using end to end thin-and-long, and the 1st grade of flowing water of the second arithmetic element
Line arithmetic element and the M level production line arithmetic element of the first arithmetic element join end to end, and M is the integer greater than 1.
In some embodiments, the M level production line arithmetic element respectively includes computing module and memory module, described
Computing module is for executing pipeline operations at different levels, and the memory module is for saving operation results at different levels.
In some embodiments, in the M level production line arithmetic element junior's pipeline operation unit computing module
It is connected with the memory module of higher level's pipeline operation unit.
In some embodiments, first arithmetic element and the second arithmetic element are for executing SHA-256 operation.
In some embodiments, the M level production line arithmetic element includes 64 level production line arithmetic elements.
In some embodiments, the logic unit block receives the operational data that the input-output unit is sent, and holds
Row data operation, and operation result is exported to the input-output unit.
In some embodiments, a kind of computer is additionally provided, the layout comprising above-mentioned dedicated IC chip
Structure.
In some embodiments, a kind of computer readable storage medium is additionally provided, the executable finger of computer is stored with
It enables, the computer executable instructions are arranged to carry out the layout method of above-mentioned dedicated IC chip.
In some embodiments, a kind of computer program product is additionally provided, the computer program product includes depositing
The computer program on computer readable storage medium is stored up, the computer program includes program instruction, when described program refers to
When order is computer-executed, the computer is made to execute the layout method of above-mentioned dedicated IC chip.
Above-mentioned computer readable storage medium can be transitory computer readable storage medium, be also possible to non-transient meter
Calculation machine readable storage medium storing program for executing.
In some embodiments, a kind of electronic equipment is additionally provided, structure is as shown in figure 11, the electronic equipment packet
It includes：
In at least one processor (processor) 110, Figure 11 by taking a processor 110 as an example；And memory
(memory) 111, it can also include communication interface (Communication Interface) 112 and bus 113.Wherein, it handles
Device 110, communication interface 112, memory 111 can complete mutual communication by bus 113.Communication interface 112 can be used
It is transmitted in information.Processor 110 can call the logical order in memory 111, to execute the dedicated integrated of above-described embodiment
The layout method of circuit chip.
In addition, the logical order in above-mentioned memory 111 can be realized by way of SFU software functional unit and conduct
Independent product when selling or using, can store in a computer readable storage medium.
Memory 111 is used as a kind of computer readable storage medium, can be used for storing software program, journey can be performed in computer
Sequence, such as the corresponding program instruction/module of the method in the utility model embodiment.Processor 110 is stored in storage by operation
Software program, instruction and module in device 111, thereby executing functional application and data processing, i.e. the realization above method is real
Apply the layout method of the dedicated IC chip in example.
Memory 111 may include storing program area and storage data area, wherein storing program area can storage program area,
Application program needed at least one function；Storage data area, which can be stored, uses created data etc. according to terminal device.
In addition, memory 111 may include high-speed random access memory, it can also include nonvolatile memory.
The layout method for the dedicated IC chip that the utility model embodiment proposes eliminates chip in the prior art
The area in the input and output region of the right and left is also saved to provide strong ESD protection and is formed needed for annular electric supply circuit
Area, and phase-locked loop is set in the input and output region of chip, is also not take up the region area for calculating kernel, is saved
Chip area be completely used for calculate kernel, thus avoid waste chip calculate kernel area.
Particular embodiments described above has carried out into one the purpose of this utility model, technical scheme and beneficial effects
Step is described in detail, it should be understood that being not limited to this foregoing is merely specific embodiment of the utility model
Utility model, within the spirit and principle of the utility model, any modification, equivalent substitution, improvement and etc. done should all wrap
Containing being within the protection scope of the utility model.
Claims (15)
1. a kind of layout structure of dedicated IC chip, which is characterized in that including：
It is arranged in the first input and output region of the first edge of the dedicated IC chip, first I/O area
Domain includes input-output unit；
It is arranged in the second I/O area of the second edge opposite with the first edge of the dedicated IC chip
Domain, second input and output region includes input-output unit；
It wherein, include phase-locked loop in first input and output region or the second input and output region.
2. the layout structure of dedicated IC chip according to claim 1, which is characterized in that first input is defeated
Region and the second input and output region respectively include the input-output unit of multiple parallel arrangeds out.
3. the layout structure of dedicated IC chip according to claim 2, which is characterized in that the phase-locked loop is set
It is placed in the combination of the input-output unit of multiple parallel arrangeds in first input and output region or the second input and output region
One end.
4. the layout structure of dedicated IC chip according to claim 1 or 2, which is characterized in that the layout knot
Structure further include the independent power supply circuit powered respectively to first input and output region and the second input and output region or in
Between position.
5. the layout structure of dedicated IC chip according to claim 4, which is characterized in that the power supply circuit or
Middle position is used for power supply side and first input and output region and the second I/O area in chip input and output
With the power supply of starlike connection type between domain.
6. the layout structure of dedicated IC chip according to claim 1 or 2, which is characterized in that the layout knot
Structure further comprises calculating kernel area；The calculating kernel area is located at first input and output region and the second input is defeated
Intermediate region between region out.
7. the layout structure of dedicated IC chip according to claim 6, which is characterized in that the calculating inner core region
Domain includes the array of multiple logic unit block compositions, and the array of the multiple logic unit block composition includes symmetrical two
Multirow is arranged in column, each column, and every row arranges a logic unit block, and wherein logic unit block is in the structure of thin-and-long.
8. the layout structure of dedicated IC chip according to claim 7, which is characterized in that the logic unit block
Including the first arithmetic element and the second arithmetic element, first arithmetic element is for executing first time operation, second fortune
Unit is calculated for executing second of operation.
9. the layout structure of dedicated IC chip according to claim 8, which is characterized in that the first operation list
Member is connected to second arithmetic element, wherein the result that first arithmetic element executes first time operation is used for described second
Arithmetic element executes second of operation.
10. the layout structure of dedicated IC chip according to claim 9, which is characterized in that first operation
Unit and the second arithmetic element respectively include M level production line arithmetic element, and the M level production line arithmetic element is used and joined end to end
Thin-and-long arrangement, and the M level production line of the 1st level production line arithmetic element of the second arithmetic element and the first arithmetic element is transported
It calculates unit to join end to end, M is the integer greater than 1.
11. the layout structure of dedicated IC chip according to claim 10, which is characterized in that the M grades of flowing water
Line arithmetic element respectively includes computing module and memory module, and the computing module is described for executing pipeline operations at different levels
Memory module is for saving operation results at different levels.
12. the layout structure of dedicated IC chip according to claim 11, which is characterized in that the M grades of flowing water
The computing module of junior's pipeline operation unit is connected with the memory module of higher level's pipeline operation unit in line arithmetic element.
13. the layout structure of dedicated IC chip according to claim 12, which is characterized in that first operation
Unit and the second arithmetic element are for executing SHA-256 operation.
14. the layout structure of dedicated IC chip according to claim 13, which is characterized in that the M grades of flowing water
Line arithmetic element includes 64 level production line arithmetic elements.
15. the layout structure of dedicated IC chip according to claim 14, which is characterized in that the logic unit
Block receives the operational data that the input-output unit is sent, and executes data operation, and export and transport to the input-output unit
Calculate result.
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| CN201820492851.6U CN208141379U (en) | 2018-04-09 | 2018-04-09 | The layout structure of dedicated IC chip |
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| CN201820492851.6U CN208141379U (en) | 2018-04-09 | 2018-04-09 | The layout structure of dedicated IC chip |
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