CN108536989A - The layout structure and method of dedicated IC chip - Google Patents
The layout structure and method of dedicated IC chip Download PDFInfo
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- CN108536989A CN108536989A CN201810372342.4A CN201810372342A CN108536989A CN 108536989 A CN108536989 A CN 108536989A CN 201810372342 A CN201810372342 A CN 201810372342A CN 108536989 A CN108536989 A CN 108536989A
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Abstract
The embodiment of the present invention proposes a kind of layout structure of dedicated IC chip, it includes calculating kernel area and input and output region, it is described to calculate the array that kernel area includes multiple logic unit block compositions, the array of the multiple logic unit block composition includes symmetrical two row, multirow is arranged in each column, often one logic unit block of row arrangement；The input and output region includes the first input and output region of the first edge for being arranged in the dedicated IC chip and is arranged in the second input and output region of the second edge opposite with the first edge of the dedicated IC chip, and first input and output region and the second input and output region respectively include the input-output unit of at least one parallel arranged；Intermediate channel is provided between symmetrical array, intermediate channel is used to arrange the signal transmssion line in connection the first input and output region and the second input and output region.The embodiment of the present invention in terms of existing technologies, saves the area in the input and output region of chip both sides, and provided with units such as intermediate channel arrangement ESD, to avoid wasting the entire area of area and chip that chip calculates kernel.
Description
Technical field
The present invention relates to integrated circuit fields, the layout structure more particularly to a kind of dedicated IC chip and side
Method.
Background technology
Block chain technology is the structure verification and storage data using block chain type, wherein the data cell of verification and storage is adopted
With digital signature encryption mode, the recipient of data cell is realized to confirm the source of data cell and the integrality of data cell,
And data are protected, prevent data cell to be tampered or forge.Block chain technology can be used for cloud computing, Internet of Things, e-commerce,
The various fields such as authentication, file storage, financial transaction, digital cash, wherein digital cash field generally use SHA-256
Secure hash algorithm (Secure Hash Algorithm, SHA) is digitally signed.
Block chain dedicated IC chip (also known as asic chip) is calculating most basic, most crucial in block Chain System
Equipment.The block chain dedicated IC chip category that SHA-256 algorithm ultrahigh speeds compute repeatedly is realized for digital cash field
In the full custom chip for SHA-256 algorithms, generally include to calculate kernel and communication interface modules.
As shown in Figure 1, the prior art is when designing this dedicated IC chip, it is usually that the input of interface module is defeated
Go out (I/O) cell distribution chip surrounding, be simply input output unit include several electrostatic protections (ESD) pipe and it is several and
Or logic unit, complicated input-output unit may then include the circuit of hundreds of or even up to ten thousand scales.It is distributed in chip
The input-output unit of surrounding constitutes the input and output region of annular, and in input and output region, annular electric supply power cord is
Each input-output unit power supply, power cord form complete annular electric supply circuit by the metal layer of different layers, and one complete
Annular electric supply loop strong ESD protection can be provided simultaneously.However, this be arranged in chip surrounding by input-output unit
Layout structure needs to occupy the fringe region of chip surrounding, reduces the region area for calculating kernel.It improves chip and calculates kernel
Region area be also dedicated IC chip design when, emphasis considers the problems of.
Invention content
To solve the above-mentioned problems, according to an aspect of the present invention, a kind of layout of dedicated IC chip is proposed
Structure, including：
Kernel area and input and output region are calculated, it is described to calculate the battle array that kernel area includes multiple logic unit block compositions
The array of row, the multiple logic unit block composition includes symmetrical two row, and multirow is arranged in each column, and often row arrangement one is patrolled
Collect cell block (dhash block)；The input and output region includes the first side for being arranged in the dedicated IC chip
First input and output region (SYS_GLU) of edge and it is arranged in the opposite with the first edge of the dedicated IC chip
Second edge the second input and output region (bottom IO), first input and output region and the second I/O area
Domain respectively includes the input-output unit (IO) of at least one parallel arranged；It is provided with intermediate channel between symmetrical array
(middle_channel), intermediate channel is used to arrange the signal in connection the first input and output region and the second input and output region
Transmission line.
In some embodiments, the intermediate channel can further arrange that ESD and TS, the ESD are used for, the TS
For.
In some embodiments, the first input and output region can further arrange control unit (top_ctrl), control
Unit (top_ctrl) processed is used for.
In some embodiments, the input and output list in first input and output region or the second input and output region
Member is connected by control unit, carries out data or order transmission.
In some embodiments, the input-output unit in the second input and output region is passed by the signal of intermediate channel
Defeated line is connected with control unit, and control unit is connected with the input-output unit in the second input and output region again.
In some embodiments, first input and output region or the second input and output region further comprise locking phase
It is one or more in loop circuit PLL, MUX and CLK_GCU.
In some embodiments, logic unit block is in the structure of thin-and-long.
In some embodiments, first input and output region and the second input and output region respectively include it is multiple simultaneously
The input-output unit of row arrangement.
In some embodiments, the phase-locked loop PLL, MUX or CLK_GCU are set to first I/O area
One end of the combination of the input-output unit of multiple parallel arrangeds in domain or the second input and output region.
In some embodiments, the layout structure further includes defeated to first input and output region and the second input
Go out the independent power supply circuit or centre position that region powers respectively.
In some embodiments, the power supply circuit or centre position are used for the power supply side in chip input and output
It is powered with starlike connection type between first input and output region and the second input and output region.
In some embodiments, the logic unit block includes the first arithmetic element and the second arithmetic element, and described the
One arithmetic element is for executing first time operation, and second arithmetic element is for executing second of operation.
In some embodiments, first arithmetic element is connected to second arithmetic element, wherein described first
The result that arithmetic element executes first time operation executes second of operation for second arithmetic element.
In some embodiments, first arithmetic element and the second arithmetic element respectively include M level production line operations
Unit, the M level production lines arithmetic element is arranged using end to end thin-and-long, and the 1st grade of flowing water of the second arithmetic element
Line arithmetic element and the M level production line arithmetic elements of the first arithmetic element join end to end, and M is the integer more than 1.
In some embodiments, the M level production lines arithmetic element respectively includes computing module and memory module, described
Computing module is for executing pipeline operations at different levels, and the memory module is for preserving operation results at different levels.
In some embodiments, in the M level production lines arithmetic element subordinate's pipeline operation unit computing module
It is connected with the memory module of higher level's pipeline operation unit.
In some embodiments, first arithmetic element and the second arithmetic element are for executing SHA-256 operations.
In some embodiments, the M level production lines arithmetic element includes 64 level production line arithmetic elements.
In some embodiments, the logic unit block receives the operational data that the input-output unit is sent, and holds
Row data operation, and export operation result to the input-output unit.
In some embodiments, the logic unit block executes data operation, and operation result is sent to control unit
After being further processed operation result is exported to the input-output unit.
In some embodiments, a kind of computer is also provided, including application-specific integrated circuit core described in any one of the above embodiments
The layout structure of piece.
The layout structure and method for the dedicated IC chip that the embodiment of the present invention proposes eliminate prior art core
The area in the input and output region of piece the right and left also saves to provide strong ESD protections and forms annular electric supply circuit institute
The area needed, and phase-locked loop is set in the input and output region of chip, is also not take up the region area for calculating kernel, section
The chip area of province is completely used for calculating kernel, to avoid waste chip from calculating the area of kernel.Lead among chip setting
The signal transmssion line in the input and output region of peer end of the connection, technique aligned units TCD, electrostatic protection cell ESD and temperature are arranged in road
Sensing unit TS is spent, the area of chip is further reduced, improves the performance of chip, reduce its power.
Description of the drawings
Fig. 1 is the schematic diagram of the layout structure of the dedicated IC chip of the prior art；
Fig. 2 is the schematic diagram of the layout structure of dedicated IC chip according to an embodiment of the invention；
Fig. 3 is the schematic diagram of the layout structure of dedicated IC chip according to another embodiment of the present invention；
Fig. 4 is the schematic diagram of the layout structure of dedicated IC chip according to another embodiment of the present invention；
Fig. 5 is the schematic diagram of the layout structure of dedicated IC chip according to another embodiment of the present invention；
Fig. 6 is the schematic diagram of the layout structure of dedicated IC chip according to another embodiment of the present invention；
Fig. 7 is the structural schematic diagram of the logic unit block of dedicated IC chip according to an embodiment of the invention.
Fig. 8 is the flow diagram of the layout method of dedicated IC chip according to an embodiment of the invention；
Fig. 9 is the flow diagram of the layout method of dedicated IC chip according to another embodiment of the present invention.
Specific implementation mode
To make the objectives, technical solutions, and advantages of the present invention clearer, below in conjunction with specific embodiment, and reference
Attached drawing, the present invention is described in more detail.The embodiment of the present invention for convenience of description is shown merely in attached drawing of the present invention
The necessary parts of bright the object of the invention.
Fig. 2 is the schematic diagram of the layout structure of dedicated IC chip according to an embodiment of the invention.Such as Fig. 2 institutes
Show, the layout structure of dedicated IC chip described in the embodiment of the present invention includes：It is arranged in the input of the first edge of chip
Output area 12 and be arranged in chip the second edge opposite with the first edge input and output region 13.Two independences
Input and output region 12 and 13 respectively include input and output (I/O) unit 120.Input and output (I/O) unit 120 can be
One or more parallel arrangeds.
Kernel area 11 is calculated between the independent input and output region 12 and 13, including is used to execute data fortune
The logic unit block array of calculation.Logic unit block can execute the Encryption Algorithm of SHA series or other data algorithms, packet
It includes but is not limited to SHA-256 algorithms.
In some embodiments, the layout structure further includes distinguishing the independent input and output region 12 and 13
The independent power supply circuit of power supply.Specifically, the power supply circuit is used for the power supply side in chip input and output and institute
It states and is powered with starlike connection type between input and output region 12 and 13.It powers respectively to independent input and output region 12 and 13
Strong ESD protections are provided different from annular electric supply circuit in the prior art, a degree of ESD protections to chip are only provided,
But the input and output region for eliminating chip the right and left and the circuit area needed for annular electric supply.
The layout structure for the dedicated IC chip that the embodiment of the present invention proposes eliminates prior art chips or so
The area in the input and output region on both sides also saves to provide strong ESD protections and forms the face needed for annular electric supply circuit
Product, the chip area of saving are completely used for calculating kernel, to avoid waste chip from calculating the area of kernel.
Fig. 3 is the schematic diagram of the layout structure of dedicated IC chip according to another embodiment of the present invention.Such as Fig. 3 institutes
Show, the layout structure of dedicated IC chip described in the embodiment of the present invention includes：It is arranged in the input of the first edge of chip
Output area 12 and be arranged in chip the second edge opposite with the first edge input and output region 13.Two independences
Input and output region 12 and 13 respectively include input and output (I/O) unit 120.Input and output (I/O) unit 120 can be
One or more parallel arrangeds.
Wherein, in the input and output region 12 further include phase-locked loop (PLL) 130.In some embodiments, locking phase
Circuit 130 is set to one end of the combination of the input-output unit 120 of multiple parallel arrangeds.
Kernel area 11 is calculated between the independent input and output region 12 and 13, including is used to execute data fortune
The logic unit block array of calculation.Logic unit block can execute the Encryption Algorithm of SHA series or other data algorithms, packet
It includes but is not limited to SHA-256 algorithms.
In some embodiments, the layout structure further includes distinguishing the independent input and output region 12 and 13
The independent power supply circuit of power supply or centre position.Specifically, the power supply circuit or centre position are used to input in chip
It is powered with starlike connection type between the power supply side of output and the input and output region 12 and 13.It is defeated to independent input
Go out region 12 and 13 to be powered respectively different from the strong ESD protections of annular electric supply circuit in the prior art offer, only provide to chip
A degree of ESD protections, but the input and output region for eliminating chip the right and left and the circuit needed for annular electric supply
Area.For example, one PD of setting is that all I/O units supply in input and output region 12 or 13 in input and output region 12 or 13
Voltage on PAD is supplied to opposite end I/O units by electricity by conductor wire.
The layout structure for the dedicated IC chip that the embodiment of the present invention proposes eliminates prior art chips or so
The area in the input and output region on both sides also saves to provide strong ESD protections and forms the face needed for annular electric supply circuit
Product, and phase-locked loop is set in the input and output region of chip, is also not take up the region area for calculating kernel, the core of saving
Piece area is completely used for calculating kernel, to avoid waste chip from calculating the area of kernel.
Fig. 4 is the schematic diagram of the layout structure of dedicated IC chip according to another embodiment of the present invention.Such as Fig. 4 institutes
Show, the layout structure of dedicated IC chip described in the embodiment of the present invention includes：It is arranged in the input of the first edge of chip
Output area 12 and be arranged in chip the second edge opposite with the first edge input and output region 13.Two independences
Input and output region 12 and 13 respectively include input and output (I/O) unit 120.Input and output (I/O) unit 120 can be
One or more parallel arrangeds.
Wherein, in the input and output region 13 further include phase-locked loop (PLL) 130.In some embodiments, locking phase
Circuit 130 is set to one end of the combination of the input-output unit 120 of multiple parallel arrangeds.
Kernel area 11 is calculated between the independent input and output region 12 and 13, including is used to execute data fortune
The logic unit block array of calculation.Logic unit block can execute the Encryption Algorithm of SHA series or other data algorithms, packet
It includes but is not limited to SHA-256 algorithms.
In some embodiments, the layout structure further includes distinguishing the independent input and output region 12 and 13
The independent power supply circuit of power supply or centre position.Specifically, the power supply circuit or centre position are used to input in chip
It is powered with starlike connection type between the power supply side of output and the input and output region 12 and 13.It is defeated to independent input
Go out region 12 and 13 to be powered respectively different from the strong ESD protections of annular electric supply circuit in the prior art offer, only provide to chip
A degree of ESD protections, but the input and output region for eliminating chip the right and left and the circuit needed for annular electric supply
Area.
The layout structure for the dedicated IC chip interface module that the embodiment of the present invention proposes eliminates in the prior art
The area in the input and output region of chip the right and left also saves to provide strong ESD protections and forms annular electric supply circuit
Required area, and phase-locked loop is set in the input and output region of chip, is also not take up the region area for calculating kernel,
The chip area of saving is completely used for calculating kernel, to avoid waste chip from calculating the area of kernel.
Fig. 5 is the schematic diagram of the layout structure of dedicated IC chip according to another embodiment of the present invention.Such as Fig. 5 institutes
Show, the layout structure 10 of dedicated IC chip described in the embodiment of the present invention includes mainly：It is arranged in the first edge of chip
Input and output region SYS_GLU12 and be arranged in chip the second edge opposite with the first edge input and output
Region bottom IO 13.Two independent input and output regions 12 and 13 respectively include input and output (I/O) unit 120.It is defeated
It can be one or more parallel arrangeds to enter output (I/O) unit 120.
Wherein, in the input and output region 12 further include phase-locked loop (PLL) 130, control unit (top_ctrl)
140, input and output (I/O) unit 120_1 and signal behavior unit MUX160 and clock generating unit CLK_GCU150 is used
In generation clock.Phase-locked loop 130, MUX160 and CLK_GCU150 are only schematically shown in figure is set to input and output region
13, certain its can also be set in input and output region 12.Phase-locked loop (PLL) 130 is arranged in Far Left, CLK_
GCU150 is arranged in 130 lower section of phase-locked loop (PLL), and control unit (top_ctrl) 140 is located at 130 He of phase-locked loop (PLL)
Between input and output (I/O) unit 120_1, MUX160 is arranged in rightmost.The input and output region 13 includes input and output
(I/O) unit 120_2.Control unit 140 is used for (dhash block) transmission data of logic unit block 110 and order, and is connect
The data and operating result fed back by logic unit block 110.Control unit 140 further comprises feeding back logic unit block 110
Data carry out the function of further data processing.Here phase-locked loop (PLL) 130, control unit (top_ctrl) 140, defeated
The position for entering output (I/O) unit 120_1 and MUX160 and CLK_GCU150 is only exemplary explanation, other modes
It is protected by correlation.
The layout structure further comprises calculating kernel area 11, calculates kernel area 11 and be arranged in the input and output
Intermediate region between region 12 and 13.It includes the array being made of multiple logic unit blocks 110 to calculate kernel area 11.It patrols
Cell block 110 is collected using the structure of thin-and-long, the array being made of multiple logic unit blocks 110 includes symmetrical two
N rows are arranged in row, each column, and often one logic unit block 110 of row arrangement, i.e., entire array are disposed with 2N logic unit block in total.
Intermediate channel (middle_channel) 14 is provided between symmetrical array, intermediate channel 14 is located at control
Right over unit 140 processed, and positioned at the centre position for calculating kernel area 11.Intermediate channel 14 is defeated for arranging connection first
Enter output area 12 and one or more signal transmssion line 141 in the second input and output region 13.The signal transmssion line 141 can be with
By input and output (I/O) unit of input and output (I/O) the unit 120_2 in input and output region 13 and input and output region 12
120_1 is electrically connected, for data or the transmission of order.Certainly, the input and output (I/ in the second input and output region 13
O) unit 120_2 is connected by the signal transmssion line and control unit 140 of intermediate channel 14, and control unit 140 is defeated with second again
Enter the input-output unit 120_1 connections in output area.
In order to improve the utilization rate of intermediate channel 14, the area of chip is reduced, the intermediate channel can be arranged further
One or more technique aligned units TCD, electrostatic protection cell ESD and temperature induction unit TS (temperature
sensor).The number of the ESD is identical with each column setting N line numbers, and carry out electrostatic protection is provided for often row.
Input and output region 12 and 13 respectively includes one or more input and output (I/O) unit, only schematically shows in figure
It includes input and output (I/O) unit 120_1 to go out input and output region 12, and input and output region 13 includes that input and output (I/O) are single
First 120_2.In actual implementation, input and output (I/O) unit that region input and output (I/O) 12 and 13 is respectively arranged can be unlimited
2 output (I/O) units or more can be arranged in quantity shown in Fig. 5, such as input and output region 12.
Logic unit block 110 is the most crucial module for determining chip operational capability and power consumption for executing data operation.Often
A logic unit block receives the operational data that input and output (I/O) unit is sent, and executes individual operation, and export operation knot
The operation result of fruit, lower logical cell block is sent to input and output (I/O) unit by higher level's logic unit block.The present invention is real
The Encryption Algorithm of SHA series or other data algorithms, including but not limited to SHA- can be executed by applying logic unit block in example
256 algorithms.
In some embodiments, in the array that the logic unit block 110 forms, each column 50 rows of arrangement, i.e. N=50,
But the logic unit block number that each column is arranged in actual implementation can be according to the operational performance index allocation of chip, implementation without being limited thereto
Example.
Logic unit block in dedicated IC chip is configured to thin-and-long structure by the embodiment of the present invention, is conducive to logic
The smooth transmission of cell block internal arithmetic data, and by logic unit block array form two row multirows layout so that chip
It calculates kernel area to be realized as far as possible close to the layout of square, avoids the waste of chip area, and pass through each column multirow
Layout, realize the multiple logic unit blocks of each column, enhance the operational capability of chip.And it is improved by the way that intermediate channel is arranged
The utilization rate of chip.
Fig. 6 is the schematic diagram of the layout structure of dedicated IC chip according to another embodiment of the present invention.Such as Fig. 6 institutes
Show, on the basis of embodiment shown in Fig. 5, each logic unit block 110 further comprises that the first arithmetic element 201 and second is transported
Unit 202 is calculated, first arithmetic element, 201 and second arithmetic element 202 respectively executes once-through operation, the first operation list
A part of the result of 201 execution first time operation of member as the input data of the second arithmetic element 202, for second fortune
It calculates unit 202 and executes second of operation.
The first arithmetic element 201 and the second arithmetic element 202 can execute the encryption calculation of SHA series in the embodiment of the present invention
Method or other data algorithms, including but not limited to 256 algorithms of SHA-.
Fig. 7 is the structural schematic diagram of the logic unit block of dedicated IC chip according to an embodiment of the invention.The
One arithmetic element 201 and the second arithmetic element 202 are respectively included for executing the M level production lines needed for once-through operation
(PIPELINE) arithmetic element, M are the integer more than 1.Only with the first arithmetic element 201 and the second arithmetic element 202 in Fig. 3
It is illustrated for 64 level production line arithmetic element 301_1~301_64 including executing SHA-256 operations, it is specific real
The series of the M level production line arithmetic elements included by the first arithmetic element 201 and the second arithmetic element 202 is applied according to execution
Depending on algorithm.As shown in fig. 7, including computing module 401 and memory module 402, computing module per level production line arithmetic element 301
401 for executing the operation of this level production line, and memory module 402 preserves the operation result of this grade.
The 64 level production line arithmetic elements that first arithmetic element 201 and the second arithmetic element 202 include respectively join end to end,
1st level production line arithmetic element of the second arithmetic element 202 and the 64th level production line arithmetic element of the first arithmetic element 201 are first
Tail is connected, i.e. in the 64 level production line arithmetic elements that the first arithmetic element 201 and the second arithmetic element 202 include respectively, subordinate
The computing module 401 of pipeline operation unit is connect with the memory module 402 of higher level's pipeline operation unit, receives higher level's flowing water
Some of the operation result of line arithmetic element as this grade of operational data.1st level production line operation of the second arithmetic element 202
The computing module 401 of unit is connect with the memory module 402 of the 64th level production line arithmetic element of the first arithmetic element 201,
Receive the part of the operation result of the first arithmetic element 201 as the input data of the second arithmetic element 202.First operation list
It is arranged using end to end thin-and-long between member 201 and the pipeline operation units at different levels of the second arithmetic element 202, Ke Yishi
The now smooth transmission of SHA-256 operational datas twice.
First arithmetic element 201 receives the operational data that input and output (I/O) unit is sent, and executes first time SHA- successively
64 level production line operations of 256 operations, and export 256 operations of first time SHA- as a result, passing to the second arithmetic element 202
64 level production line operations of second of SHA-256 operation are continued to execute, and exports final operation result and returns to input and output
(I/O) unit.
In the embodiment of the present invention, since there are M level production line operations for each arithmetic element, all per level production line arithmetic element
Individually obtain clock signal, therefore the 1st level production line arithmetic element of each arithmetic element and M grades of streams in logic unit block
The clock signal of waterline arithmetic element disunity.In order to overcome the clock signal of pipeline operation units at different levels to be difficult to unification
The problem of, operation result data are sent to control unit by the afterbody pipeline operation unit of the second arithmetic element 202, and
The first arithmetic element 201 is not fed back to instead of, the remaining operation that do not complete is completed by control unit, control unit is completed surplus
After remaining operation, final operation result return is handled.
Here in conjunction with attached Figures 5 and 6 to the first arithmetic element 201_3 of the left side logic unit block 110_3 in attached drawing 7 and
Two arithmetic element 202_3 carry out operation principle explanation.I/O units are sent out by control unit to the first arithmetic element 201_3 first
Calculating task is sent, which can be sent to logic unit block 110_3 by logic unit block 110_1 and 110_2, also may be used
Calculating task is directly sent to logic unit block 110_3.The first arithmetic element 201_3 of logic unit block 110_3 receives
Calculating task, executes 64 level production line operations of first time SHA-256 operation, and operation result is sent to the second arithmetic element
202_3 executes 64 level production line operations of second of SHA-256 operation.Second arithmetic element 202_3 is by operation result by patrolling
It collects cell block 110_2 and 110_1 and is sent to the remaining operation that do not complete of control unit completion, control unit completes remaining operation
Afterwards, final operation result return is handled.Operation result directly can also be sent control unit by the second arithmetic element 202_3.
In some embodiments, the layout structure further includes distinguishing the independent input and output region 12 and 13
The independent power supply circuit of power supply or centre position.Specifically, the power supply circuit or centre position are used to input in chip
It is powered with starlike connection type between the power supply side of output and the input and output region 12 and 13.It is defeated to independent input
Go out region 12 and 13 to be powered respectively different from the strong ESD protections of annular electric supply circuit in the prior art offer, only provide to chip
A degree of ESD protections, but the input and output region for eliminating chip the right and left and the circuit needed for annular electric supply
Area.For example, one PD of setting is that all I/O units supply in input and output region 12 or 13 in input and output region 12 or 13
Voltage on silicon chip pin PAD is supplied to opposite end I/O units by electricity by conductor wire.
Fig. 8 and Fig. 9 is the schematic diagram of the layout structure of dedicated IC chip according to another embodiment of the present invention.Such as
Shown in Fig. 8, on the basis of embodiment shown in Fig. 5, the position of phase-locked loop (PLL) 130 is had adjusted, by phase-locked loop (PLL) 130
It is arranged in input and output region 13.As shown in figure 9, on the basis of embodiment shown in Fig. 5, phase-locked loop (PLL) 130 is had adjusted
With the position of CLK_GCU150, phase-locked loop (PLL) 130 and CLK_GCU150 are arranged in input and output region 13, and
Increase input and output (I/O) unit 120_3 in input and output region 12, input and output (I/O) unit 120_1 and 120_3 are located at
140 both sides of control unit.It can be seen that those skilled in the art can have adjusted phase-locked loop (PLL) according to actual conditions
130, control unit (top_ctrl) 140, input and output (I/O) unit 120_1 and MUX160 and CLK_GCU150 position
It sets.
The layout method for the dedicated IC chip that the embodiment of the present invention proposes eliminates prior art chips or so
The area in the input and output region on both sides also saves to provide strong ESD protections and forms the face needed for annular electric supply circuit
Product, the chip area of saving are completely used for calculating kernel, to avoid waste chip from calculating the area of kernel.
The layout method for the dedicated IC chip that the embodiment of the present invention proposes eliminates prior art chips or so
The area in the input and output region on both sides also saves to provide strong ESD protections and forms the face needed for annular electric supply circuit
Product, and phase-locked loop is set in the input and output region of chip, is also not take up the region area for calculating kernel, the core of saving
Piece area is completely used for calculating kernel, to avoid waste chip from calculating the area of kernel.It is arranged in chip setting intermediate channel
The signal transmssion line in the input and output region of peer end of the connection, technique aligned units TCD, electrostatic protection cell ESD and temperature sensing
Unit TS further reduces the area of chip, improves the performance of chip, reduces its power.
Particular embodiments described above has carried out further in detail the purpose of the present invention, technical solution and advantageous effect
It describes in detail bright, it should be understood that the above is only a specific embodiment of the present invention, is not intended to restrict the invention, it is all
Within the spirit and principles in the present invention, any modification, equivalent substitution, improvement and etc. done should be included in the guarantor of the present invention
Within the scope of shield.
Claims (21)
1. a kind of layout structure of dedicated IC chip, which is characterized in that including calculating kernel area and I/O area
Domain, it is described to calculate the array that kernel area includes multiple logic unit block compositions, the array of the multiple logic unit block composition
Including symmetrical two row, multirow is arranged in each column, often one logic unit block (dhash block) of row arrangement；The input
Output area include the first edge for being arranged in the dedicated IC chip the first input and output region (SYS_GLU) and
It is arranged in the second input and output region of the second edge opposite with the first edge of the dedicated IC chip
(bottom IO), first input and output region and the second input and output region respectively include at least one parallel arranged
Input-output unit (IO)；Intermediate channel (middle_channel) is provided between symmetrical array, intermediate channel is used
Signal transmssion line in arrangement connection the first input and output region and the second input and output region.
2. the layout structure of dedicated IC chip according to claim 1, which is characterized in that the intermediate channel can
Further to arrange one or more technique aligned units TCD, multiple electrostatic protection cell ESDs and temperature induction unit TS.
3. the layout structure of dedicated IC chip according to claim 1 or 2, which is characterized in that the first input is defeated
Going out region can further arrange that control unit (top_ctrl), control unit (top_ctrl) are controlled for chip logic.
4. the layout structure of dedicated IC chip according to claim 3, which is characterized in that first input is defeated
The input-output unit gone out in region or the second input and output region is connected by control unit, carries out data or order transmission.
5. the layout structure of dedicated IC chip according to claim 4, which is characterized in that the second I/O area
Input-output unit in domain is connected by the signal transmssion line of intermediate channel with control unit, and control unit is inputted with second again
Input-output unit connection in output area.
6. the layout structure of dedicated IC chip according to claim 1 or 2, which is characterized in that described first is defeated
Enter output area or the second input and output region further comprises that phase-locked loop circuit PLL, signal selector MUX and clock are generated
It is one or more in unit CLK_GCU.
7. the layout structure of dedicated IC chip according to claim 1 or 2, which is characterized in that wherein logic list
First block is in the structure of thin-and-long.
8. the layout structure of dedicated IC chip according to claim 1 or 2, which is characterized in that described first is defeated
Enter output area and the second input and output region respectively includes the input-output unit of multiple parallel arrangeds.
9. the layout structure of dedicated IC chip according to claim 6, which is characterized in that the phase-locked loop
PLL, MUX or CLK_GCU are set to multiple parallel arrangeds in first input and output region or the second input and output region
One end of the combination of input-output unit.
10. the layout structure of dedicated IC chip according to claim 1 or 2, which is characterized in that the layout knot
Structure further include the independent power supply circuit powered respectively to first input and output region and the second input and output region or in
Between position.
11. the layout structure of dedicated IC chip according to claim 10, which is characterized in that the power supply circuit
Or centre position is used for the power supply side in chip input and output and first input and output region and the second input and output
It is powered with starlike connection type between region.
12. the layout structure of dedicated IC chip according to claim 1 or 2, which is characterized in that the logic list
First block includes the first arithmetic element and the second arithmetic element, and first arithmetic element is for executing first time operation, and described the
Two arithmetic elements are for executing second of operation.
13. the layout structure of dedicated IC chip according to claim 12, which is characterized in that first operation
Unit is connected to second arithmetic element, wherein first arithmetic element executes the result of first time operation for described the
Two arithmetic elements execute second of operation.
14. the layout structure of dedicated IC chip according to claim 13, which is characterized in that first operation
Unit and the second arithmetic element respectively include M level production line arithmetic elements, and the M level production lines arithmetic element is used and joined end to end
Thin-and-long arrangement, and the M level production lines of the 1st level production line arithmetic element of the second arithmetic element and the first arithmetic element are transported
It calculates unit to join end to end, M is the integer more than 1.
15. the layout structure of dedicated IC chip according to claim 14, which is characterized in that the M grades of flowing water
Line arithmetic element respectively includes computing module and memory module, and the computing module is described for executing pipeline operations at different levels
Memory module is for preserving operation results at different levels.
16. the layout structure of dedicated IC chip according to claim 15, which is characterized in that the M grades of flowing water
The computing module of subordinate's pipeline operation unit is connected with the memory module of higher level's pipeline operation unit in line arithmetic element.
17. the layout structure of dedicated IC chip according to claim 16, which is characterized in that first operation
Unit and the second arithmetic element are for executing SHA-256 operations.
18. the layout structure of dedicated IC chip according to claim 17, which is characterized in that the M grades of flowing water
Line arithmetic element includes 64 level production line arithmetic elements.
19. the layout structure of dedicated IC chip according to claim 18, which is characterized in that the logic unit
Block receives the operational data that the input-output unit is sent, and executes data operation, and export and transport to the input-output unit
Calculate result.
20. the layout structure of dedicated IC chip according to claim 18, which is characterized in that the logic unit
Block executes data operation, and operation result is sent to after control unit is further processed to the input-output unit and exports operation
As a result.
21. a kind of computer, which is characterized in that include the cloth of claim 1-20 any one of them dedicated IC chips
Office's structure.
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| Application Number | Priority Date | Filing Date | Title |
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| CN201810372342.4A CN108536989A (en) | 2018-04-24 | 2018-04-24 | The layout structure and method of dedicated IC chip |
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| Application Number | Priority Date | Filing Date | Title |
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| CN201810372342.4A CN108536989A (en) | 2018-04-24 | 2018-04-24 | The layout structure and method of dedicated IC chip |
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ID=63478290
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN113675187A (en) * | 2021-07-27 | 2021-11-19 | 广芯微电子（广州）股份有限公司 | Chip for seamless splicing of operation units |
| CN113743047A (en) * | 2021-08-19 | 2021-12-03 | 广芯微电子（广州）股份有限公司 | Chip |
-
2018
- 2018-04-24 CN CN201810372342.4A patent/CN108536989A/en not_active Withdrawn
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN113675187A (en) * | 2021-07-27 | 2021-11-19 | 广芯微电子（广州）股份有限公司 | Chip for seamless splicing of operation units |
| CN113675187B (en) * | 2021-07-27 | 2022-09-06 | 广芯微电子（广州）股份有限公司 | Chip for seamless splicing of operation units |
| CN113743047A (en) * | 2021-08-19 | 2021-12-03 | 广芯微电子（广州）股份有限公司 | Chip |
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