CN208093585U - Light emitting diode - Google Patents

Light emitting diode Download PDF

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Publication number
CN208093585U
CN208093585U CN201820469094.0U CN201820469094U CN208093585U CN 208093585 U CN208093585 U CN 208093585U CN 201820469094 U CN201820469094 U CN 201820469094U CN 208093585 U CN208093585 U CN 208093585U
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layer
electrode
light emitting
insulating
insulating layer
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CN201820469094.0U
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王�锋
王庆
陈征
洪灵愿
许圣贤
林素慧
彭康伟
张家宏
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Quanzhou Sanan Semiconductor Technology Co Ltd
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Xiamen Sanan Optoelectronics Technology Co Ltd
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Abstract

The utility model discloses a kind of light emitting diodes.In some embodiments, the light emitting diode, including:Light emitting epitaxial layer includes the first semiconductor layer, luminescent layer and the second semiconductor layer successively from top to bottom;First electrode is formed in first semiconductor layer;Second electrode is formed in second semiconductor layer;It is characterized in that:The first electrode, second electrode are respectively arranged below with the first insulating layer, second insulating layer, and the thickness of first insulating layer is more than the thickness of the second insulating layer.

Description

Light emitting diode
Technical field
The utility model is related to semiconductor elements, more particularly, to a kind of light emitting diode.
Background technology
Since light emitting diode has the advantages that long lifespan, small, high vibration strength, fever degree are small and power consumption is low etc., Light emitting diode has been widely used in the indicator light or light source of household appliances and various instrument.
The gallium nitride based LED chip fabrication technique of early stage is usually by mesa etch(MESA), make transparency conducting layer(Such as ITO), make electrode and make four technique of protective layer composition, the light-emitting diode chip for backlight unit formed is as shown in Figure 1, it is general Including substrate 101, N-type layer 111, luminescent layer 112, P-type layer 113, transparency conducting layer 120, P electrode 141 (pad 143 and extension Portion 144), N electrode 142 and protective layer 130.In gallium nitride based LED, P-GaN layers are relatively low due to its carrier mobility, it will usually In electrode(PAD)Cause certain electric current congestion in bottom.Therefore, typically now it can increase current blocking in the bottom of P-type electrode Layer 150 increases the current spread of transparency conducting layer, as shown in Figure 2 for inhibiting crossing for electric current to inject.The chip fabrication technique Typically at least include:Mesa etch(MESA), make current barrier layer, make current extending(Such as ITO), make electrode and Make five technique of protective layer.
Utility model content
The utility model provides a kind of light emitting diode, is set below welding disk/extension of the first, second electrode The insulating layer for setting different-thickness effectively improves the light extraction efficiency and reliability of light emitting diode.
According to the first aspect of the invention, light emitting diode, including:Light emitting epitaxial layer includes the successively from top to bottom Semi-conductor layer, luminescent layer and the second semiconductor layer;First electrode, is formed in first semiconductor layer, and with it is described First semiconductor layer is electrically connected;Second electrode, is formed in second semiconductor layer, and is led with described the second half Body layer is electrically connected;It is characterized in that:The first electrode, second electrode are respectively arranged below with the first insulating layer, second Insulating layer, it is characterised in that the thickness of first insulating layer is more than the thickness of the second insulating layer.
According to the second aspect of the invention, light emitting diode, including:Light emitting epitaxial layer includes the successively from top to bottom Semi-conductor layer, luminescent layer and the second semiconductor layer;First electrode, is formed in first semiconductor layer, and with it is described First semiconductor layer is electrically connected;Second electrode, is formed in second semiconductor layer, and is led with described the second half Body layer is electrically connected;It is characterized in that:The first electrode includes the first welding disk and the first extension, second electricity Pole includes the second welding disk and the second extension, and first welding disk, the second welding disk are respectively arranged below with the first insulation Layer, second insulating layer, it is characterised in that the thickness of first insulating layer is more than the thickness of the second insulating layer.
Preferably, first insulating layer includes at least the first insulating sublayer layer and the second insulating sublayer layer.
Preferably, the second insulating sublayer layer is located on the first insulating sublayer layer, and the second insulating sublayer layer packet Wrap up in the side wall of the first insulating sublayer layer.
Preferably, transparency conducting layer is equipped between first insulating layer and first semiconductor layer.
Preferably, first insulating layer wraps up the side wall of the transparency conducting layer.
It is preferably located at the first insulating layer below the first electrode and is equipped with an at least through-hole structure, for described the One electrode is electrically connected with transparency conducting layer realization.
It is preferably located at second insulating layer below the second electrode and is equipped with an at least through-hole structure, for described the Two electrodes are electrically connected with second semiconductor layer realization.
Preferably, third insulating layer is equipped between first extension and first semiconductor layer, described second expands The 4th insulating layer is equipped between exhibition portion and second semiconductor layer.
Preferably, the thickness of the third insulating layer is more than the thickness of the second insulating layer.
Preferably, the thickness of the 4th insulating layer is more than the thickness of the second insulating layer.
Preferably, the upper surface of the first extension of the first electrode is in high and low undulated, and the of the second electrode The upper surface of two extensions is in high and low undulated.
The utility model at least has the advantages that:
(1)The insulating layer below the pad of first electrode, second electrode is remained, while as current barrier layer, being used for Improve current spread;
(2)By the protective effect of the first thicker insulating layer, such as the first insulating layer include at least the first insulating sublayer layer and Second insulating sublayer layer avoids transparency conducting layer from inside contracting etching process and causes overetch phenomenon, to improve manufacturing reliability;
(3)By first electrode, second electrode extension below insulating layer thicken, i.e., thickness is more than second electrode Thickness of insulating layer below pad, can improving extraction efficiency;
(4)The pad of first electrode is largely contacted with insulating layer, and the usually adhesive layer material of first electrode(Usually Cr, Ti, Ni etc.)It is preferable with the adhesion of insulating layer, it is opposite with the adhesion of transparency conducting layer contact portion weaker, and this connects The height of contact portion point is relatively low, is conducive to the routing for improving electrode pad, improves the stability of electrode pad;
(5)First electrode, second electrode extension be distributed with high and low fluctuating, it is possible to reduce electrode and other objects Contact area, the damage for effectively reducing the pour mask of LED later stages, the electrode extension in the process such as transporting and shift reduces simultaneously Electrode extension it is dirty.
Other features and advantages of the utility model will illustrate in the following description, also, partly from specification In become apparent, or understood by implementing the utility model.The purpose of this utility model and other advantages can pass through Specifically noted structure is realized and is obtained in specification, claims and attached drawing.
Although describing the utility model, this field skill hereinafter in connection with some exemplary implementations and application method Art personnel should understand that, it is no intended to limit the invention to these embodiments.It is on the contrary, it is intended to which that covering is included in appended All substitutes, amendment and equivalent in the spirit and scope of the utility model as defined in the claims.
Description of the drawings
Attached drawing is used to provide a further understanding of the present invention, and a part for constitution instruction, with this practicality New embodiment for explaining the utility model, does not constitute limitations of the present invention together.In addition, attached drawing data are to retouch Summary is stated, is not drawn to scale.
Fig. 1 is the structural schematic diagram of existing light emitting diode.
Fig. 2 is the structural schematic diagram of another existing light emitting diode.
Fig. 3 and 4 is the structural schematic diagram of the light emitting diode of the utility model embodiment 1, and Fig. 4 is Fig. 3 along the directions A-A Sectional view.
Fig. 5 ~ Fig. 8 is the structural schematic diagram of the light emitting diode of the utility model embodiment 2, and Fig. 6 is Fig. 5 along the directions A-A Sectional view, Fig. 8 be Fig. 7 along the directions B-B sectional view.
Specific implementation mode
The embodiment of the utility model is described in detail below with reference to accompanying drawings and embodiments, whereby to the utility model How applied technology method solves technical problem, and the realization process for reaching technique effect can fully understand and implement. If it should be noted that do not constitute conflict, each feature in each embodiment and each embodiment in the utility model It can be combined with each other, be formed by technical solution and both be within the protection scope of the present invention.
It should be appreciated that purpose of the term used in the utility model merely for description specific implementation mode, rather than purport In limitation the utility model.As used in the utility model, singulative "a", "an" and "the" is also intended to including multiple Number form formula, in addition to context clearly illustrates.It is to be further understood that term "comprising", " packet ought be used in the present invention Include ", " containing " when, for show statement feature, entirety, step, operation, the presence of element, and/or packaging part, without arrange Except other one or more features, entirety, step, operation, the presence or increase of element, packaging part, and/or combination thereof.
Unless defined otherwise, all terms used in the utility model(Including technical terms and scientific terms)Have Meaning identical with the meaning that the utility model those of ordinary skill in the art are generally understood.It is to be further understood that this Term used in utility model should be understood have with these terms in the context and related field of this specification Meaning consistent meaning, and should not be understood with the meaning of idealization or too formal, except clear such in the utility model Except definition.
Embodiment 1
Referring to Fig. 3 and Fig. 4, wherein Fig. 3 show that the light emitting diode of the utility model first preferred embodiment is bowed View, Fig. 4 are the sectional views splitted along the directions A-A along Fig. 3.The light emitting diode includes:Substrate 201, buffer layer 211, N-type Layer 212, luminescent layer 213, P-type layer 214, transparency conducting layer 221, the first insulating sublayer layer 231, second the 232, first electricity of insulating sublayer layer Pole(P electrode)241 and second electrode(N electrode)242.Wherein first electrode 241 includes pad and extension, second electrode 242 Including pad and extension, depending on chip size size, which can only include pad, and be not provided with extension.
Specifically, it includes but not limited to sapphire, aluminium nitride, gallium nitride, silicon, silicon carbide, surface that substrate 201, which is chosen, Structure can be planar structure or patterning graph structure;Light emitting epitaxial layer may include buffer layer, N-type layer, luminescent layer and P-type layer, Wherein buffer layer 211 can select AlN or AlGaN layer, be formed in Sapphire Substrate 201;N-type layer 212 is formed in buffering On layer 211;Luminescent layer 213 is formed in N-type layer 212;P-type layer 214 is formed on luminescent layer 213;Through light shield etching etc. Technique, from top to bottom from part P-type layer 214, dry etching to exposed portion N-type layer 212 exposes N table tops;In P-type layer 214 On, transparency conducting layer 221 is formed, transparency conducting layer can select tin indium oxide(ITO)Or zinc oxide(ZnO)Or cadmium tin (CTO)Or indium oxide(InO)Or indium(In)Doping zinc-oxide(ZnO)Or aluminium(Al)Doping zinc-oxide(ZnO)Or gallium(Ga)Doping Zinc oxide(ZnO)Or one of aforementioned arbitrary combination, the preferred ITO of the present embodiment is located at P as transparency conducting layer, the transparency conducting layer On type layer table top, and through wet etching process transparency conducting layer 221 is inside contracted, to ensure at MESA steps without electrically conducting transparent Layer residual eliminates electric leakage hidden danger.The first insulating layer is formed on transparency conducting layer 221, and second insulating layer is formed on N table tops, It is preferred that the thickness of the first insulating layer is more than the thickness of second insulating layer.First insulating layer of the present embodiment includes the first insulating sublayer layer 231 and the second insulating sublayer layer 232, second insulating layer only include the second insulating sublayer layer 232, preferably the second insulating sublayer layer is more than first Insulating sublayer layer thickness, the first insulating sublayer layer thickness is no more than 10nm, to ensure that it is anti-reflection that the first, second insulating sublayer layer overall thickness meets Under the premise of film required thickness, the thickness of the second insulating sublayer layer on N table tops will not significantly deviate thickness needed for anti-reflection film Degree, and influence the extraction efficiency of light.Or under the premise of ensuring that the second insulating sublayer layer thickness meets anti-reflection film required thickness, first The thickness of insulating layer will not significantly deviate anti-reflection film required thickness, and influence the extraction efficiency of light.Further, it is preferable to first Insulating sublayer layer 231 is located on transparency conducting layer 221, but does not wrap up transparency conducting layer 221, so can be used for protecting transparent lead Electric layer will not be etched during wet etching process it is excessive, and the second insulating sublayer layer 232 be located at the first insulating sublayer layer 231 it On, and wrap up the side wall of the first insulating sublayer layer 231, transparency conducting layer 221 and light emitting epitaxial layer, i.e., substantially cover entire device Phenomena such as surface of part can so protect transparency conducting layer and MESA steps, it is avoided to cause to leak electricity because of contamination. First insulating layer is equipped with an at least through-hole structure 233, is electrically connected with the realization of transparency conducting layer 221 for follow-up P electrode 241, the Two insulating layers are equipped with an at least through-hole structure 233, are electrically connected with the realization of the N-type layer 212 of N table tops for follow-up N electrode 242.P electricity Pole 241 and N electrode 242 are formed on insulating layer, and wherein the welding disk of P electrode passes through through-hole structure 233 and transparency conducting layer 221 Contact is not provided with insulating layer below the extension of P electrode, and the welding disk of N electrode is located on table top, passes through through-hole structure 233 contact with N-type layer 212, and insulating layer is not provided with below the extension of N electrode.Due to first electrode(P electrode)The big portion of pad Divide and is contacted with insulating layer, and the usually adhesive layer material of P electrode(Usually Cr, Ti, Ni etc.)It is preferable with the adhesion of insulating layer, It is opposite with the adhesion of transparency conducting layer contact portion weaker, and the height of the contact portion is relatively low, is conducive to improve electrode The routing of pad improves the stability of electrode pad.
In the present embodiment, the first, second insulating layer is in block distribution, and material can select SiO2、Si3N4、Al2O3、 TiO2Deng selecting SiO in the present embodiment2.In light emitting diode construction described in the present embodiment, the first, second insulating layer is on the one hand LED surface is protected, current barrier layer is on the other hand used as, for inhibiting the electric current of base part to cross injection, is increased saturating The current spread of bright conductive layer considers the requirement for taking into account the two, and the second insulating sublayer layer thickness d is preferably λ/4n × (2k-1), Middle λ is the emission wavelength of institute's luminescent layer, and n is the refractive index of protective layer, and the preferable value of the natural number that k is 1 or more, k is 2 ~ 3, Corresponding thickness is that 150nm ~ 500nm is preferred.First insulating sublayer layer thickness d is preferably λ/4n × (2k), and the preferable value of k is 1 ~ 2, corresponding thickness is that 50nm ~ 500nm is preferred.First insulating sublayer layer thickness d can also be preferably less than 10nm, to ensure first Insulating layer or the second insulating sublayer layer thickness will not significantly deviate anti-reflection film required thickness, i.e. λ/4n × (2k-1).Work as insulating layer The too small when ratio of thickness be less favorable for playing current barrier layer and protective effect, when thickness is excessive, absorb can be additional for material itself Increase light loss.It is 1.5 hereinafter, its material that first, second insulating layer, which can select low-refraction insulating materials, preferred index, It can be the same, can also be different.In addition, the first insulating layer can comprise more than 2 straton insulating layers, can also select With the insulating layer material of multipair different refractivity size, that is, form Bragg reflecting layer(DBR), the extraction of side light is promoted, into And increase light emitting anger.
It, can be with by the mask plate effect of the first insulating layer in the manufacture craft of the present embodiment light emitting diode construction Make MESA and transparency conducting layer simultaneously(ITO)Light shield, and ensure that ITO does not seriously cross erosion and influences brightness, to save light The cost of cover mask plate.
Embodiment 2
The structural schematic diagram of another light emitting diode of Fig. 5 ~ Fig. 8 displays, Fig. 6 are Fig. 5 along the sectional view in the directions A-A, Fig. 8 It is Fig. 7 along the sectional view in the directions B-B.It is different from embodiment 1, the extension 243 of P electrode 241 is upper described in the present embodiment Surface is in high and low undulated, and the upper surface of the extension 244 of the N electrode 242 is in high and low undulated.Specifically, it shines The area that N table tops expose in diode structure is reduced, that is, remains several light emitting epitaxial layer column structure, and the phase Adjacent light emitting epitaxial layer column structure is separated by a series of through-hole structures 235.In addition, in the present embodiment, being located at outside shining Prolong the extension 244 of the N electrode on layer column structure, there is the second insulating sublayer layer 232, the first insulating sublayer layer successively below 231, transparency conducting layer 221, P-type layer 214, and the extension 244 of the N electrode on the through-hole structure 235 is directly and N-type layer 212 form contact.
The present embodiment is different from embodiment 1:First extension of the P electrode of light emitting diode construction, N electrode It is equipped with insulation layer structure below second extension.Specifically, the 243 lower section setting third of extension of wherein P electrode insulate The 4th insulating layer is arranged in 244 lower section of extension of layer, N electrode, and the third insulating layer below the extension of P electrode passes through several Through-hole structure 234 separates, and the 4th insulating layer below the extension of N electrode is separated by several through-hole structures 235, and preferably The thickness of three insulating layers, the 4th insulating layer thickness be all higher than the thickness of second insulating layer, can so be further reduced P, N electrode Electric current injection below extension, while 244 height of part extension of N electrode being raised, can effectively it be subtracted using refractive power effect The metal of few electrode extension is in the light area, to promote the efficiency of light extraction of LED.
In the present embodiment, it is located at many insulating protective layers of the base part of light emitting diode, on the one hand protects and shine Diode is not damaged, and on the other hand can increase again for inhibiting the electric current of base part to cross injection directly as current barrier layer Add the current spread of transparency conducting layer;First electrode(P electrode)Extension be located on insulating protective layer, and by through-hole Structure is contacted with transparency conducting layer so that the extension of first electrode forms the upper and lower step for playing shape, increases light at extension The angle of outgoing promotes light extraction efficiency, can be with simultaneously because there is high step and low step to rise and fall distribution for the extension of electrode The contact area of electrode and other objects is reduced, the pour mask of LED later stages is effectively reduced, the electrode extension in the process such as transports and shift The damage in portion, while reducing the dirty of electrode extension.
It should be noted that embodiment of above is merely to illustrate the utility model, and it is new to be not intended to limit this practicality Type, those skilled in the art can do the utility model in the case where not departing from the spirit and scope of the utility model Go out various modifications and variation, therefore all equivalent technical solutions also belong to the scope of the utility model, the utility model it is special Sharp protection domain should regard Claims scope and limit.

Claims (12)

1. light emitting diode, including:
Light emitting epitaxial layer includes the first semiconductor layer, luminescent layer and the second semiconductor layer successively from top to bottom;
First electrode is formed in first semiconductor layer;
Second electrode is formed in second semiconductor layer;
It is characterized in that:The first electrode, second electrode are respectively arranged below with the first insulating layer, second insulating layer, and described The thickness of one insulating layer is more than the thickness of the second insulating layer.
2. light emitting diode, including:
Light emitting epitaxial layer includes the first semiconductor layer, luminescent layer and the second semiconductor layer successively from top to bottom;
First electrode is formed in first semiconductor layer;
Second electrode is formed in second semiconductor layer;
It is characterized in that:The first electrode includes the first welding disk and the first extension, and the second electrode includes the second weldering Pan portion and the second extension, first welding disk, the second welding disk be respectively arranged below with the first insulating layer, second insulation Layer, it is characterised in that the thickness of first insulating layer is more than the thickness of the second insulating layer.
3. light emitting diode according to claim 1 or 2, it is characterised in that:First insulating layer includes at least first Insulating sublayer layer and the second insulating sublayer layer.
4. light emitting diode according to claim 3, it is characterised in that:The second insulating sublayer layer is located at first son On insulating layer, and the second insulating sublayer layer wraps up the side wall of the first insulating sublayer layer.
5. light emitting diode according to claim 1 or 2, it is characterised in that:First insulating layer and described the first half Transparency conducting layer is equipped between conductor layer.
6. light emitting diode according to claim 5, it is characterised in that:First insulating layer wraps up the electrically conducting transparent The side wall of layer.
7. light emitting diode according to claim 5, it is characterised in that:The first insulation below the first electrode Layer is equipped with an at least through-hole structure, is electrically connected with transparency conducting layer realization for the first electrode.
8. light emitting diode according to claim 1 or 2, it is characterised in that:Second below the second electrode Insulating layer is equipped with an at least through-hole structure, is electrically connected with second semiconductor layer realization for the second electrode.
9. light emitting diode according to claim 2, it is characterised in that:First extension and first semiconductor It is equipped with third insulating layer between layer, the 4th insulating layer is equipped between second extension and second semiconductor layer.
10. light emitting diode according to claim 9, it is characterised in that:The thickness of the third insulating layer is more than described The thickness of second insulating layer.
11. light emitting diode according to claim 9, it is characterised in that:The thickness of 4th insulating layer is more than described The thickness of second insulating layer.
12. light emitting diode according to claim 2, it is characterised in that:First extension of the first electrode it is upper Surface is in high and low undulated, and the upper surface of the second extension of the second electrode is in high and low undulated.
CN201820469094.0U 2018-03-30 2018-03-30 Light emitting diode Active CN208093585U (en)

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Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN112385052A (en) * 2019-10-23 2021-02-19 安徽三安光电有限公司 Light emitting diode and manufacturing method thereof
CN114050209A (en) * 2021-10-26 2022-02-15 厦门三安光电有限公司 Light emitting diode
CN116779741A (en) * 2023-07-18 2023-09-19 江西兆驰半导体有限公司 LED chip for improving luminous brightness and preparation method thereof

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN112385052A (en) * 2019-10-23 2021-02-19 安徽三安光电有限公司 Light emitting diode and manufacturing method thereof
CN114050209A (en) * 2021-10-26 2022-02-15 厦门三安光电有限公司 Light emitting diode
CN114050209B (en) * 2021-10-26 2024-01-09 厦门三安光电有限公司 Light emitting diode
CN116779741A (en) * 2023-07-18 2023-09-19 江西兆驰半导体有限公司 LED chip for improving luminous brightness and preparation method thereof

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Effective date of registration: 20231027

Address after: Yuanqian village, Shijing Town, Nan'an City, Quanzhou City, Fujian Province

Patentee after: QUANZHOU SAN'AN SEMICONDUCTOR TECHNOLOGY Co.,Ltd.

Address before: 361009 no.1721-1725, Luling Road, Siming District, Xiamen City, Fujian Province

Patentee before: XIAMEN SANAN OPTOELECTRONICS TECHNOLOGY Co.,Ltd.