CN207896091U - array substrate and display device - Google Patents
array substrate and display device Download PDFInfo
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- CN207896091U CN207896091U CN201820395453.2U CN201820395453U CN207896091U CN 207896091 U CN207896091 U CN 207896091U CN 201820395453 U CN201820395453 U CN 201820395453U CN 207896091 U CN207896091 U CN 207896091U
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Abstract
The utility model discloses a kind of array substrate and display devices, belong to display technology field.The array substrate includes：Underlay substrate, and a plurality of signal wire that is arranged on the underlay substrate；In two adjacent signal wires, the first signal wire is connect with the first connection electrode, and second signal line is connect with the second connection electrode, and first connection electrode insulate with second connection electrode；It is additionally provided with conductive electrode on the underlay substrate, the conductive electrode insulate with each connection electrode and per signal line, and orthographic projection of the conductive electrode on the underlay substrate is Chong Die with the orthographic projection of first connection electrode and second connection electrode on the underlay substrate respectively.Array substrate provided by the utility model has antistatic protection function, and it is not necessary that electrostatic protection device is arranged, structure is relatively simple, is conducive to the realization of narrow frame display panel.
Description
Technical field
The utility model is related to display technology field, more particularly to a kind of array substrate and display device.
Background technology
In array substrate manufacturing process, since the techniques such as plasma-deposited, film layer etching and friction easy to produce electrostatic,
Electrostatic breakdown and electrostatic damage may occur for the signal wire therefore formed in array substrate, cause array substrate bad.In order to protect
The normal work of various signal wires is demonstrate,proved, the electrostatic protection device being connect with signal wire can be set in array substrate.
Electrostatic protection device in the related technology generally comprise multiple transistors and at least one electrostatic defending line (such as
Public electrode wire or short-circuited conducting sleeve etc.), each transistor can be connect with a signal line and the electrostatic defending line respectively, will
The electrostatic generated on signal wire is discharged in time to the electrostatic defending line.
But electrostatic protection device the space occupied in the related technology is larger, is unfavorable for the reality of narrow frame display panel
It is existing.
Utility model content
The utility model provides a kind of array substrate and display device, and the array substrate that can be solved in the related technology needs
The problem of electrostatic protection device is set, the realization of narrow frame display panel is unfavorable for.Technical solution is as follows：
On the one hand, a kind of array substrate is provided, the array substrate includes：Underlay substrate, and be arranged in the lining
A plurality of signal wire on substrate；
In two adjacent signal wires, the first signal wire is connect with the first connection electrode, and second signal line is connect with second
Electrode connects, and first connection electrode insulate with second connection electrode；
It is additionally provided with conductive electrode on the underlay substrate, insulation is provided between the conductive electrode and the signal wire
Layer, and the conductive electrode insulate with each connection electrode, orthographic projection of the conductive electrode on the underlay substrate point
It is not Chong Die with the orthographic projection of first connection electrode and second connection electrode on the underlay substrate.
Optionally, in a plurality of signal wire, it is respectively connected with connection electrode per signal line, the conductive electrode is in substrate
Orthographic projection on substrate is Chong Die with orthographic projection of each connection electrode on the underlay substrate respectively.
Optionally, first signal wire and first connection electrode are the integral structure of same layer setting, and described the
One connection electrode is located at first signal wire close to the side of the binary signal line；
The second signal line and the integral structure that second connection electrode is same layer setting, and the second connection electricity
Pole is located at the second signal line close to the side of a signal wire.
Optionally, a plurality of signal wire is grid line, and thin film transistor (TFT) TFT is additionally provided on the underlay substrate；
The active layer, source-drain electrode metal layer or shading metal layer same layer of the conductive electrode and the TFT are arranged, and institute
The conductive structure that conductive electrode is arranged with same layer is stated to be made of same material.
Optionally, the array substrate further includes：The multiple data lines arranged in a crossed manner with a plurality of grid line；
In a plurality of grid line, connection electrode is respectively connected with the grid lines that connect of driving TFT, and each grid line is connected
Connection electrode is respectively positioned between adjacent the first data line and the second data line；
Wherein, first data line is connect with an illusory TFT of row, and second data line is connect with a row driving TFT,
Other each column data lines of second data line relative to first data line in the array substrate, the driving
TFT is connect with pixel electrode, the illusory TFT unconnected pixels electrode.
Optionally, adjacent first data line and the second data line surround the illusory picture of a row with a plurality of grid line
Element；
The first connection electrode and the second connection electrode that are connected per adjacent two grid lines are located at the picture of a dummy pixel
In plain region；
The conductive electrode includes multiple spaced electrode blocks, and each electrode block is located at the pixel of a dummy pixel
In region, and the connection electrode being arranged in orthographic projection of the electrode block on the underlay substrate and the pixel region is in institute
State the orthographic projection overlapping on underlay substrate.
Optionally, each electrode block insulate with other conductive structures in array substrate；
Alternatively, the active layer of the illusory TFT of each dummy pixel is integrated knot with the electrode block being arranged in its pixel region
Structure.
Optionally, it is additionally provided with third data line between first data line and second data line, described first
Side of the data line far from second data line is additionally provided with the 4th data line；
The third data line and the 4th data line are connect with an illusory TFT of row respectively.
Optionally, the conductive electrode is strip shaped electric poles, orthographic projection of the strip shaped electric poles on underlay substrate with it is each
Orthographic projection of the connection electrode on the underlay substrate is overlapped.
Optionally, a plurality of signal wire is data line, and thin film transistor (TFT) is additionally provided on the underlay substrate；
The gate metal layer same layer of the conductive electrode and the thin film transistor (TFT) is arranged, and the conductive electrode use with
The identical material of the gate metal layer is made.
Optionally, first signal wire is connect by the first contact via with first connection electrode, and described second
Signal wire is connect by the second contact via with second connection electrode.
Optionally, each connection electrode is strip shaped electric poles, and the extending direction of the strip shaped electric poles connects with it
The extending direction of the signal wire connect is vertical.
Optionally, the input terminal per signal line or output end are connected with connection electrode.
Optionally, first connection electrode is arranged with the second connection electrode same layer；
The width range in the gap between first connection electrode and second connection electrode is 2 microns to 20 micro-
Rice；
The width range of the conductive electrode is 10 microns to 90 microns.
On the other hand, a kind of display device is provided, the display device includes：
Such as the array substrate provided in terms of above-mentioned.
The advantageous effect that technical solution provided by the utility model is brought is：
The utility model embodiment provides a kind of array substrate and display device, two adjacent letters in the array substrate
It in number line, is connect with a connection electrode per signal line, and two connection electrodes and conductive electrode are on underlay substrate
Orthographic projection is overlapped.Therefore when generating electrostatic on either signal line, the connection electrode which is connected can be with the conduction
Electrode constitutes capacitance, which has good antistatic protection function.Also, when the voltage of the signal wire due to accumulation of static electricity and
When higher, conductive path is formed between electrode and conductive electrode which is connected, so as to timely release signal line
On electrostatic.Electrostatic can be realized it is not necessary that electrostatic protection device is arranged in the array substrate provided due to the utility model embodiment
The function of protection can occupy excessive space to avoid electrostatic protection device, be conducive to the realization of narrow frame display panel, and can
To reduce the manufacturing cost of array substrate.
Description of the drawings
It is required in being described below to embodiment in order to illustrate more clearly of the technical scheme in the embodiment of the utility model
Attached drawing to be used is briefly described, it should be apparent that, the accompanying drawings in the following description is only some realities of the utility model
Example is applied, it for those of ordinary skill in the art, without creative efforts, can also be according to these attached drawings
Obtain other attached drawings.
Fig. 1 is a kind of structural schematic diagram for array substrate that the utility model embodiment provides；
Fig. 2 is a kind of sectional view for array substrate that the utility model embodiment provides；
Fig. 3 is the structural schematic diagram for another array substrate that the utility model embodiment provides；
Fig. 4 is sectional view of the array substrate shown in Fig. 3 in the directions AA；
Fig. 5 is sectional view of the array substrate shown in Fig. 3 in the directions BB；
Fig. 6 is the structural schematic diagram for another array substrate that the utility model embodiment provides；
Fig. 7 is sectional view of the array substrate shown in fig. 6 in the directions CC；
Fig. 8 is the structural schematic diagram for another array substrate that the utility model embodiment provides；
Fig. 9 is the structural schematic diagram for another array substrate that the utility model embodiment provides；
Figure 10 is a kind of flow chart of the manufacturing method for array substrate that the utility model embodiment provides.
Specific implementation mode
It is new to this practicality below in conjunction with attached drawing to keep the purpose of this utility model, technical solution and advantage clearer
Type embodiment is described in further detail.
Fig. 1 is a kind of structural schematic diagram for array substrate that the utility model embodiment provides, with reference to figure 1, the array base
Plate may include：Underlay substrate 00, and a plurality of signal wire that is arranged on the underlay substrate 00.
In two adjacent signal wires in a plurality of signal wire, the first signal wire 01 is connect with the first connection electrode 11,
Second signal line 02 is connect with the second connection electrode 21, which insulate with second connection electrode 21.
Conductive electrode 110 is also provided on the underlay substrate 00, Fig. 2 is one kind that the utility model embodiment provides
The sectional view of array substrate, with reference to figure 2 as can be seen that being provided with insulating layer 001 between the conductive electrode 110 and signal wire, and
The conductive electrode 110 insulate with each connection electrode.The orthographic projection of the conductive electrode 110 on underlay substrate 00 respectively with this
The orthographic projection overlapping of first connection electrode 11 and second connection electrode 21 on the underlay substrate 00.
In conclusion in the array substrate that the utility model embodiment provides, in two adjacent signal lines, per bars
Line is connect with a connection electrode, and two connection electrodes are Chong Die with orthographic projection of the conductive electrode on underlay substrate.Therefore
When generating electrostatic on either signal line, the connection electrode which is connected can constitute capacitance with the conductive electrode, should
Capacitance has good antistatic protection function.Also, when the voltage of the signal wire is higher due to accumulation of static electricity, the signal wire
Conductive path is formed between the electrode and conductive electrode that are connected, so as to the electrostatic on timely release signal line.Due to this
It, can be with it is not necessary that the function that electrostatic protection can be realized in electrostatic protection device is arranged in the array substrate that utility model embodiment provides
It avoids electrostatic protection device from occupying excessive space, is conducive to the realization of narrow frame display panel, and array substrate can be reduced
Manufacturing cost.
Fig. 3 is the structural schematic diagram for another array substrate that the utility model embodiment provides, as shown in figure 3, substrate
In a plurality of signal wire being arranged on substrate 00, per signal line (signal wire shown in Fig. 3 refer to horizontally arranged grid line)
Can be connected with connection electrode, and the orthographic projection of the conductive electrode 110 on underlay substrate 00 respectively with each connection electrode
Orthographic projection overlapping on the underlay substrate 00.
Further, referring to figs. 1 to Fig. 3 as can be seen that the first signal wire 01 and the first connection electrode 11 can be same layer
The integral structure of setting, and the first connection electrode 11 is located at the first signal wire 01 close to the side of the binary signal line 02.
Likewise, second signal line 02 and the second connection electrode 21 can be the integral structure of same layer setting, and this second
Connection electrode 21 is located at the second signal line 02 close to the side of a signal wire 01.
As a kind of optional realization method of the utility model embodiment, with reference to figure 3, which can be grid
Line is additionally provided with multiple thin film transistor (TFT)s (Thin Film Transistor, TFT) 30 on the underlay substrate 00.Fig. 4 is Fig. 3
Shown in array substrate in the sectional view in the directions AA, can be seen that each TFT 30 with reference to figure 3 and Fig. 4 may include grid, source
Pole 301, drain electrode 302 and active layer 303, wherein the grid of each TFT 30 is structure as a whole with grid line, therefore not in figure
Mark.
The conductive electrode 110 can be with the active layer 303 of TFT 30, source-drain electrode metal layer (i.e. source electrode 301 and drain electrode 302
The metal layer at place) or the setting of shading metal layer same layer, and the conductive structure that the conductive electrode 110 can be arranged with same layer is adopted
It is made of same material.
For example, when the conductive electrode 110 and source-drain electrode metal layer or shading metal layer same layer are arranged, the conductive electrode
110, which may be used metal material, is made, the metal material can be include molybdenum (Mo), molybdenum niobium alloy (MoNb), Al, aluminium neodymium alloy
(AlNd), any one of titanium (Ti) and copper (Cu)；(Fig. 4 institutes when the conductive electrode 110 and 303 same layer of active layer are arranged
Show structure), which may be used semi-conducting material and is made, which may include non-crystalline silicon
(amorphous silicon, a-Si), polysilicon or indium gallium zinc oxide (indium gallium zinc oxide,
IGZO) etc..
In addition, as shown in figure 4, when the signal wire is grid line, which is structure as a whole with the connection electrode that it is connect
(such as the first grid line 01 is structure as a whole with the first connection electrode 11, the second grid line 02 and the second connection electrode 21 are integrated knot
Structure), and when conductive electrode 110 and 303 same layer of active layer are arranged, the insulation that is arranged between the conductive electrode 110 and connection electrode
Layer 001 can be gate insulation layer.The side of the conductive electrode 110 far from underlay substrate 00 is also provided with passivation layer 002.
Further, with reference to figure 3, which can also include：The multiple data lines arranged in a crossed manner with a plurality of grid line.
In a plurality of grid line being arranged in array substrate, connection electrode, and each grid line are respectively connected with driving TFT every grid line connecting
The connection electrode connected is respectively positioned between adjacent the first data line 41 and the second data line 42.
First data line 41 can be connect with illusory (dummy) the TFT 30a of row, which can be with one
Row driving TFT 30b connections, second data line 42 relative to first data line 41 in the array substrate other respectively
Column data line, i.e. first data line 41 are arranged in the edge of the underlay substrate 00.
Fig. 5 is sectional view of the array substrate shown in Fig. 3 in the directions BB, can be seen that driving TFT in conjunction with Fig. 3 and Fig. 5
The drain electrode 302 of 30b is connect with pixel electrode 50, for charging for the pixel electrode 50；And illusory TFT 30a then unconnected pixels
Electrode, the i.e. illusory TFT 30a are not intended to the TFT of driving, can be for for ensureing that the structural symmetry of array substrate is set
The TFT set.
Grid line due in a plurality of grid line that is arranged in array substrate, being located at edge may be illusory grid line, the i.e. grid
The TFT that line is connected is illusory TFT.The influence of the performance of the electrostatic array substrate accumulated on the illusory grid line is smaller, because
This illusory grid line may not need connection connection electrode.
With continued reference to Fig. 3, the first adjacent data line 41 and the second data 42 can surround row void with a plurality of grid line
If pixel, the illusory TFT 30a unconnected pixels electrodes included by the dummy pixel.Wherein, it is connected per adjacent two grid lines
The first connection electrode 11 and the second connection electrode 21 can be located at a dummy pixel pixel region in.
Correspondingly, as shown in figure 3, the conductive electrode 110 may include multiple spaced electrode block 10a, Mei Ge electricity
Pole block 10a is located in the pixel region of a dummy pixel, and orthographic projections of the electrode block 10a on the underlay substrate 00 with should
Orthographic projection overlapping of the connection electrode being arranged in pixel region on the underlay substrate 00.That is to say, per adjacent two grid lines it
Between an electrode block 10a can be set, two connection electrodes that electrode block 10a can be connect with two grid lines distinguish shape
At capacitance.
It is exemplary, in array substrate shown in Fig. 3, the first connection electrode 11 that the first row grid line 01 is connected, and
The second connection electrode 21 that second row grid line 02 is connected, is respectively positioned in the pixel region of the dummy pixel of the first row first row.
Electrode block 10a is additionally provided in the pixel region, orthographic projections of the electrode block 10a on underlay substrate 00 and the first connection electrode
The 11 orthographic projection overlapping on underlay substrate 00, and it is Chong Die with orthographic projection of second connection electrode 21 on underlay substrate 00.
With reference to figure 3 and Fig. 4, in an optional implementation manner, each electrode block 10a can be with its in array substrate
His conductive structure insulate, i.e., each electrode block 10a is arranged independently of other conductive structures on the underlay substrate 00, and the electricity
Pole block 10a is not also connect with external electrode, external circuit or bonding pad (bondingpad).
Fig. 6 is the structural schematic diagram for another array substrate that the utility model embodiment provides, and Fig. 7 is shown in fig. 6
Array substrate the directions CC sectional view, with reference to figure 6 and Fig. 7, in another optional realization method, each dummy pixel
Illusory TFT 30a active layers 303 can be structure as a whole with the electrode block 10a being arranged in its pixel region.
Optionally, as shown in fig. 6, being also provided with third number between first data line 41 and second data line 42
According to line 43, which is also provided with the 4th data line 44.
Wherein, the third data line 43 and the 4th data line 44 are connect with the illusory TFT 30a of row respectively.Due to every phase
Adjacent two data lines and a plurality of grid line on underlay substrate 00 can surround a row pixel, and the first data line 41, third data
The TFT that line 43 and the 4th data line 44 are connected is the illusory TFT 30a of unconnected pixels electrode, therefore the underlay substrate 00
On, a row dummy pixel, the first data line 41 and third data can be formed between the 4th data line 44 and the first data line 41
A row dummy pixel can be formed between line 43, it is illusory to form a row between third data line 43 and the second data line 42
Pixel.
Fig. 8 is the structural schematic diagram for another array substrate that the utility model embodiment provides, optional at another
In realization method, as shown in figure 8, the conductive electrode 110 can also be strip shaped electric poles, i.e. the conductive electrode 110 can be strip
The integral structure of shape, the orthographic projection of the strip shaped electric poles 110 on underlay substrate 00 is with each connection electrode in the underlay substrate 00
On orthographic projection be overlapped.
Also, with reference to figure 8 it can also be seen that the illusory TFT that the strip shaped electric poles 110 can be connect with the first data line 41
The active layer of 30a can be structure as a whole.
Fig. 9 is the structural schematic diagram for another array substrate that the utility model embodiment provides, as the utility model
Another optional realization method of embodiment, with reference to figure 9, which can also be data line, on the underlay substrate 00
It is also provided with multiple TFT, such as illusory TFT 30a shown in Fig. 9, and driving TFT 30b.
The conductive electrode 110 can be arranged with gate metal layer (i.e. layer where grid line) same layer of the TFT, and conduction electricity
Pole 110 may be used material identical with the gate metal layer and be made.
Further, as shown in figure 9, can be connected with connection electrode per data line, and per adjacent two data line
The connection electrode connected is respectively positioned between adjacent the first grid line 61 and the second grid line 62.Wherein, the first grid line 61 can be with
The illusory TFT 30a connections of a line, second grid line 62 can with a line drive TFT 30b connect, second grid line 62 relative to
Other each row grid lines of first grid line 61 in the array substrate, i.e. first grid line 61 can be arranged in the underlay substrate
00 edge.
With reference to figure 9 it can also be seen that adjacent the first grid line 61 and the second grid line 62 can be surrounded with the multiple data lines
A line dummy pixel, the illusory TFT unconnected pixels electrode included by the dummy pixel.Wherein, per adjacent two data lines institute
The first connection electrode 11 and the second connection electrode 21 of connection can be located in the pixel region of a dummy pixel.
Likewise, for the scene that a plurality of signal wire is data line, which can be strip shaped electric poles, or
Person, the conductive electrode 110 can also include multiple spaced electrode blocks, and each electrode block can be tied independently of other conductions
Structure is arranged.
In the utility model embodiment, each connection electrode is arranged in addition to the signal wire same layer that can be connect with it,
It can not also be arranged with signal wire same layer, i.e., the two can different layer setting.Correspondingly, first signal wire 01 can pass through first
Contact via is connect with first connection electrode 11, which can contact via by second and second be connect with this
Electrode 21 connects.
Optionally, referring to figs. 1 to Fig. 9 as can be seen that each connection electrode can be strip shaped electric poles, and the strip shaped electric poles
The extending direction of signal wire that is connect with it of extending direction it is vertical.
For example, when the signal wire is grid line, as shown in Fig. 3, Fig. 6 and Fig. 8, connection electrode which is connected is prolonged
Stretching direction can be parallel with the extending direction of data line.When the signal wire is data line, as shown in figure 9, the data line connects
The extending direction of the connection electrode connect can be parallel with the extending direction of grid line.
Further, the input terminal per signal line or output end are connected with connection electrode.It that is to say, the connection electrode
It can be arranged in the edge of underlay substrate 00, be impacted to avoid to the normal display of display panel.
Optionally, when first connection electrode 11 and 21 same layer of the second connection electrode are arranged, with reference to figure 3 and Fig. 4, the
May range from for the width w1 in the gap between one connection electrode 11 and second connection electrode 21 can be micro- with 2 microns to 20
Rice.
In addition, the width w2's of the conductive electrode 110 may range from 10 microns to 90 microns.Also, the conductive electrode
110 width can be more than the width of connection electrode, to ensure to increase the overlapping region between the conductive electrode and connection electrode
Area, to both increase the antistatic capacity of the capacitance formed.
Wherein, the signal wire that the width direction of conductive electrode and connection electrode is connected each parallel to the connection electrode prolongs
Stretch direction, and the signal wire that the width direction in the gap between two connection electrodes is then connected perpendicular to the connection electrode prolongs
Stretch direction.
Further, it can also be seen that the conductive electrode 110 extended in a first direction from Fig. 3, Fig. 6, Fig. 8 and Fig. 9
Orthographic projection of the axis on underlay substrate 00, can with connection electrode along the axis that the first direction extends on underlay substrate 00
Orthographic projection overlap, the extending direction for the signal wire which is connected perpendicular to connection electrode.By by conductive electrode
110 are coaxially arranged with connection electrode, it is ensured that the orthographic projection of conductive electrode 110 can be compared with limits and connection electrode
Orthographic projection is overlapped, to increase the area of the overlapping region between the conductive electrode 110 and connection electrode as possible.
In conclusion in the array substrate that the utility model embodiment provides, in two adjacent signal lines, per bars
Line is connect with a connection electrode, and two connection electrodes are Chong Die with orthographic projection of the conductive electrode on underlay substrate.Therefore
When generating electrostatic on either signal line, the connection electrode which is connected can constitute capacitance with the conductive electrode, should
Capacitance has good antistatic protection function.Also, when the voltage of the signal wire is higher due to accumulation of static electricity, the signal wire
Conductive path is formed between the electrode and conductive electrode that are connected, so as to the electrostatic on timely release signal line.Due to this
It, can be with it is not necessary that the function that electrostatic protection can be realized in electrostatic protection device is arranged in the array substrate that utility model embodiment provides
It avoids electrostatic protection device from occupying excessive space, is conducive to the realization of narrow frame display panel, and array substrate can be reduced
Manufacturing cost.
The utility model embodiment additionally provides a kind of manufacturing method of array substrate, and with reference to figure 10, this method can wrap
It includes：
Step 101 forms a plurality of signal wire on underlay substrate, in a plurality of signal wire in two adjacent signal wires,
First signal wire is connect with the first connection electrode, and second signal line is connect with the second connection electrode, first connection electrode with should
Second connection electrode insulate.
Exemplary, the mode that magnetron sputtering may be used deposits one layer of metallic film on the surface of underlay substrate；Later may be used
To be patterned processing to the metallic film using a photoetching process, to obtain a plurality of signal wire.The metallic film
It can be the film layer formed by any one of Mo, MoNb, Al, AlNd, Ti and Cu material, or can be by above-mentioned material
Multiple material formed single-layer or multi-layer composite laminate.
Step 102 forms conductive electrode on underlay substrate, and insulating layer is formed between the conductive electrode and signal wire,
And the conductive electrode insulate with each connection electrode, orthographic projection of the conductive electrode on the underlay substrate respectively with this first
The orthographic projection overlapping of connection electrode and second connection electrode on the underlay substrate.
In the utility model embodiment, which can be formed by metal material, can also be by semi-conducting material
It is formed.
When the conductive electrode is formed by metal material, the mode that magnetron sputtering may be used is heavy on the surface of underlay substrate
One layer of metallic film of product；A photoetching process may be used later, processing is patterned to the metallic film, to be somebody's turn to do
Conductive electrode.
When the conductive electrode is formed by semi-conducting material, plasma enhanced chemical vapor deposition may be used
(Plasma Enhanced Chemical Vapor Deposition, PECVD) technique deposits one layer on the surface of underlay substrate
Semiconductor material thin film；A photoetching process may be used later, processing is patterned to the semiconductor material thin film, to
Obtain the conductive electrode.
It should be noted that the execution sequence of above-mentioned steps 101 and step 102 can be adjusted according to actual conditions,
I.e. step 102 can also execute before step 101, and the utility model embodiment does not limit this.
In the utility model embodiment, multiple thin film transistor (TFT)s can also be formed on the underlay substrate.
In an optional implementation manner, which can be grid line, then the conductive electrode can be with film
Source-drain electrode metal layer, active layer or the shading metal layer of transistor are formed by a patterning processes same layer, and conduction electricity
The conductive structure that can be extremely formed with same layer is formed using same material.
In another optional realization method, which can be data line, which can be with this
The gate metal layer of thin film transistor (TFT) is formed by a patterning processes same layer, and may be used identical with the gate metal layer
Material is formed.
Also, according to the difference of the type of thin film transistor (TFT) in array substrate, the conductive electrode and connection electrode (or signal
Line) between the insulating layer that is formed can also be able to be either the film layers such as passivation layer or interlayer dielectric layer with gate insulation layer.Being formed should
The insulating materials of insulating layer may include silica, silicon nitride, aluminium oxide, hafnium oxide or molybdenum oxide etc..
The utility model embodiment provides a kind of display device, which may include：As Fig. 1 to Fig. 9 is any
Shown in array substrate.The display device can be：Liquid crystal display panel, Electronic Paper, mobile phone, tablet computer, television set, display,
Any product or component with display function such as laptop, Digital Frame, navigator.
The above is only the preferred embodiment of the present invention, is not intended to limit the utility model, all in this practicality
Within novel spirit and principle, any modification, equivalent replacement, improvement and so on should be included in the guarantor of the utility model
Within the scope of shield.
Claims (15)
1. a kind of array substrate, which is characterized in that the array substrate includes：Underlay substrate, and be arranged in the substrate base
A plurality of signal wire on plate；
In two adjacent signal wires, the first signal wire is connect with the first connection electrode, second signal line and the second connection electrode
Connection, first connection electrode insulate with second connection electrode；
It is additionally provided with conductive electrode on the underlay substrate, insulating layer is provided between the conductive electrode and the signal wire,
And the conductive electrode insulate with each connection electrode, orthographic projection of the conductive electrode on the underlay substrate respectively with
The orthographic projection overlapping of first connection electrode and second connection electrode on the underlay substrate.
2. array substrate according to claim 1, which is characterized in that in a plurality of signal wire, connect per signal line
It is connected to connection electrode, orthographic projection of the conductive electrode on underlay substrate is respectively with each connection electrode in the underlay substrate
On orthographic projection overlapping.
3. array substrate according to claim 1, which is characterized in that
First signal wire and the integral structure that first connection electrode is same layer setting, and first connection electrode position
In first signal wire close to the side of the binary signal line；
The second signal line and the integral structure that second connection electrode is same layer setting, and second connection electrode position
In the second signal line close to the side of a signal wire.
4. array substrate according to claim 3, which is characterized in that a plurality of signal wire is grid line, the substrate base
Thin film transistor (TFT) TFT is additionally provided on plate；
Active layer, source-drain electrode metal layer or the shading metal layer same layer of the conductive electrode and the TFT are arranged, and described lead
The conductive structure that electrode is arranged with same layer is made of same material.
5. array substrate according to claim 4, which is characterized in that the array substrate further includes：It is handed over a plurality of grid line
Pitch the multiple data lines of setting；
In a plurality of grid line, connection electrode, and the connection that each grid line is connected are respectively connected with the driving TFT grid lines connecting
Electrode is respectively positioned between adjacent the first data line and the second data line；
Wherein, first data line is connect with an illusory TFT of row, and second data line is connect with a row driving TFT, described
Other each column data lines of second data line relative to first data line in the array substrate, the driving TFT
It is connect with pixel electrode, the illusory TFT unconnected pixels electrode.
6. array substrate according to claim 5, which is characterized in that adjacent first data line and the second data line
A row dummy pixel is surrounded with a plurality of grid line；
The first connection electrode and the second connection electrode that are connected per adjacent two grid lines are located at the pixel region of a dummy pixel
In domain；
The conductive electrode includes multiple spaced electrode blocks, and each electrode block is located at the pixel region of a dummy pixel
It is interior, and the connection electrode being arranged in orthographic projection of the electrode block on the underlay substrate and the pixel region is in the lining
Orthographic projection overlapping on substrate.
7. array substrate according to claim 6, which is characterized in that
Each electrode block insulate with other conductive structures in array substrate；
Alternatively, the active layer of the illusory TFT of each dummy pixel is structure as a whole with the electrode block being arranged in its pixel region.
8. array substrate according to claim 5, which is characterized in that first data line and second data line it
Between be additionally provided with third data line, side of first data line far from second data line is additionally provided with the 4th data
Line；
The third data line and the 4th data line are connect with an illusory TFT of row respectively.
9. array substrate according to claim 5, which is characterized in that the conductive electrode is strip shaped electric poles, the strip
Orthographic projection of the electrode on underlay substrate and orthographic projection of each connection electrode on the underlay substrate are be overlapped.
10. array substrate according to claim 2, which is characterized in that a plurality of signal wire is data line, the substrate
Thin film transistor (TFT) is additionally provided on substrate；
The gate metal layer same layer of the conductive electrode and the thin film transistor (TFT) is arranged, and the conductive electrode use with it is described
The identical material of gate metal layer is made.
11. array substrate according to claim 1, which is characterized in that first signal wire passes through the first contact via
It is connect with first connection electrode, the second signal line is connect by the second contact via with second connection electrode.
12. array substrate according to any one of claims 1 to 11, which is characterized in that each connection electrode is item
Shape electrode, and the extending direction of signal wire that the extending direction of the strip shaped electric poles is connect with it is vertical.
13. array substrate according to any one of claims 1 to 11, which is characterized in that per signal line input terminal or
Output end is connected with connection electrode.
14. array substrate according to any one of claims 1 to 11, which is characterized in that first connection electrode with it is described
Second connection electrode same layer is arranged；
The width range in the gap between first connection electrode and second connection electrode is 2 microns to 20 microns；
The width range of the conductive electrode is 10 microns to 90 microns.
15. a kind of display device, which is characterized in that the display device includes：
Array substrate as described in claim 1 to 14 is any.
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| CN201820395453.2U CN207896091U (en) | 2018-03-22 | 2018-03-22 | array substrate and display device |
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109375439A (en) * | 2018-12-20 | 2019-02-22 | 武汉华星光电技术有限公司 | Array substrate and display panel |
| CN110277411A (en) * | 2019-06-26 | 2019-09-24 | 上海天马有机发光显示技术有限公司 | A kind of array substrate, organic electroluminescent display panel and display device |
| WO2024044967A1 (en) * | 2022-08-30 | 2024-03-07 | 京东方科技集团股份有限公司 | Display substrate and method for manufacturing same, and display device |
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2018
- 2018-03-22 CN CN201820395453.2U patent/CN207896091U/en active Active
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109375439A (en) * | 2018-12-20 | 2019-02-22 | 武汉华星光电技术有限公司 | Array substrate and display panel |
| US11037961B2 (en) | 2018-12-20 | 2021-06-15 | Wuhan China Star Optoelectronics Technology Co., Ltd. | Array substrate and display panel |
| CN110277411A (en) * | 2019-06-26 | 2019-09-24 | 上海天马有机发光显示技术有限公司 | A kind of array substrate, organic electroluminescent display panel and display device |
| CN110277411B (en) * | 2019-06-26 | 2021-04-16 | 上海天马有机发光显示技术有限公司 | Array substrate, organic electroluminescent display panel and display device |
| WO2024044967A1 (en) * | 2022-08-30 | 2024-03-07 | 京东方科技集团股份有限公司 | Display substrate and method for manufacturing same, and display device |
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