TW201443532A - Display device - Google Patents
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Abstract
Description
本發明涉及一種顯示裝置，且特別涉及一種能有效降低公共電極阻抗值的顯示裝置。The present invention relates to a display device, and more particularly to a display device capable of effectively reducing the impedance value of a common electrode.
顯示裝置具有輕薄、大尺寸化、平面化及數位化等優點，近年來需求迅速增加，大量使用在電視、電腦監視器、行動電話、車用螢幕與數位相框等等。同時，隨著需求迅速增加，對於顯示裝置的品質要求，也越來越高。The display device has the advantages of being thin, large, flat, and digital. In recent years, the demand has rapidly increased, and it has been widely used in televisions, computer monitors, mobile phones, car screens, and digital photo frames. At the same time, as the demand increases rapidly, the quality requirements for display devices are also increasing.
與傳統扭曲向列型（twisted nematic）顯示裝置相比，平面內切換型（in-plane switching，IPS）顯示裝置和邊緣場切換型（fringe field switching，FFS）顯示裝置具有廣視角的優點。在平面內切換型（IPS）顯示裝置和邊緣場切換型（FFS）顯示裝置中公共電極為位於陣列基板的透明銦錫氧化物層。銦錫氧化物材料本身具有較高阻抗值，會影響信號傳輸速率。然而在高解析度的要求下，需要高信號傳輸速率。In-plane switching (IPS) display devices and fringe field switching (FFS) display devices have the advantage of a wide viewing angle compared to conventional twisted nematic display devices. The common electrode in the in-plane switching type (IPS) display device and the fringe field switching type (FFS) display device is a transparent indium tin oxide layer on the array substrate. The indium tin oxide material itself has a higher impedance value, which affects the signal transmission rate. However, at high resolution requirements, high signal transmission rates are required.
先前技術中一般通過增加公共電極的膜厚來降低其阻抗值，然而隨著公共電極膜厚的增加，會衍生出銦錫氧化物多晶化的問題，這樣在進行蝕刻工序時，會產生銦錫氧化物殘留問題，而且增加銦錫氧化物的膜厚也會增加生產成本。In the prior art, the impedance value of the common electrode is generally reduced by increasing the film thickness of the common electrode. However, as the film thickness of the common electrode increases, the problem of polycrystallization of indium tin oxide is derived, so that in the process of performing the etching process, indium is generated. The problem of tin oxide residue, and increasing the film thickness of indium tin oxide also increases production costs.
有鑑於此，有必要提供一種降低公共電極阻抗值的顯示裝置。In view of this, it is necessary to provide a display device that reduces the impedance value of the common electrode.
本發明提供一種顯示裝置，該顯示裝置的陣列基板包括：基板；薄膜電晶體，該薄膜電晶體設置於該基板之上；第一鈍化層，該第一鈍化層覆蓋該薄膜電晶體；金屬導電層，該金屬導電層至少包括第一部分，該第一部分位於該第一鈍化層之上，且該金屬導電層的膜厚小於30 A；公共電極，該公共電極覆蓋於該金屬導電層的該第一部分之上,且與該金屬導電層的該第一部分直接接觸並電性導通；第二鈍化層，該第二鈍化層覆蓋該第一鈍化層和該公共電極；像素電極，該像素電極位於該第二鈍化層之上。The present invention provides a display device, the array substrate of the display device includes: a substrate; a thin film transistor, the thin film transistor is disposed on the substrate; a first passivation layer, the first passivation layer covers the thin film transistor; a layer, the metal conductive layer includes at least a first portion, the first portion is located above the first passivation layer, and the metal conductive layer has a film thickness of less than 30 A; a common electrode, the common electrode covering the metal conductive layer a portion above and in direct contact with the first portion of the metal conductive layer and electrically conductive; a second passivation layer covering the first passivation layer and the common electrode; a pixel electrode, the pixel electrode being located Above the second passivation layer.
本發明提供另一種顯示裝置，該顯示裝置的陣列基板包括：基板；至少一個電極層設置於該基板上，該電極層包括層疊設置的非金屬導電層及金屬導電層，非金屬導電層與金屬導電層之間電性導通且二者間傳遞的電信號相同，且該金屬導電層的膜厚小於30 A。The present invention provides another display device. The array substrate of the display device includes: a substrate; at least one electrode layer is disposed on the substrate, the electrode layer includes a non-metal conductive layer and a metal conductive layer, and a non-metal conductive layer and a metal layer. The electrically conductive layers are electrically conductive and the electrical signals transmitted therebetween are the same, and the metal conductive layer has a film thickness of less than 30 Å.
由於該金屬導電層的膜厚小於30A，因此，在該厚度下，光可透過該金屬導電層，且由於本發明中該公共電極重疊於部分或全部該金屬導電層的第一部分之上，因此可有效降低該公共電極的阻抗值，提高信號的傳輸速率，從而可降低不良信號的影響，滿足高解析度的要求。Since the film thickness of the metal conductive layer is less than 30 A, light can be transmitted through the metal conductive layer at the thickness, and since the common electrode overlaps part or all of the first portion of the metal conductive layer in the present invention, The impedance value of the common electrode can be effectively reduced, and the transmission rate of the signal can be improved, thereby reducing the influence of the bad signal and meeting the requirement of high resolution.
200、300．．．陣列基板200, 300. . . Array substrate
T．．．薄膜電晶體T. . . Thin film transistor
41、71．．．基板41, 71. . . Substrate
44、74．．．半導體層44, 74. . . Semiconductor layer
42．．．遮光層42. . . Shading layer
441．．．溝道區441. . . Channel region
43．．．緩衝層43. . . The buffer layer
442．．．摻雜區442. . . Doped region
431．．．氮化矽層431. . . Tantalum nitride layer
45、73．．．閘極絕緣層45, 73. . . Gate insulation
432．．．氧化矽層432. . . Cerium oxide layer
451．．．氧化矽層451. . . Cerium oxide layer
48、75．．．資料電極48, 75. . . Data electrode
452．．．氮化矽層452. . . Tantalum nitride layer
481、751．．．源極481, 751. . . Source
46、72．．．閘極46, 72. . . Gate
482、752．．．汲極482, 752. . . Bungee
47、76．．．層間介質層47, 76. . . Interlayer dielectric layer
49．．．第一接觸孔49. . . First contact hole
471．．．氮化矽層471. . . Tantalum nitride layer
50、77．．．第一鈍化層50, 77. . . First passivation layer
472．．．氧化矽層472. . . Cerium oxide layer
51、80．．．第二鈍化層51, 80. . . Second passivation layer
52、78．．．金屬導電層52, 78. . . Metal conductive layer
53、79．．．公共電極53,79. . . Common electrode
521．．．第一部分521. . . first part
54．．．第二接觸孔54. . . Second contact hole
522．．．第二部分522. . . the second part
55、82．．．像素電極55, 82. . . Pixel electrode
56．．．第三接觸孔56. . . Third contact hole
81．．．通孔81. . . Through hole
圖1為本發明實施方式顯示裝置的陣列基板的剖視圖。1 is a cross-sectional view of an array substrate of a display device according to an embodiment of the present invention.
圖2a-2c為本發明實施方式中金屬導電層第一部分的不同圖案設計放大俯視圖。2a-2c are enlarged plan views showing different patterns of the first portion of the metal conductive layer in the embodiment of the present invention.
圖3為本發明另一實施方式顯示裝置的陣列基板的剖視圖。3 is a cross-sectional view of an array substrate of a display device according to another embodiment of the present invention.
下文將參照附圖來描述根據本發明的顯示裝置。A display device according to the present invention will hereinafter be described with reference to the accompanying drawings.
圖1示出本發明實施方式顯示裝置的陣列基板200的剖視圖，本實施方式中，該陣列基板200可由低溫多晶矽（low-temperature polycrystalline silicon，LTPS）半導體工藝形成。替代實施方式中，陣列基板可由非晶矽半導體工藝形成。1 is a cross-sectional view of an array substrate 200 of a display device according to an embodiment of the present invention. In the present embodiment, the array substrate 200 may be formed by a low-temperature polycrystalline silicon (LTPS) semiconductor process. In an alternative embodiment, the array substrate can be formed by an amorphous germanium semiconductor process.
該陣列基板100包括基板41、遮光層42、緩衝層43、薄膜電晶體T。該基板41可為玻璃基板或透明塑膠基板。The array substrate 100 includes a substrate 41, a light shielding layer 42, a buffer layer 43, and a thin film transistor T. The substrate 41 can be a glass substrate or a transparent plastic substrate.
該遮光層42為設置在該基板41上用來阻擋光線之金屬層。該緩衝層43覆蓋該基板41和該遮光層42。本實施方式中，該緩衝層43為疊層結構，其包括氮化矽層431和氧化矽層432。替代實施方式中，該緩衝層43也可為單層氮化矽層431或單層氧化矽層432。The light shielding layer 42 is a metal layer disposed on the substrate 41 for blocking light. The buffer layer 43 covers the substrate 41 and the light shielding layer 42. In the present embodiment, the buffer layer 43 is a laminated structure including a tantalum nitride layer 431 and a tantalum oxide layer 432. In an alternative embodiment, the buffer layer 43 may also be a single layer of tantalum nitride layer 431 or a single layer of tantalum oxide layer 432.
該薄膜電晶體T設置於該緩衝層43上，其至少包括半導體層44、閘極絕緣層45、閘極46和資料電極48。該資料電極48包括源極481和汲極482。The thin film transistor T is disposed on the buffer layer 43, and includes at least a semiconductor layer 44, a gate insulating layer 45, a gate 46, and a data electrode 48. The data electrode 48 includes a source 481 and a drain 482.
該半導體層44為部分覆蓋該緩衝層43上的多晶矽層，其包括溝道區441和位於該溝道區441兩側的摻雜區442。該摻雜區442為在該半導體層44相反的兩端摻雜磷離子形成。磷離子可以有效提高該摻雜區442的導電性。該遮光層42主要用來防止入射光照射到該溝道區441，該緩衝層43主要用來防止該基板41中的雜質進入該半導體層44中。The semiconductor layer 44 is a polysilicon layer partially covering the buffer layer 43, and includes a channel region 441 and doped regions 442 on both sides of the channel region 441. The doped region 442 is formed by doping phosphorus ions at opposite ends of the semiconductor layer 44. Phosphorus ions can effectively increase the conductivity of the doped region 442. The light shielding layer 42 is mainly used to prevent incident light from being irradiated to the channel region 441, and the buffer layer 43 is mainly used to prevent impurities in the substrate 41 from entering the semiconductor layer 44.
該閘極絕緣層45覆蓋該半導體層44和該緩衝層43。本實施方式中，該閘極絕緣層45為包括氧化矽層451和氮化矽層452的疊層結構。該氧化矽層451覆蓋整個半導體層44。該氮化矽層452僅設於該半導體層44的該溝道區441。替代實施方式中，該閘極絕緣層45也可為單層氧化矽層451或單層氮化矽層452，此時該單層氮化矽層452為覆蓋整個半導體層44的整層結構。The gate insulating layer 45 covers the semiconductor layer 44 and the buffer layer 43. In the present embodiment, the gate insulating layer 45 is a laminated structure including a hafnium oxide layer 451 and a tantalum nitride layer 452. The yttria layer 451 covers the entire semiconductor layer 44. The tantalum nitride layer 452 is provided only in the channel region 441 of the semiconductor layer 44. In an alternative embodiment, the gate insulating layer 45 may also be a single layer of tantalum oxide layer 451 or a single layer of tantalum nitride layer 452. In this case, the single layer of tantalum nitride layer 452 is a whole layer structure covering the entire semiconductor layer 44.
該閘極46為設置在該閘極絕緣層45上的金屬鉬層。該閘極46與該氮化矽層452層疊並設於該半導體層44的該溝道區441。本實施方式中，該閘極46及該氮化矽層452分別都包括兩個相互間隔的島狀部分。The gate 46 is a metal molybdenum layer disposed on the gate insulating layer 45. The gate 46 is stacked on the tantalum nitride layer 452 and disposed in the channel region 441 of the semiconductor layer 44. In this embodiment, the gate 46 and the tantalum nitride layer 452 each include two island portions that are spaced apart from each other.
層間介質層47覆蓋該薄膜電晶體T。本實施方式中，該層間介質層47為包括氮化矽層471和氧化矽層472的疊層結構。替代實施方式中，該層間介質層47可為單層氮化矽層471或單層氧化矽層472。本實施方式中，該閘極絕緣層45及該層間介質層47共同定義有兩個第一接觸孔49，每個第一接觸孔49分別貫穿該閘極絕緣層45的預定部分和該層間介質層47的預定部分，以露出部分該半導體層44。本實施方式中，該每個第一接觸孔49對應一個摻雜區442。An interlayer dielectric layer 47 covers the thin film transistor T. In the present embodiment, the interlayer dielectric layer 47 is a laminated structure including a tantalum nitride layer 471 and a tantalum oxide layer 472. In an alternative embodiment, the interlayer dielectric layer 47 can be a single layer of tantalum nitride layer 471 or a single layer of tantalum oxide layer 472. In this embodiment, the gate insulating layer 45 and the interlayer dielectric layer 47 are defined by two first contact holes 49, and each of the first contact holes 49 penetrates a predetermined portion of the gate insulating layer 45 and the interlayer dielectric. A predetermined portion of the layer 47 is to expose a portion of the semiconductor layer 44. In this embodiment, each of the first contact holes 49 corresponds to one doping region 442.
該資料電極48通過該第一接觸孔49與該半導體層44接觸。該兩個第一接觸孔49中的資料電極48分別定義為源極481和汲極482。本實施方式中，該資料電極48為鉬-鋁-鉬的疊層金屬結構。替代實施方式中，該資料電極48可為單層金屬鉬層。The data electrode 48 is in contact with the semiconductor layer 44 through the first contact hole 49. The data electrodes 48 of the two first contact holes 49 are defined as a source 481 and a drain 482, respectively. In the present embodiment, the data electrode 48 is a laminated metal structure of molybdenum-aluminum-molybdenum. In an alternative embodiment, the data electrode 48 can be a single layer of metal molybdenum.
本實施方式中，該陣列基板還包括第一鈍化層50、金屬導電層52、公共電極53、第二鈍化層51、和像素電極55。In this embodiment, the array substrate further includes a first passivation layer 50, a metal conductive layer 52, a common electrode 53, a second passivation layer 51, and a pixel electrode 55.
該第一鈍化層50覆蓋該層間介質層47和該源極481。該第一鈍化層50為有機絕緣層。該第一鈍化層50定義有貫穿該第一鈍化層50預定部分的第二接觸孔54。該第二接觸孔54用於露出該汲極482。The first passivation layer 50 covers the interlayer dielectric layer 47 and the source 481. The first passivation layer 50 is an organic insulating layer. The first passivation layer 50 defines a second contact hole 54 extending through a predetermined portion of the first passivation layer 50. The second contact hole 54 is for exposing the drain 482.
該金屬導電層52為金屬鉬層，其包括相互絕緣隔離的第一部分521和第二部分522。該第一部分521位於該第一鈍化層50之上，用來傳輸公共電壓。該第二部分522部分覆蓋該第一鈍化層50及該第二接觸孔54的內表面，並與該汲極482接觸。本實施方式中，該金屬導電層52的膜厚需小於30A，以實現透光之目的。The metal conductive layer 52 is a metal molybdenum layer comprising a first portion 521 and a second portion 522 that are insulated from each other. The first portion 521 is located above the first passivation layer 50 for transmitting a common voltage. The second portion 522 partially covers the inner surfaces of the first passivation layer 50 and the second contact hole 54 and is in contact with the drain 482. In this embodiment, the thickness of the metal conductive layer 52 needs to be less than 30 A to achieve the purpose of light transmission.
該公共電極53為覆蓋於該金屬導電層52的該第一部分521之上的銦錫氧化物層。該公共電極53與該金屬導電層52的該第一部分521直接接觸並電性導通，二者傳遞的電信號相同。本實施方式中，該公共電極53為完全覆蓋該金屬導電層52的第一部分521上的銦錫氧化物層，且兩者面積相等。替代實施方式中，該公共電極53完全重疊於該金屬導電層52的第一部分521，該金屬導電層52的第一部分521沒有全部被該公共電極53覆蓋。The common electrode 53 is an indium tin oxide layer overlying the first portion 521 of the metal conductive layer 52. The common electrode 53 is in direct contact with the first portion 521 of the metal conductive layer 52 and is electrically connected, and the electrical signals transmitted by the two are the same. In this embodiment, the common electrode 53 is an indium tin oxide layer completely covering the first portion 521 of the metal conductive layer 52, and the two areas are equal in area. In an alternative embodiment, the common electrode 53 is completely overlapped with the first portion 521 of the metal conductive layer 52, and the first portion 521 of the metal conductive layer 52 is not entirely covered by the common electrode 53.
該第二鈍化層51為覆蓋該第一鈍化層50和該公共電極53的氮化矽層。本實施方式中，該第二鈍化層51定義有貫穿該第二鈍化層51預定部分的第三接觸孔56。該第三接觸孔56對應該第二接觸孔54設置，用於露出該金屬導電層52的第二部分522。The second passivation layer 51 is a tantalum nitride layer covering the first passivation layer 50 and the common electrode 53. In the embodiment, the second passivation layer 51 defines a third contact hole 56 penetrating a predetermined portion of the second passivation layer 51. The third contact hole 56 is disposed corresponding to the second contact hole 54 for exposing the second portion 522 of the metal conductive layer 52.
該像素電極55為覆蓋部分該第二鈍化層51的銦錫氧化物層，其依次通過該第三接觸孔56及該第二接觸孔54連接該金屬導電層52的第二部分522，進而實現同該汲極482的電連接。The pixel electrode 55 is an indium tin oxide layer covering a portion of the second passivation layer 51. The third contact portion 56 and the second contact hole 54 are sequentially connected to the second portion 522 of the metal conductive layer 52. Electrical connection to the drain 482.
替代實施方式中，該金屬導電層52可設計不同的圖案。圖2a-2c為本發明實施方式中該金屬導電層52的該第一部分521不同圖案設計的三個實施方式放大俯視圖。如圖2a所示，該金屬導電層52的第一部分521的圖案可為片狀結構。如圖2b所示，該金屬導電層52的第一部分521的圖案也可為馬賽克圖案。如圖2c所示，該金屬導電層52的第一部分521的圖案也可為網格圖案。In alternative embodiments, the metal conductive layer 52 can be designed in different patterns. 2a-2c are enlarged top views of three embodiments of different pattern designs of the first portion 521 of the metal conductive layer 52 in accordance with an embodiment of the present invention. As shown in FIG. 2a, the pattern of the first portion 521 of the metal conductive layer 52 may be a sheet-like structure. As shown in FIG. 2b, the pattern of the first portion 521 of the metal conductive layer 52 may also be a mosaic pattern. As shown in FIG. 2c, the pattern of the first portion 521 of the metal conductive layer 52 may also be a grid pattern.
本實施方式中，由於該公共電極53部分覆蓋或完全覆蓋膜厚小於30A的該金屬導電層52的第一部分521，因此，該公共電極53的阻抗值可被有效降低。In the present embodiment, since the common electrode 53 partially covers or completely covers the first portion 521 of the metal conductive layer 52 having a film thickness of less than 30 A, the impedance value of the common electrode 53 can be effectively reduced.
替代實施方式中，本發明也可應用於非晶矽技術領域，如圖3所示，本發明另一實施方式的陣列基板300包括基板71、薄膜電晶體T。該基板71可為玻璃基板或透明塑膠基板。In an alternative embodiment, the present invention is also applicable to the field of amorphous germanium. As shown in FIG. 3, the array substrate 300 according to another embodiment of the present invention includes a substrate 71 and a thin film transistor T. The substrate 71 can be a glass substrate or a transparent plastic substrate.
該薄膜電晶體T設置於該基板71之上，其至少包括閘極72、閘極絕緣層73、半導體層74和資料電極75。該資料電極75包括源極751和汲極752。The thin film transistor T is disposed on the substrate 71 and includes at least a gate 72, a gate insulating layer 73, a semiconductor layer 74, and a data electrode 75. The data electrode 75 includes a source 751 and a drain 752.
該閘極72為設置在該基板71之上的金屬鉬層。該閘極絕緣層73完全覆蓋該閘極72，本實施方式中，該閘極絕緣層73為單層氮化矽層或單層氧化矽層。替代實施方式中，該閘極絕緣層73可為氮化矽層和氧化矽層的疊層結構。該半導體層74為部分覆蓋該閘極絕緣層73的非晶矽層，且該半導體層74完全覆蓋該閘極72。該資料電極75設置在該半導體層74和該閘極絕緣層73之上，該源極751和該汲極752分別位於該半導體層74的兩側，彼此電性絕緣，且都與該半導體層74部分重疊。本實施方式中，該資料電極75為單層金屬鉬層。替代實施方式中，該資料電極75可為鉬-鋁-鉬的層疊金屬結構。The gate 72 is a metal molybdenum layer disposed on the substrate 71. The gate insulating layer 73 completely covers the gate 72. In the embodiment, the gate insulating layer 73 is a single layer of tantalum nitride layer or a single layer of tantalum oxide layer. In an alternative embodiment, the gate insulating layer 73 may be a stacked structure of a tantalum nitride layer and a tantalum oxide layer. The semiconductor layer 74 is an amorphous germanium layer partially covering the gate insulating layer 73, and the semiconductor layer 74 completely covers the gate 72. The data electrode 75 is disposed on the semiconductor layer 74 and the gate insulating layer 73. The source electrode 751 and the drain electrode 752 are respectively located on opposite sides of the semiconductor layer 74, electrically insulated from each other, and both of the semiconductor layer 74 parts overlap. In the present embodiment, the data electrode 75 is a single-layer metal molybdenum layer. In an alternative embodiment, the data electrode 75 can be a laminated metal structure of molybdenum-aluminum-molybdenum.
層間介質層76覆蓋該薄膜電晶體T。本實施方式中，該層間介質層76為單層氮化矽層或單層氧化矽層。替代實施方式中，該層間介質層76可為氮化矽層和氧化矽層的疊層結構。An interlayer dielectric layer 76 covers the thin film transistor T. In this embodiment, the interlayer dielectric layer 76 is a single layer of tantalum nitride layer or a single layer of tantalum oxide layer. In an alternative embodiment, the interlayer dielectric layer 76 may be a stacked structure of a tantalum nitride layer and a tantalum oxide layer.
本實施方式中，該陣列基板300還包括第一鈍化層77、金屬導電層78、公共電極79、第二鈍化層80、像素電極82。In the embodiment, the array substrate 300 further includes a first passivation layer 77, a metal conductive layer 78, a common electrode 79, a second passivation layer 80, and a pixel electrode 82.
該第一鈍化層77覆蓋該層間介質層76，且該第一鈍化層77為有機絕緣層。該金屬導電層78為金屬鉬層，用來傳輸公共電壓。本實施方式中，該金屬導電層78只包括位於該第一鈍化層77之上的第一部分，且該金屬導電層78的膜厚小於30 A，以實現透光之目的。The first passivation layer 77 covers the interlayer dielectric layer 76, and the first passivation layer 77 is an organic insulating layer. The metal conductive layer 78 is a metal molybdenum layer for transmitting a common voltage. In this embodiment, the metal conductive layer 78 includes only the first portion above the first passivation layer 77, and the metal conductive layer 78 has a film thickness of less than 30 A for the purpose of light transmission.
該公共電極79為覆蓋於該金屬導電層78的第一部分上的銦錫氧化物層，且與該金屬導電層78的該第一部分直接接觸並電性導通，二者傳遞的電信號相同。由於本實施方式中，該金屬導電層78只包括位於該第一鈍化層77之上的第一部分，因此，本實施方式中，該公共電極79實際覆蓋於該金屬導電層78之上。本實施方式中，該公共電極79完全覆蓋該金屬導電層78，且兩者面積相等。替代實施方式中，該公共電極79完全重疊於該金屬導電層78，而該金屬導電層78沒有完全被該公共電極79覆蓋。The common electrode 79 is an indium tin oxide layer covering the first portion of the metal conductive layer 78, and is in direct contact with the first portion of the metal conductive layer 78 and electrically connected, and the electrical signals transmitted by the two are the same. In this embodiment, the metal conductive layer 78 includes only the first portion on the first passivation layer 77. Therefore, in the embodiment, the common electrode 79 actually covers the metal conductive layer 78. In this embodiment, the common electrode 79 completely covers the metal conductive layer 78, and the two areas are equal in area. In an alternative embodiment, the common electrode 79 is completely overlaid on the metal conductive layer 78, and the metal conductive layer 78 is not completely covered by the common electrode 79.
該第二鈍化層80為覆蓋該第一鈍化層77和該公共電極79的氮化矽層。本實施方式中，該第二鈍化層80、該第一鈍化層77和該層間介質層76共同定義有通孔81，該通孔貫穿該第二鈍化層80預定部分、該第一鈍化層77預定部分和該層間介質層76預定部分，用於露出部分該汲極752。The second passivation layer 80 is a tantalum nitride layer covering the first passivation layer 77 and the common electrode 79. In this embodiment, the second passivation layer 80, the first passivation layer 77, and the interlayer dielectric layer 76 are defined by a through hole 81 extending through a predetermined portion of the second passivation layer 80 and the first passivation layer 77. The predetermined portion and the predetermined portion of the interlayer dielectric layer 76 serve to expose a portion of the drain 752.
該像素電極82為位於該第二鈍化層80的銦錫氧化物層，其通過該通孔81與該汲極752電連接。The pixel electrode 82 is an indium tin oxide layer on the second passivation layer 80, and is electrically connected to the drain 752 through the through hole 81.
替代實施方式中，該金屬導電層78可設計成不同的圖案，如圖2a-2c所示的片狀結構、馬賽克圖案或網格圖案。In alternative embodiments, the metal conductive layer 78 can be designed in a different pattern, such as a sheet structure, a mosaic pattern, or a grid pattern as shown in Figures 2a-2c.
本實施方式中，由於該公共電極79部分覆蓋或完全覆蓋膜厚小於30A的該金屬導電層78，因此，該公共電極79的阻抗值可被有效降低。In the present embodiment, since the common electrode 79 partially covers or completely covers the metal conductive layer 78 having a film thickness of less than 30 A, the impedance value of the common electrode 79 can be effectively reduced.
替代實施方式中，該陣列基板可包括透明基板。至少一個電極層設置於該基板上，該電極層包括層疊設置的非金屬導電層及金屬導電層，該非金屬導電層與該金屬導電層之間電性導通且二者間傳遞的電信號相同，該金屬導電層位於基板與非金屬導電層之間且與該非金屬導電層直接接觸。該非金屬導電層為銦錫氧化物層。該金屬導電層為膜厚小於30 A的金屬鉬層，可實現透光。In an alternative embodiment, the array substrate can include a transparent substrate. At least one electrode layer is disposed on the substrate, the electrode layer includes a non-metal conductive layer and a metal conductive layer disposed in a stack, and the non-metal conductive layer is electrically connected to the metal conductive layer and the electrical signals transmitted therebetween are the same. The metal conductive layer is located between the substrate and the non-metallic conductive layer and is in direct contact with the non-metal conductive layer. The non-metallic conductive layer is an indium tin oxide layer. The metal conductive layer is a metal molybdenum layer having a film thickness of less than 30 A, and light transmittance can be achieved.
該陣列基板還可包括：設置於該基板之上的薄膜電晶體；覆蓋該薄膜電晶體的第一鈍化層；由上述電極層形成的公共電極，由於該公共電極為非金屬導電層與金屬導電層的層疊結構，因此可有效降低該公共電極的阻抗值；覆蓋該第一鈍化層和該公共電極的第二鈍化層；位於該第二鈍化層之上的像素電極。The array substrate may further include: a thin film transistor disposed on the substrate; a first passivation layer covering the thin film transistor; a common electrode formed by the electrode layer, wherein the common electrode is a non-metallic conductive layer and a metal conductive a layered structure of layers, thereby effectively reducing the impedance value of the common electrode; a second passivation layer covering the first passivation layer and the common electrode; and a pixel electrode located above the second passivation layer.
本發明精神或範圍的情況下可對本發明作出各種修改和變型。因此，本發明旨在涵蓋落入所附權利要求書範圍及其等效範圍內的對本發明的所有各種修改和變型。Various modifications and variations of the present invention are possible in the embodiments of the invention. Accordingly, the invention is intended to embrace all such modifications and modifications of the invention
200．．．陣列基板200. . . Array substrate
471．．．氮化矽層471. . . Tantalum nitride layer
41．．．基板41. . . Substrate
472．．．矽氧化層472. . . Antimony oxide layer
42．．．遮光層42. . . Shading layer
48．．．資料電極48. . . Data electrode
43．．．緩衝層43. . . The buffer layer
481．．．源極481. . . Source
431．．．氮化矽層431. . . Tantalum nitride layer
482．．．汲極482. . . Bungee
432．．．氧化矽層432. . . Cerium oxide layer
49．．．第一接觸孔49. . . First contact hole
T．．．薄膜電晶體T. . . Thin film transistor
50．．．第一鈍化層50. . . First passivation layer
44．．．半導體層44. . . Semiconductor layer
51．．．第二鈍化層51. . . Second passivation layer
441．．．溝道區441. . . Channel region
52．．．金屬導電層52. . . Metal conductive layer
442．．．摻雜區442. . . Doped region
521．．．第一部分521. . . first part
45．．．閘極絕緣層45. . . Gate insulation
522．．．第二部分522. . . the second part
451．．．氧化矽層451. . . Cerium oxide layer
53．．．公共電極53. . . Common electrode
452．．．氮化矽層452. . . Tantalum nitride layer
54．．．第二接觸孔54. . . Second contact hole
46．．．閘極46. . . Gate
55．．．像素電極55. . . Pixel electrode
47．．．層間介質層47. . . Interlayer dielectric layer
56．．．第三接觸孔56. . . Third contact hole
Claims (15)
基板；
薄膜電晶體，該薄膜電晶體設置於該基板之上；
第一鈍化層，該第一鈍化層覆蓋該薄膜電晶體；
金屬導電層，該金屬導電層至少包括第一部分，該第一部分位於該第一鈍化層之上，且該金屬導電層的膜厚小於30 A；
公共電極，該公共電極覆蓋於該金屬導電層的該第一部分之上,且與該金屬導電層的該第一部分直接接觸並電性導通；
第二鈍化層，該第二鈍化層覆蓋該第一鈍化層和該公共電極；
像素電極，該像素電極位於該第二鈍化層之上。A display device, the array substrate of the display device comprises:
Substrate
a thin film transistor, the thin film transistor being disposed on the substrate;
a first passivation layer, the first passivation layer covering the thin film transistor;
a metal conductive layer, the metal conductive layer comprising at least a first portion, the first portion is located above the first passivation layer, and the metal conductive layer has a film thickness of less than 30 A;
a common electrode covering the first portion of the metal conductive layer and in direct contact with the first portion of the metal conductive layer and electrically conducting;
a second passivation layer covering the first passivation layer and the common electrode;
a pixel electrode, the pixel electrode being located above the second passivation layer.
基板；
至少一個電極層設置於該基板上，該電極層包括層疊設置的非金屬導電層及金屬導電層，非金屬導電層與金屬導電層之間電性導通且二者間傳遞的電信號相同，且該金屬導電層的膜厚小於30 A。A display device, the array substrate of the display device comprises:
Substrate
At least one electrode layer is disposed on the substrate, the electrode layer includes a non-metal conductive layer and a metal conductive layer disposed in a stack, and the non-metal conductive layer and the metal conductive layer are electrically connected and the electrical signals transmitted therebetween are the same, and The metal conductive layer has a film thickness of less than 30 Å.
薄膜電晶體，該薄膜電晶體設置於該基板之上；
第一鈍化層，該第一鈍化層覆蓋該薄膜電晶體；
由上述電極層形成的公共電極；
第二鈍化層，該第二鈍化層覆蓋該第一鈍化層和該公共電極；
像素電極，該像素電極位於該第二鈍化層之上。
The display device of any one of claims 10-14, wherein the array substrate further comprises:
a thin film transistor, the thin film transistor being disposed on the substrate;
a first passivation layer, the first passivation layer covering the thin film transistor;
a common electrode formed by the above electrode layer;
a second passivation layer covering the first passivation layer and the common electrode;
a pixel electrode, the pixel electrode being located above the second passivation layer.
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| CN105140244B (en) * | 2015-09-25 | 2018-11-06 | 武汉华星光电技术有限公司 | Array substrate and its manufacturing method, display device |
| CN105278193B (en) * | 2015-11-19 | 2018-09-18 | 深圳市华星光电技术有限公司 | Array substrate and its manufacturing method, liquid crystal display panel |
| KR102456121B1 (en) * | 2015-12-15 | 2022-10-17 | 엘지디스플레이 주식회사 | Light controlling device, transparent display device including the same and method for manufacturing the same |
| CN105470266B (en) * | 2016-01-04 | 2018-06-01 | 武汉华星光电技术有限公司 | FFS type array substrates and preparation method thereof |
| TWI671578B (en) | 2018-03-30 | 2019-09-11 | 友達光電股份有限公司 | Pixel structure and touch panel |
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| KR100849599B1 (en) * | 2007-02-05 | 2008-07-31 | 비오이 하이디스 테크놀로지 주식회사 | Fringe field switching mode liquid crystal display device |
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