CN207896092U - array substrate and display device - Google Patents
array substrate and display device Download PDFInfo
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- CN207896092U CN207896092U CN201820396778.2U CN201820396778U CN207896092U CN 207896092 U CN207896092 U CN 207896092U CN 201820396778 U CN201820396778 U CN 201820396778U CN 207896092 U CN207896092 U CN 207896092U
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Abstract
The utility model discloses a kind of array substrate and display devices, belong to display technology field.The array substrate includes：Underlay substrate, and a plurality of signal wire that is arranged on the underlay substrate；There are at least one target signal line in a plurality of signal wire, at least side in the both sides of the target signal line is provided with conductive electrode；The conductive electrode insulate with other conductive structures in the array substrate, and orthographic projection of the conductive electrode on the underlay substrate is Chong Die with orthographic projection of the target signal line on the underlay substrate.Array substrate provided by the utility model has antistatic protection function, and it is not necessary that electrostatic protection device is arranged, structure is relatively simple, is conducive to the realization of narrow frame display panel.
Description
Technical field
The utility model is related to display technology field, more particularly to a kind of array substrate and display device.
Background technology
In array substrate manufacturing process, since the techniques such as plasma-deposited, film layer etching and friction easy to produce electrostatic,
Electrostatic breakdown and electrostatic damage may occur for the signal wire therefore formed in array substrate, cause array substrate bad.In order to protect
The normal work of various signal wires is demonstrate,proved, the electrostatic protection device being connect with signal wire can be set in array substrate.
Electrostatic protection device in the related technology generally comprise multiple transistors and at least one electrostatic defending line (such as
Public electrode wire or short-circuited conducting sleeve etc.), each transistor can be connect with a signal line and the electrostatic defending line respectively, will
The electrostatic generated on signal wire is discharged in time to the electrostatic defending line.
But electrostatic protection device the space occupied in the related technology is larger, is unfavorable for the reality of narrow frame display panel
It is existing.
Utility model content
The utility model provides a kind of array substrate and display device, and the array substrate that can be solved in the related technology needs
The problem of electrostatic protection device is set, the realization of narrow frame display panel is unfavorable for.Technical solution is as follows：
On the one hand, a kind of array substrate is provided, the array substrate includes：Underlay substrate, and be arranged in the lining
A plurality of signal wire on substrate；
There are at least one target signal line in a plurality of signal wire, at least one in the both sides of the target signal line
Side is provided with conductive electrode；
The conductive electrode insulate with other conductive structures in the array substrate, and the conductive electrode is described
Orthographic projection on underlay substrate is Chong Die with orthographic projection of the target signal line on the underlay substrate.
Optionally, it is provided with insulating layer between the conductive electrode and the target signal line；
The side closer or far from the underlay substrate in the target signal line is arranged in the conductive electrode.
Optionally, the conductive electrode includes multiple spaced electrode blocks, and the width of each electrode block is more than
The line width of the target signal line.
Optionally, multiple electrode blocks are equidistantly arranged along the extending direction of the target signal line.
Optionally, the width range in the gap between each two adjacent electrode block is 5 microns to 50 microns；
The length range of each electrode block is 10 microns to 50 microns；
The width range of each electrode block is 5 microns to 50 microns.
Optionally, the conductive electrode is strip shaped electric poles, the extending direction of the strip shaped electric poles and the target signal line
Extending direction it is parallel, and the width of the conductive electrode be more than the target signal line line width.
Optionally, orthographic projection of the conductive electrode on the underlay substrate is serpentine-like, the snakelike outsourcing rectangle
Width be more than the target signal line line width.
Optionally, orthographic projection of the axis that the conductive electrode extends in a first direction on the underlay substrate, with institute
Orthographic projection of the axis of target signal line on the underlay substrate is stated to overlap；
Wherein, the first direction is parallel with the extending direction of the target signal line.
Optionally, the array substrate further includes：Thin film transistor (TFT) on the underlay substrate is set；
The target signal line is grid line or grid line lead, the source-drain electrode of the conductive electrode and the thin film transistor (TFT)
Metal layer, active layer or the setting of shading metal layer same layer, and the conductive electrode and the conductive structure of same layer setting use together
Kind material is made.
Optionally, the array substrate further includes：Thin film transistor (TFT) on the underlay substrate is set；
The target signal line is data line or data cable lead wire, the grid of the conductive electrode and the thin film transistor (TFT)
Pole metal layer same layer setting, and the conductive electrode is made of material identical with the gate metal layer.
Optionally, the array substrate further includes：Thin film transistor (TFT) on the underlay substrate, the conductive electricity are set
Pole and the active layer same layer of the thin film transistor (TFT) are arranged；
When the thin film transistor (TFT) is amorphous silicon film transistor or oxide thin film transistor, the conductive electrode
Thickness range is 100 nanometers to 500 nanometers；
When the thin film transistor (TFT) is low-temperature polysilicon film transistor, the thickness range of the conductive electrode is received for 10
Rice is to 100 nanometers.
On the other hand, a kind of display device is provided, which is characterized in that the display device includes：
Array substrate as described in terms of above-mentioned.
The advantageous effect that technical solution provided by the utility model is brought is：
The utility model provides a kind of array substrate and display device, in the array substrate, at least one echo signal
At least side of line is provided with conductive electrode, when generating electrostatic on the target signal line, the target signal line and conduction electricity
Pole may be constructed capacitance, which has good antistatic protection function.Also, when the voltage of the target signal line is due to electrostatic
Accumulation and it is higher when, conductive path can be formed between the target signal line and conductive electrode, so as to discharge target in time
Electrostatic on signal wire.The utility model embodiment provide array substrate on without be arranged electrostatic protection device can be realized it is quiet
The function of electricity protection can occupy excessive space to avoid electrostatic protection device, be conducive to the realization of narrow frame display panel, and
The manufacturing cost of array substrate can be reduced.
Description of the drawings
It is required in being described below to embodiment in order to illustrate more clearly of the technical scheme in the embodiment of the utility model
Attached drawing to be used is briefly described, it should be apparent that, the accompanying drawings in the following description is only some realities of the utility model
Example is applied, it for those of ordinary skill in the art, without creative efforts, can also be according to these attached drawings
Obtain other attached drawings.
Fig. 1 is a kind of structural schematic diagram for array substrate that the utility model embodiment provides；
Fig. 2 is the structural schematic diagram for another array substrate that the utility model embodiment provides；
Fig. 3 is the structural schematic diagram for another array substrate that the utility model embodiment provides；
Fig. 4 is the structural schematic diagram for another array substrate that the utility model embodiment provides；
Fig. 5 is the structural schematic diagram for another array substrate that the utility model embodiment provides；
Fig. 6 is the structural schematic diagram for another array substrate that the utility model embodiment provides；
Fig. 7 is a kind of manufacturing method flow chart for array substrate that the utility model embodiment provides.
Specific implementation mode
It is new to this practicality below in conjunction with attached drawing to keep the purpose of this utility model, technical solution and advantage clearer
Type embodiment is described in further detail.
Fig. 1 is a kind of structural schematic diagram for array substrate that the utility model embodiment provides, with reference to figure 1, the array base
Plate may include：Underlay substrate 00, and a plurality of signal wire being arranged on the underlay substrate 00 (illustrate only one in Fig. 1
Signal wire 01).
May exist at least one target signal line 01 in a plurality of signal wire, in the both sides of the target signal line 01 extremely
Few side is provided with conductive electrode 11.Other conductive structures in the conductive electrode 11 and the array substrate (including believe by the target
Number line 01) insulate, and orthographic projection of the conductive electrode 11 on the underlay substrate 00 with the target signal line 01 in the substrate
Orthographic projection overlapping on substrate 00.
Wherein, the both sides of target signal line 01 can refer to the both sides up and down of target signal line 01, the i.e. target signal line
01 close to the side of underlay substrate 00 and the side of the target signal line 01 far from underlay substrate 00.The conductive electrode 11 can
Think that the hanging electrode in array substrate, the i.e. conductive electrode 11 are being served as a contrast independently of other conductive structures setting in array substrate
On substrate 00, and the conductive electrode 11 is not also connect with external electrode, external circuit or bonding pad (bonding pad).
In conclusion in the array substrate that the utility model embodiment provides, at least the one of at least one target signal line
Side is provided with conductive electrode, and when generating electrostatic on the target signal line, which may be constructed with the conductive electrode
Capacitance, the capacitance have good antistatic protection function.Also, when the voltage of the target signal line is higher due to accumulation of static electricity
When, conductive path can be formed between the target signal line and conductive electrode, so as in time will be quiet on target signal line
Electricity is discharged to conductive electrode.It is not necessary that electrostatic protection device is arranged in the array substrate provided due to the utility model embodiment
It realizes the function of electrostatic protection, excessive space can be occupied to avoid electrostatic protection device, be conducive to the reality of narrow frame display panel
It is existing, and the manufacturing cost of array substrate can be reduced.
Optionally, in the utility model embodiment, which can be arranged the non-display area in array substrate
Domain.
Fig. 2 is the structural schematic diagram for another array substrate that the utility model embodiment provides, with reference to figure 2, the conduction
Insulating layer 001 can be provided between electrode 11 and target signal line 01, to ensure effective insulation of the two.
The conductive electrode 11 can be arranged in target signal line 01 close to the side of the underlay substrate 00；Alternatively, such as Fig. 2 institutes
Show, which can also be arranged in the side of the target signal line 01 far from the underlay substrate 00.Only in echo signal
Conductive electrode 11 is arranged in the side of line 01, can avoid the system for increasing array substrate on the basis of ensureing antistatic protection function
Make the complexity of technique.
As a kind of optional realization method of the utility model embodiment, with reference to figure 1 and Fig. 2, which can be with
Including multiple spaced electrode block 11a, the width w1 of each electrode block 11a can be more than the line width of the target signal line 01
w2.It will be seen from figure 1 that the width direction of each electrode block 11a is parallel with the width direction of target signal line 01, i.e., and target
The extending direction of signal wire 01 is vertical.
The width of each electrode block 11a is arranged it is wider, can increase as possible each electrode block and target signal line it
Between overlapping region area, to both increase the capacity of the capacitance formed, and then increase the antistatic capacity of the capacitance.
Optionally, as depicted in figs. 1 and 2, multiple electrode block 11a can be along the extending direction etc. of the target signal line 01
Spacing arranges.Also, the width w3 in the gap between each two adjacent electrode block 11a may range from 5 microns to 50 it is micro-
Rice；The length w4's of each electrode block 11a may range from 10 microns to 50 microns；The model of the width w1 of each electrode block 11a
Enclosing can be 5 microns to 50 microns.
As another optional realization method of the utility model embodiment, with reference to figure 3, which may be
Strip shaped electric poles, the i.e. conductive electrode 11 can be the integral structure of strip.The extending direction X of the strip shaped electric poles 11 and the target
The extending direction of signal wire 01 is parallel, and the width w1 of the conductive electrode 11 can be more than the line width w2 of the target signal line 01,
To increase the area of the overlapping region between the conductive electrode and target signal line as possible, so as to increase the electricity that the two is formed
The antistatic capacity of appearance.Exemplary, the width w1's of the strip shaped electric poles 11 may range from 5 microns to 50 microns.
Another optional realization method as the utility model embodiment, with reference to figure 4, the conductive electrode 11 is in the substrate
Orthographic projection on substrate 00 can also be in the snakelike of bending.And the width w1 of the snakelike outsourcing rectangle (not shown) can be with
More than the line width w2 of the target signal line 01, it can similarly increase the overlapping region between the conductive electrode and target signal line
Area, the antistatic capacity of the capacitance formed both to increase.Exemplary, the width range of the snakelike outsourcing rectangle can
Think 10 microns to 50 microns
Wherein, the edge line of snakelike orthographic projection of the conductive electrode 11 on underlay substrate 00 can be the straight line of bending
(i.e. shown in Fig. 4), or may be camber line, the utility model embodiment does not limit this.
Further, with reference to figure 3, the conductive electrode 11 is along the axis that first direction X extends on the underlay substrate 00
Orthographic projection is overlapped with orthographic projection of the axis of the target signal line 01 on the underlay substrate 00.Wherein, first direction X with
The extending direction of the target signal line is parallel.
For example, in structure shown in Fig. 3, the axis of the conductive electrode 11 and the axis of target signal line 01 are serving as a contrast
Orthographic projection on substrate 00 is axis m.
By the way that conductive electrode 11 and target signal line 01 are coaxially arranged, it is ensured that the orthographic projection energy of conductive electrode 11
It is enough Chong Die with the orthographic projection of target signal line 01 compared with limits.
Optionally, which can also include：Thin film transistor (TFT) on underlay substrate 00 is set.
In an optional implementation manner, which can be grid line or grid line lead, conduction electricity
Pole 01 can be arranged with the source-drain electrode metal layer, active layer or shading metal layer same layer of the thin film transistor (TFT).And conduction electricity
The conductive structure that pole 01 can be arranged with same layer is made of same material.
For example, when the conductive electrode 01 and source-drain electrode metal layer or shading metal layer same layer are arranged, the conductive electrode
01, which may be used metal material, is made；When the conductive electrode 01 and active layer same layer are arranged, which may be used
Semi-conducting material is made.
Wherein, the metal material can be include molybdenum (Mo), molybdenum niobium alloy (MoNb), Al, aluminium neodymium alloy (AlNd), titanium
(Ti) and any one of copper (Cu)；The semi-conducting material may include non-crystalline silicon (amorphous silicon, a-Si), more
Crystal silicon or indium gallium zinc oxide (indium gallium zinc oxide, IGZO) etc..
It is exemplary, it is assumed that the target signal line 01 is grid line, which can be with the active layer of thin film transistor (TFT)
Same layer is arranged, then correspondingly, the insulating layer 001 being arranged between the conductive electrode 11 and target signal line 01 can be gate insulation
Layer.Also, as shown in Fig. 2, the side of the conductive electrode 11 far from underlay substrate 00 is also provided with passivation layer 002.
When the thin film transistor (TFT) is the thin film transistor (TFT) of bottom grating structure, as shown in Fig. 2, the conductive electrode 11 can be arranged
In side of the target signal line 01 far from underlay substrate 00；When the thin film transistor (TFT) is the thin film transistor (TFT) of top gate structure, such as
Shown in Fig. 5, which can be arranged in target signal line 01 close to the side of underlay substrate 00.Correspondingly, the conduction
Buffer layer 003 can be provided between electrode 11 and underlay substrate 00.
It should be noted that when the active layer same layer of the conductive electrode 11 and thin film transistor (TFT) is arranged, if film crystal
Pipe is amorphous silicon film transistor or oxide thin film transistor, then the thickness range of the conductive electrode 11 can be 100 nanometers
To 500 nanometers；When the thin film transistor (TFT) is that low temperature polycrystalline silicon (Low Temperature Poly-Silicon, LTPS) film is brilliant
When body pipe, the thickness range of the conductive electrode 11 can be 10 nanometers to 100 nanometers.Wherein, the thickness direction of conductive electrode 11
The surface that signal wire is provided with underlay substrate 00 is vertical.
In another optional realization method, which can also be data line or data cable lead wire,
The conductive electrode 11 can be arranged with the gate metal layer same layer of the thin film transistor (TFT), and may be used and the gate metal layer phase
Same material is made.
Also, according to the difference of the type of thin film transistor (TFT) in array substrate, the conductive electrode 11 and target signal line 01
Between the insulating layer that is arranged can be gate insulation layer, passivation layer or interlayer dielectric layer etc..Form the insulating materials of the insulating layer
May include silica, silicon nitride, aluminium oxide, hafnium oxide or molybdenum oxide etc..
It should be noted that as shown in fig. 6, when the broken line that the target signal line 01 is made of multiple signal line segments,
The extending direction (or orientation of the electrode block included by conductive electrode) of the conductive electrode 11 also can be with the echo signal
The variation of 01 extending direction of line and change.
In conclusion in the array substrate that the utility model embodiment provides, at least the one of at least one target signal line
Side is provided with conductive electrode, and when generating electrostatic on the target signal line, which may be constructed with the conductive electrode
Capacitance, the capacitance have good antistatic protection function.Also, when the voltage of the target signal line is higher due to accumulation of static electricity
When, conductive path can be formed between the target signal line and conductive electrode, so as to discharge on target signal line in time
Electrostatic.It is not necessary that the work(that electrostatic protection can be realized in electrostatic protection device is arranged in the array substrate that the utility model embodiment provides
Can, excessive space can be occupied to avoid electrostatic protection device, be conducive to the realization of narrow frame display panel, and battle array can be reduced
The manufacturing cost of row substrate.
The utility model embodiment additionally provides a kind of manufacturing method of array substrate, and with reference to figure 7, this method can wrap
It includes：
Step 101 forms a plurality of signal wire in underlay substrate.
Exemplary, the mode that magnetron sputtering may be used deposits one layer of metallic film on the surface of underlay substrate；Later may be used
To be patterned processing to the metallic film using a photoetching process, to obtain a plurality of signal wire.The metallic film
It can be the film layer formed by any one of Mo, MoNb, Al, AlNd, Ti and Cu material, or can be by above-mentioned material
Multiple material formed single-layer or multi-layer composite laminate.
In step 102, at least one target signal line in a plurality of signal wire, in the both sides of every target signal line
At least side formed conductive electrode.
The conductive electrode insulate with other conductive structures in the array substrate, and the conductive electrode is in the underlay substrate
On orthographic projection it is Chong Die with orthographic projection of the target signal line on the underlay substrate.
In the utility model embodiment, which can be formed by metal material, can also be by semi-conducting material
It is formed.
When the conductive electrode is formed by metal material, the mode that magnetron sputtering may be used is heavy on the surface of underlay substrate
One layer of metallic film of product；A photoetching process may be used later, processing is patterned to the metallic film, to be somebody's turn to do
Conductive electrode.
When the conductive electrode is formed by semi-conducting material, plasma enhanced chemical vapor deposition may be used
(Plasma Enhanced Chemical Vapor Deposition, PECVD) technique deposits one layer on the surface of underlay substrate
Semiconductor material thin film；A photoetching process may be used later, processing is patterned to the semiconductor material thin film, to
Obtain the conductive electrode.
It should be noted that the execution sequence of above-mentioned steps 101 and step 102 can be adjusted according to actual conditions,
I.e. step 102 can also execute before step 101, and the utility model embodiment does not limit this.
In the utility model embodiment, multiple thin film transistor (TFT)s can also be formed on the underlay substrate.
In an optional implementation manner, which can be grid line or grid line lead, then the conduction is electric
Extremely it can pass through a patterning processes same layer shape with the source-drain electrode metal layer, active layer or shading metal layer of thin film transistor (TFT)
At, and the conductive structure that the conductive electrode 01 can be formed with same layer is formed using same material.
In another optional realization method, which can be data line or data cable lead wire, this is led
Electrode can be formed with the gate metal layer of the thin film transistor (TFT) by a patterning processes same layer, and may be used and the grid
Metal layer identical material in pole is formed.
The utility model embodiment provides a kind of display device, which may include：As Fig. 1 to Fig. 6 is any
Shown in array substrate.The display device can be：Liquid crystal display panel, Electronic Paper, mobile phone, tablet computer, television set, display,
Any product or component with display function such as laptop, Digital Frame, navigator.
The above is only the preferred embodiment of the present invention, is not intended to limit the utility model, all in this practicality
Within novel spirit and principle, any modification, equivalent replacement, improvement and so on should be included in the guarantor of the utility model
Within the scope of shield.
Claims (12)
1. a kind of array substrate, which is characterized in that the array substrate includes：Underlay substrate, and be arranged in the substrate base
A plurality of signal wire on plate；
There are at least one target signal line in a plurality of signal wire, at least side in the both sides of the target signal line is set
It is equipped with conductive electrode；
The conductive electrode insulate with other conductive structures in the array substrate, and the conductive electrode is in the substrate
Orthographic projection on substrate is Chong Die with orthographic projection of the target signal line on the underlay substrate.
2. array substrate according to claim 1, which is characterized in that between the conductive electrode and the target signal line
It is provided with insulating layer；
The side closer or far from the underlay substrate in the target signal line is arranged in the conductive electrode.
3. array substrate according to claim 1, which is characterized in that the conductive electrode includes multiple spaced electricity
The width of pole block, each electrode block is more than the line width of the target signal line.
4. array substrate according to claim 3, which is characterized in that
Multiple electrode blocks are equidistantly arranged along the extending direction of the target signal line.
5. array substrate according to claim 4, which is characterized in that
The width range in the gap between each two adjacent electrode block is 5 microns to 50 microns；
The length range of each electrode block is 10 microns to 50 microns；
The width range of each electrode block is 5 microns to 50 microns.
6. array substrate according to claim 1, which is characterized in that the conductive electrode is strip shaped electric poles, the strip
The extending direction of electrode is parallel with the extending direction of the target signal line, and the width of the conductive electrode is more than the target
The line width of signal wire.
7. array substrate according to claim 1, which is characterized in that the conductive electrode on the underlay substrate just
Project serpentine-like, the width of the snakelike outsourcing rectangle is more than the line width of the target signal line.
8. array substrate according to any one of claims 1 to 7, which is characterized in that the conductive electrode prolongs along first direction
Orthographic projection of the axis stretched on the underlay substrate, with the positive throwing of the axis of the target signal line on the underlay substrate
Shadow overlaps；
Wherein, the first direction is parallel with the extending direction of the target signal line.
9. array substrate according to any one of claims 1 to 7, which is characterized in that the array substrate further includes：Setting exists
Thin film transistor (TFT) on the underlay substrate；
The target signal line is grid line or grid line lead, the source-drain electrode metal of the conductive electrode and the thin film transistor (TFT)
Layer, active layer or the setting of shading metal layer same layer, and the conductive electrode and the conductive structure of same layer setting use material of the same race
Material is made.
10. array substrate according to any one of claims 1 to 7, which is characterized in that the array substrate further includes：Setting
Thin film transistor (TFT) on the underlay substrate；
The target signal line is data line or data cable lead wire, the grid gold of the conductive electrode and the thin film transistor (TFT)
Belong to the setting of layer same layer, and the conductive electrode is made of material identical with the gate metal layer.
11. the array substrate according to any one of claims 1 to 7, which is characterized in that the array substrate is also wrapped
It includes：Thin film transistor (TFT) on the underlay substrate, the active layer same layer of the conductive electrode and the thin film transistor (TFT) are set
Setting；
When the thin film transistor (TFT) is amorphous silicon film transistor or oxide thin film transistor, the thickness of the conductive electrode
Ranging from 100 nanometers to 500 nanometers；
When the thin film transistor (TFT) is low-temperature polysilicon film transistor, the thickness range of the conductive electrode be 10 nanometers extremely
100 nanometers.
12. a kind of display device, which is characterized in that the display device includes：
Array substrate as described in claim 1 to 11 is any.
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| CN201820396778.2U CN207896092U (en) | 2018-03-22 | 2018-03-22 | array substrate and display device |
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| CN201820396778.2U CN207896092U (en) | 2018-03-22 | 2018-03-22 | array substrate and display device |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109377874A (en) * | 2018-12-21 | 2019-02-22 | 上海中航光电子有限公司 | Display panel and display device |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109377874A (en) * | 2018-12-21 | 2019-02-22 | 上海中航光电子有限公司 | Display panel and display device |
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