CN207852644U - Semiconductor structure - Google Patents
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- CN207852644U CN207852644U CN201721470663.5U CN201721470663U CN207852644U CN 207852644 U CN207852644 U CN 207852644U CN 201721470663 U CN201721470663 U CN 201721470663U CN 207852644 U CN207852644 U CN 207852644U
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- semiconductor
- semiconductor structure
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 113
- 229910052751 metal Inorganic materials 0.000 claims abstract description 113
- 239000002184 metal Substances 0.000 claims abstract description 113
- 239000000758 substrate Substances 0.000 claims abstract description 69
- 229910052782 aluminium Inorganic materials 0.000 claims description 11
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 claims description 11
- 239000003990 capacitor Substances 0.000 claims description 11
- 239000000463 material Substances 0.000 claims description 11
- 239000004411 aluminium Substances 0.000 claims description 9
- 239000010936 titanium Substances 0.000 claims description 5
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 claims description 4
- NRTOMJZYCJJWKI-UHFFFAOYSA-N Titanium nitride Chemical compound [Ti]#N NRTOMJZYCJJWKI-UHFFFAOYSA-N 0.000 claims description 4
- 229910052719 titanium Inorganic materials 0.000 claims description 4
- 238000002955 isolation Methods 0.000 claims description 3
- 239000004020 conductor Substances 0.000 claims description 2
- 238000010992 reflux Methods 0.000 abstract description 39
- 238000000034 method Methods 0.000 abstract description 15
- 238000002310 reflectometry Methods 0.000 abstract description 11
- 230000008569 process Effects 0.000 abstract description 8
- 230000005012 migration Effects 0.000 abstract description 5
- 238000013508 migration Methods 0.000 abstract description 5
- 238000001953 recrystallisation Methods 0.000 abstract description 5
- 239000010410 layer Substances 0.000 description 123
- 238000000151 deposition Methods 0.000 description 11
- 238000011049 filling Methods 0.000 description 8
- 238000002360 preparation method Methods 0.000 description 8
- 230000008021 deposition Effects 0.000 description 6
- 238000010586 diagram Methods 0.000 description 5
- 238000005240 physical vapour deposition Methods 0.000 description 5
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 4
- 238000012986 modification Methods 0.000 description 3
- 230000004048 modification Effects 0.000 description 3
- 238000004062 sedimentation Methods 0.000 description 3
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 2
- 229910002601 GaN Inorganic materials 0.000 description 2
- JMASRVWKEDWRBT-UHFFFAOYSA-N Gallium nitride Chemical compound [Ga]#N JMASRVWKEDWRBT-UHFFFAOYSA-N 0.000 description 2
- 230000008859 change Effects 0.000 description 2
- 238000005229 chemical vapour deposition Methods 0.000 description 2
- 238000001816 cooling Methods 0.000 description 2
- 229910052802 copper Inorganic materials 0.000 description 2
- 239000010949 copper Substances 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 2
- 239000010931 gold Substances 0.000 description 2
- 229910052737 gold Inorganic materials 0.000 description 2
- 239000011229 interlayer Substances 0.000 description 2
- 229910052594 sapphire Inorganic materials 0.000 description 2
- 239000010980 sapphire Substances 0.000 description 2
- 239000000377 silicon dioxide Substances 0.000 description 2
- 229910052774 Proactinium Inorganic materials 0.000 description 1
- 230000004075 alteration Effects 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 230000019771 cognition Effects 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 230000007812 deficiency Effects 0.000 description 1
- 238000007872 degassing Methods 0.000 description 1
- 230000005484 gravity Effects 0.000 description 1
- 238000002386 leaching Methods 0.000 description 1
- 238000003701 mechanical milling Methods 0.000 description 1
- 238000010943 off-gassing Methods 0.000 description 1
- 230000035484 reaction time Effects 0.000 description 1
- 230000009467 reduction Effects 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
Landscapes
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
The utility model provides a kind of semiconductor structure, and semiconductor structure includes：Semiconductor substrate is formed with groove in semiconductor substrate；And reflow metal layer, it is filled in the groove.The utility model is by carrying out high temperature reflux processing after deposited metal layer in the trench, metal layer can at reflux from the opening of the groove to the flows of the groove, to the groove is filled up and is ensured in the metal layer being filled in groove will not hole presence；Meanwhile high temperature reflow processes can allow metallic atom recrystallization to form the higher high-quality reflow metal layer of reflectivity, to enhance the electric migration performance and service life of semiconductor devices.
Description
Technical field
The utility model belongs to semiconductor preparing process technical field, more particularly to a kind of semiconductor structure.
Background technology
The use of the metal layers such as physical gas-phase deposition (PVD) deposition of aluminum film is many half in existing semiconductor technology
Necessary step in semiconductor process.In existing technique, one is heated to generally by wafer to be placed in vacuum reaction room
Constant temperature degree, the step process deposited using sputtering method.
However, deepening continuously with device miniaturization, the size of semiconductor structure is smaller and smaller, especially works as semiconductor
When the critical dimension reduction of product is to 30nm or less, causes to fill groove and the difficulty of through-hole is increasing.Using existing
When the groove 10 (for example contact hole) that depositing operation carries out high-aspect-ratio carries out metal layer 11 (for example aluminium layer) filling, it is easy to make
The groove 10 cannot be filled up (as shown in Figure 1, between 11 inside of the metal layer in the groove 10 has by obtaining the metal layer 11
Gap 12) or hole 12 is formed in the interior metal layer 11 filled of the groove 10, and if the metal layer 11 cannot be filled out
Expiring the groove 10 or being filled in the metal layer 11 in the groove 10 has the presence of described hole 12, inevitably results in half
The decline of conductor device performance even results in the failure of semiconductor devices.
Utility model content
In view of the foregoing deficiencies of prior art, the purpose of this utility model is to provide a kind of semiconductor structures, use
Hole can be formed in solving the when of being filled in the prior art into row metal to groove using existing depositing operation in the metal layer of filling
The problem of hole declines so as to cause performance of semiconductor device, even results in semiconductor device failure.
In order to achieve the above objects and other related objects, the utility model provides a kind of semiconductor structure preparation method, institute
The preparation method for stating semiconductor structure includes the following steps：
1) semi-conductive substrate is provided, groove is formed in the semiconductor substrate；
2) in the groove and the semiconductor substrate upper surface deposited metal layer；And
3) metal layer is carried out the high temperature reflux under vacuum environment to handle so that reflux occurs for the metal layer with shape
The groove is filled up at reflow metal layer.
Further include step between step 1) and step 2) as a kind of preferred embodiment of the utility model：It is partly led described
Body substrate is heated, to remove the semiconductor substrate surface steam.
Further include step between step 1) and step 2) as a kind of preferred embodiment of the utility model：Form soakage layer
In the upper surface of the semiconductor substrate, the bottom of the groove and side wall, step 2), the deposition of metal is in the leaching
Moisten the outer surface of layer.
As a kind of preferred embodiment of the utility model, the metal layer formed in step 2) includes aluminium layer.
As a kind of preferred embodiment of the utility model, in step 1), the quantity of the groove in the semiconductor substrate
To be multiple, multiple grooves are intervally arranged in the semiconductor substrate.
As a kind of preferred embodiment of the utility model, in step 3), always persistently removed in high temperature reflux processing procedure
Gas.
As a kind of preferred embodiment of the utility model, in step 2), using physical gas-phase deposition in the groove
Interior and described semiconductor substrate upper surface deposits the metal layer.
As a kind of preferred embodiment of the utility model, the depositing temperature of the metal layer is described less than or equal to 100 DEG C
The thickness of metal layer is 5000 angstroms~6000 angstroms, and sedimentation time is 1 minute~5 minutes.
Further include following steps after step 3) as a kind of preferred embodiment of the utility model：
4) by high temperature reflux, treated that the semiconductor substrate is cooled to room temperature；And
5) the reflow metal layer of the removal positioned at the semiconductor substrate upper surface.
As a kind of preferred embodiment of the utility model, in step 3), in the groove and upper surface is formed with described
The semiconductor substrate of metal layer is placed in vacuum reaction chamber room, and high temperature is carried out under the conditions of the reaction temperature more than 400 DEG C
Processing, so that reflux occurs for the metal layer fills up the groove to form the reflow metal layer.
As a kind of preferred embodiment of the utility model, the reaction temperature is 440 DEG C~550 DEG C, the reaction time
It it is 30 seconds~180 seconds, the indoor vacuum degree of vacuum reaction chamber is more than 10-8Pa。
The utility model also provides a kind of semiconductor structure, and the semiconductor structure includes：
Semiconductor substrate is formed with groove in the semiconductor substrate；And
Reflow metal layer is filled in the groove.
As a kind of preferred embodiment of the utility model, the material of the reflow metal layer includes aluminium.
As a kind of preferred embodiment of the utility model, upper surface and the semiconductor substrate of the reflow metal layer
Upper surface flush.
As a kind of preferred embodiment of the utility model, the depth-to-width ratio of the groove is less than or equal to 2.
As a kind of preferred embodiment of the utility model, the semiconductor structure further includes soakage layer, is located at the groove
It is interior, using as the combination liner between the reflow metal layer and the semiconductor substrate.
As a kind of preferred embodiment of the utility model, the material of the soakage layer include titanium or titanium nitride wherein it
One.
As a kind of preferred embodiment of the utility model, the bottom of the semiconductor substrate is equipped with transistor arrangement, described
Transistor arrangement has grid structure, and the semiconductor structure further includes：
Capacitor arrangement is located in the semiconductor substrate；
Wherein, the reflow metal layer is between the capacitor arrangement and the transistor arrangement, the reflux gold
Belong to the multiple node contacts of layer staged isolation layer, is leaked by by grid structure switch startup with being electrically connected the transistor arrangement
The lower electrode of polar region and the capacitor arrangement.
As described above, the utility model semiconductor structure, has the advantages that：The utility model passes through in the trench
High temperature reflux processing is carried out after deposited metal layer, metal layer can be at reflux from the opening of the groove to the groove
Flows, to the groove is filled up and is ensured in the metal layer being filled in groove will not hole presence；Together
When, high temperature reflow processes can allow metallic atom recrystallization to form the higher high-quality reflow metal layer of reflectivity, after reflux
The reflectivity of the reflow metal layer of formation can reach twice of the reflectivity of the preceding metal layer of reflux, to enhance semiconductor devices
Electric migration performance and service life.
Description of the drawings
Metal layer fails to fill up the structural schematic diagram of groove when Fig. 1 is shown as filling groove in the prior art.
Fig. 2 is shown as the structural representation of hole in the metal layer being filled in groove when filling groove in the prior art
Figure.
Fig. 3 is shown as the flow chart of the preparation method of the semiconductor structure provided in the utility model embodiment one.
Fig. 4 to Fig. 8 is shown as each step in the preparation method of the semiconductor structure provided in the utility model embodiment one
Corresponding structural schematic diagram, wherein Fig. 8 is a kind of topology example of the semiconductor structure of the utility model.
Fig. 9 is shown as a kind of structural schematic diagram of the semiconductor structure provided in the utility model embodiment two.
Component label instructions
10 grooves
11 metal layers
12 gaps
13 holes
20 semiconductor substrates
21 grooves
22 soakage layers
23 metal layers
24 reflow metal layers
25 transistor arrangements
251 grid structures
252 drain regions
26 capacitor arrangements
261 times electrodes
S1~S3 steps 1)~step 3)
Specific implementation mode
Illustrate that the embodiment of the utility model, those skilled in the art can be by this theorys below by way of specific specific example
Content disclosed by bright book understands other advantages and effect of the utility model easily.The utility model can also be by addition
Different specific implementation modes are embodied or practiced, and the various details in this specification can also be based on different viewpoints and answer
With carrying out various modifications or alterations under the spirit without departing from the utility model.
Fig. 3 is please referred to Fig. 9.It should be noted that the diagram provided in the present embodiment only illustrates this in a schematic way
The basic conception of utility model, though when only display is with related component in the utility model rather than according to actual implementation in diagram
Component count, shape and size are drawn, when actual implementation form, quantity and the ratio of each component can be a kind of random change
Become, and its assembly layout form may also be increasingly complex.
Embodiment one
Referring to Fig. 3, the utility model provides a kind of preparation method of semiconductor structure, the preparation of the semiconductor structure
Method includes the following steps：
1) semi-conductive substrate is provided, groove is formed in the semiconductor substrate；
2) in the groove and the semiconductor substrate upper surface deposited metal layer；And
3) metal layer is carried out the high temperature reflux under vacuum environment to handle so that reflux occurs for the metal layer with shape
The groove is filled up at reflow metal layer.
In step 1), S1 steps and Fig. 4 in Fig. 3 are please referred to, semi-conductive substrate 20, the semiconductor substrate are provided
Groove 21 is formed in 20.
As an example, the semiconductor substrate 20 can be described can arbitrarily to be formed known to ordinary skill
The semiconductor structure that groove 21 and the groove 21 needs are filled can be formed such as the interlayer dielectric layer of semiconductor devices
The groove 21 forms electric connection structure (for example, conductive plugs), using the interconnection structure as upper and lower device layer after filling.Institute
Stating the material of semiconductor substrate 20 can be but be not limited to silica, gallium nitride or sapphire etc..
As an example, the quantity of the groove 21 formed in the semiconductor substrate 20 can be multiple, it is multiple described
Groove 21 is intervally arranged in the semiconductor substrate 20.Between multiple grooves 21 can wait in the semiconductor substrate 20
It, can also non-equidistant arrangement away from being intervally arranged.Only to be formed in the semiconductor substrate 20, there are one the grooves 21 to make by Fig. 4
Actual quantity for example, the groove 21 is not limited.
As an example, the cross sectional shape of the groove 21 can be set according to actual needs, it is preferable that the present embodiment
In, the cross sectional shape of the groove 21 can be the arbitrary shape that filling may be implemented such as rectangle, trapezoidal, U-shaped.
As an example, the depth-to-width ratio of the groove 21 can be set according to actual needs, it is preferable that the present embodiment
In, the depth-to-width ratio of the groove 21 is less than or equal to 2.
As an example, further including following steps after step 1)：The semiconductor substrate 20 is heated, to remove
State the steam on 20 surface of semiconductor substrate.Specifically, the semiconductor substrate 20 can be placed in high volatile material processing
(Degas) reative cell is heated, to remove the steam on 20 surface of the semiconductor substrate.
Further include following steps as an example, as shown in figure 5, after removing the steam on 20 surface of the semiconductor substrate：
Soakage layer is formed in the upper surface of the semiconductor substrate 20, the bottom of the groove 21 and side wall.Specifically, object may be used
Physical vapor deposition technique (PVD) or chemical vapor deposition method (CVD) form the soakage layer 22.The material of the soakage layer 22
Can be titanium (Ti) or titanium nitride (TiN) etc..
In step 2), S2 steps and Fig. 6 in Fig. 3 are please referred to, in the groove 21 and the semiconductor substrate 20
Upper surface deposited metal layer 23.
As an example, physical gas-phase deposition may be used in the groove 21 and 20 upper table of semiconductor substrate
Face deposits the metal layer 23, wherein the depositing temperature of the metal layer 23 is less than or equal to 100 DEG C, i.e., in less than or equal to
It uses physical gas-phase deposition in the groove 21 at a temperature of 100 DEG C and 20 upper surface of semiconductor substrate deposits institute
State metal layer 23.Preferably, in the present embodiment, depositing temperature is 25 DEG C~100 DEG C.
As an example, the metal layer 23 may include but be not limited only to aluminium layer, the metal layer 23 can be undoped
Aluminum layer, or doped with the aluminium layer of some modifying elements.Certainly, in other examples, the metal layer 23 may be used also
Think other metal layers such as copper.
As an example, the thickness of the metal layer 23 can be set according to the depth of the groove 21, it is preferable that this
In embodiment, the thickness of the metal layer 23 can be but be not limited only to 5000 angstroms~6000 angstroms, using physical vapour deposition (PVD) work
Skill is in the groove 21 and sedimentation time that 20 upper surface of semiconductor substrate deposits the metal layer 23 can be but not
It is only limitted to 1 minute~5 minutes.Certainly, in other examples, the thickness of the metal layer 23 and sedimentation time can also be according to realities
Border needs to be adjusted, but it is described to should be noted that the metal layer 23 deposited in the step can should at least fill up substantially
Groove 21, to ensure that the reflow metal layer formed after subsequent high temperature reflux technique can fill up the groove 21.
In step 3), S3 steps and Fig. 7 in Fig. 3 are please referred to, the metal layer 23 is subjected to the height under vacuum environment
Warm reflow treatment so that the metal layer 23 occurs reflux and fills up the groove 21 to form reflow metal layer 24.
As an example, in the groove 21 and upper surface can be formed with to the semiconductor substrate of the metal layer 23
20 (structures that i.e. step 2) obtains) are placed in a vacuum reaction chamber room, to step under the conditions of the reaction temperature more than 400 DEG C
2) structure obtained carries out high-temperature process, so that reflux occurs for the metal layer 23 to form the reflow metal layer 24
Fill up the groove 21.When being handled under the conditions of the reaction temperature more than 400 DEG C, the metal layer 23 is in the hot conditions
Lower can have a mobility (for example, dissolve etc.), the atom of the metal layer 23 with mobility understand under the effect of gravity from
The opening at 21 top of the groove flows back to the bottom of the groove 21, and the direction of the arrow in Fig. 7 indicates the metal layer
The directions of 23 reflux, so that the groove 21 be filled up, due to during reflux, the gas such as air in the metal layer 23
Cognition is discharged, and then may insure to be filled in will not hole in the reflow metal layer 24 in the groove 21.Meanwhile
High temperature reflow processes can make the recrystallization of the metallic atom in the metal layer 23 be returned to form the higher high-quality of reflectivity
Metal layer is flowed, the reflectivity of the reflow metal layer 24 formed after reflux can reach the reflection of the metal layer 23 before reflux
Twice of rate, to enhance the electric migration performance and service life of semiconductor devices.
As an example, the reaction temperature of high temperature reflux processing is preferably 440 DEG C~550 DEG C, certainly, in other examples,
The reaction temperature of high temperature reflux processing can also be set as other temperature values according to actual needs.
As an example, the time of high temperature reflux processing can be set according to actual needs, it is preferable that the present embodiment
In, the time of high temperature reflux processing can be 30 seconds~180 seconds.
As an example, the indoor vacuum degree of vacuum reaction chamber should reach certain numerical value, after further ensuring that reflux
Hole will not be formed by being filled in the reflow metal layer 24 in the groove 21.Preferably, in the present embodiment, the vacuum
The indoor vacuum degree of reaction chamber should be at least more than 10-8Pa, i.e., the described indoor pressure of vacuum reaction chamber should be at least below 10- 8Pa。
As an example, can also continue during the metal layer 23 is carried out the high temperature reflux processing under vacuum environment
Carry out degasification (outgassing).
As an example, further including following steps after step 3)：
4) by high temperature reflux, treated that the semiconductor substrate 20 is cooled to room temperature；And
5) the reflow metal layer 24 of the removal positioned at 20 upper surface of the semiconductor substrate.
As an example, in step 4), by step 3) treated the semiconductor substrate 20 from the vacuum reaction chamber
After interior taking-up, the mode that natural cooling may be used is cooled to room temperature, and the pressure of other cooling methods air-cooled can also be waited to be cooled to
Room temperature.
As an example, step) in 5, may be used but be not limited only to chemical mechanical milling tech (CMP) removal be located at it is described
The reflow metal layer 24 of 20 upper surface of semiconductor substrate so that the reflow metal layer 24 of reservation is respectively positioned on the groove
In 21.Finally obtained structure as shown in figure 8, the reflow metal layer 24 being filled in the groove 21 upper surface and institute
State the upper surface flush of semiconductor substrate 20.In finally obtained structure, the reflux being filled in the groove 21 is golden
Belonging to layer 24 can be as the conductive plugs between connection different components or different conductive metal layers.
Embodiment two
Please continue to refer to Fig. 8, the utility model also provides a kind of semiconductor structure, wherein the semiconductor structure can be with
To be prepared using the preparation method of the semiconductor structure described in embodiment one, the semiconductor structure includes：Partly lead
Body substrate 20 and reflow metal layer 24 are formed with groove 21 in the semiconductor substrate 20；The reflow metal layer 24 is filled in
In the groove 21.
As an example, the reflow metal layer 24 is to pass through height after deposited metal layer in the groove 21 in embodiment one
Warm reflow treatment and obtain, in the reflow metal layer 24 will not hole presence；Meanwhile in the reflow metal layer 24
The process that metallic atom is handled in high temperature reflux always has occurred and that recrystallization, the reflectivity of the reflow metal layer 24 can reach
Twice of the reflectivity of metal layer before reflux, to enhance the electric migration performance and service life of semiconductor devices.
As an example, the semiconductor substrate 20 can be described can arbitrarily to be formed known to ordinary skill
The semiconductor structure that groove 21 and the groove 21 needs are filled can be formed such as the interlayer dielectric layer of semiconductor devices
The groove 21 forms electric connection structure (for example, conductive plugs), using the interconnection structure as upper and lower device layer after filling.Institute
Stating the material of semiconductor substrate 20 can be but be not limited to silica, gallium nitride or sapphire etc..
As an example, the quantity of the groove 21 formed in the semiconductor substrate 20 can be multiple, it is multiple described
Groove 21 is intervally arranged in the semiconductor substrate 20.Between multiple grooves 21 can wait in the semiconductor substrate 20
It, can also non-equidistant arrangement away from being intervally arranged.Only to be formed in the semiconductor substrate 20, there are one the grooves 21 to make by Fig. 4
Actual quantity for example, the groove 21 is not limited.
As an example, the cross sectional shape of the groove 21 can be set according to actual needs, it is preferable that the present embodiment
In, the cross sectional shape of the groove 21 can be the arbitrary shape that filling may be implemented such as rectangle, trapezoidal, U-shaped.
As an example, the depth-to-width ratio of the groove 21 can be set according to actual needs, it is preferable that the present embodiment
In, the depth-to-width ratio of the groove 21 is less than or equal to 2.
As an example, the material of the reflow metal layer 24 includes aluminium, can be undoped fine aluminium, or mix
The miscellaneous aluminium for having some modifying elements.Certainly, in other examples, the material of the reflow metal layer 24 can also be copper etc. other
Metal.
As an example, the upper surface flush of the upper surface of the reflow metal layer 24 and the semiconductor substrate 21.
As an example, the semiconductor structure further includes soakage layer 22, the soakage layer 22 is located in the groove 21, with
As the combination liner between the reflow metal layer 24 and the semiconductor substrate 20.
As an example, the material of the soakage layer 22 may include titanium or titanium nitride etc..
As an example, as shown in figure 9, the bottom of the semiconductor substrate is equipped with transistor arrangement 25, the transistor junction
Structure 25 has grid structure 251, and the semiconductor structure further includes：Capacitor arrangement 26, the capacitor arrangement 26 are located at described
In semiconductor substrate 20；Wherein, the reflow metal layer 24 be located at the capacitor arrangement 26 and the transistor arrangement 25 it
Between, 24 staged isolation of reflow metal layer is at multiple node contacts, to be electrically connected the transistor arrangement 25 by by described
Grid structure 251 opens the lower electrode 261 of the drain region 252 and the capacitor arrangement 26 that start.
In conclusion the utility model provides a kind of semiconductor structure, the preparation method of the semiconductor structure includes such as
Lower step：1) semi-conductive substrate is provided, groove is formed in the semiconductor substrate；2) in described leading in the groove and partly
Body substrate upper surface deposited metal layer；And 3) handle the high temperature reflux under metal layer progress vacuum environment so that it is described
Metal layer occurs reflux and fills up the groove to form reflow metal layer.After the utility model is by deposited metal layer in the trench
Carry out high temperature reflux processing, metal layer can at reflux from the opening of the groove to the flows of the groove,
To the groove is filled up and is ensured in the metal layer being filled in groove will not hole presence；Meanwhile high temperature reflux
Technique can allow metallic atom recrystallization to form the higher high-quality reflow metal layer of reflectivity, the reflux gold formed after reflux
The reflectivity of category layer can reach twice of the reflectivity of the preceding metal layer of reflux, to enhance the electric migration performance of semiconductor devices
And service life.
The above embodiments are only illustrative of the principle and efficacy of the utility model, new not for this practicality is limited
Type.Any person skilled in the art can all carry out above-described embodiment under the spirit and scope without prejudice to the utility model
Modifications and changes.Therefore, such as those of ordinary skill in the art without departing from the revealed essence of the utility model
All equivalent modifications completed under refreshing and technological thought or change, should be covered by the claim of the utility model.
Claims (6)
1. a kind of semiconductor structure, which is characterized in that the semiconductor structure includes：
Semiconductor substrate is formed with groove in the semiconductor substrate；
Reflow metal layer is filled in the groove；And
Soakage layer is located in the groove, using as the engagement liner between the reflow metal layer and the semiconductor substrate.
2. semiconductor structure according to claim 1, which is characterized in that the material of the reflow metal layer includes aluminium.
3. semiconductor structure according to claim 1, which is characterized in that the upper surface of the reflow metal layer and described half
The upper surface flush of conductor substrate.
4. semiconductor structure according to claim 1, which is characterized in that the depth-to-width ratio of the groove is less than or equal to 2.
5. semiconductor structure according to claim 1, which is characterized in that the material of the soakage layer includes titanium and titanium nitride
One of.
6. semiconductor structure according to any one of claim 1 to 5, which is characterized in that the bottom of the semiconductor substrate
Portion is equipped with transistor arrangement, and the transistor arrangement further includes with grid structure, the semiconductor structure：
Capacitor arrangement is located in the semiconductor substrate；
Wherein, the reflow metal layer is between the capacitor arrangement and the transistor arrangement, the reflow metal layer
Staged isolation is at multiple node contacts, to be electrically connected the transistor arrangement by the drain area started by grid structure switch
With the lower electrode of the capacitor arrangement.
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201721470663.5U CN207852644U (en) | 2017-11-07 | 2017-11-07 | Semiconductor structure |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201721470663.5U CN207852644U (en) | 2017-11-07 | 2017-11-07 | Semiconductor structure |
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| Publication Number | Publication Date |
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| CN207852644U true CN207852644U (en) | 2018-09-11 |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107946233A (en) * | 2017-11-07 | 2018-04-20 | 睿力集成电路有限公司 | Semiconductor structure and preparation method thereof |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107946233A (en) * | 2017-11-07 | 2018-04-20 | 睿力集成电路有限公司 | Semiconductor structure and preparation method thereof |
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