CN115881522A

CN115881522A - Filling method of groove

Info

Publication number: CN115881522A
Application number: CN202211511647.1A
Authority: CN
Inventors: 朱朕; 金立培; 陈辰; 侯照海
Original assignee: Hua Hong Semiconductor Wuxi Co Ltd
Current assignee: Hua Hong Semiconductor Wuxi Co Ltd
Priority date: 2022-11-29
Filing date: 2022-11-29
Publication date: 2023-03-31

Abstract

The application discloses a filling method of a groove, which comprises the following steps: placing a wafer on a vacuum chuck of a CVD machine table, wherein the wafer is used for integrating a groove type MOS device, a groove is formed on the wafer, oxide layers are formed on the surfaces of the wafer and the groove, and the vacuum chuck is arranged in a reaction chamber of the CVD machine table; carrying out preheating treatment on the wafer, wherein the pressure value in a reaction chamber of a CVD machine table is a first pressure value when carrying out preheating treatment; vacuumizing a reaction chamber of the CVD machine table, starting a vacuum adsorption function of a vacuum chuck, and increasing a pressure value in the reaction chamber of the CVD machine table to a second pressure value; carrying out vacuum pumping treatment on a reaction chamber of the CVD machine; increasing the pressure value in the reaction chamber of the CVD machine table to a third pressure value, wherein the third pressure value is larger than the second pressure value; a silicon dioxide layer is deposited on the wafer by a CVD process. This application carries out stress release preliminary treatment back to the wafer through vacuum chuck, can effectively increase the adsorption efficiency of sucking disc, makes wafer and sucking disc closely laminate.

Description

Filling method of groove

Technical Field

The application relates to the technical field of semiconductor integrated circuit manufacturing, in particular to a filling method of a groove.

Background

Metal-oxide-semiconductor field-effect transistors (MOSFETs, referred to herein as "MOS") devices are electronic devices used in analog and digital circuits.

Among them, trench MOS (trench MOS) devices have lower on-resistance and gate-drain charge density, thus lower conduction and switching loss, and faster switching speed, and are generally widely used as power devices (also referred to as "electronic power devices") in the fields of consumer electronics, new energy vehicles, servers, control equipment, and the like. In the trench type MOS device, a Shield Gate (SGT) MOS device has a lower switching loss and can be used as a core power control component.

As the size of semiconductor devices is getting smaller, when the critical dimension (μm) of the trench of the SGT MOS device is smaller than 0.5 μm, the trench may be filled with a silicon dioxide layer by a high aspect ratio chemical vapor deposition (HARP CVD) process to overcome the phenomenon of early closing at the trench opening during the growth process.

With the reduction of the critical dimension of the SGT MOS device, the depth of the trench is increased, the influence of the warpage (bow) of the wafer on the device is increased, and when the warpage of the wafer is high, the temperature of the edge is low due to insufficient adhesion between the edge of the wafer and the heating device during the CVD process, which easily causes the problem of thick thickness of the edge during the process. In view of the above, a trench filling method is needed to solve the problem of the wafer edge thickness after CVD process due to the large warpage of the wafer.

Disclosure of Invention

The application provides a trench filling method, which can solve the problem that the uniformity of a device product is influenced by the fact that the warpage of a wafer is large in a manufacturing method of a trench type MOS device in the related art, and comprises the following steps:

placing a wafer on a vacuum chuck of a CVD machine table, wherein the wafer is used for integrating a groove type MOS device, a groove is formed on the wafer, oxide layers are formed on the surfaces of the wafer and the groove, and the vacuum chuck is arranged in a reaction chamber of the CVD machine table;

carrying out preheating treatment on the wafer, wherein the pressure value in a reaction chamber of the CVD machine table is a first pressure value during the preheating treatment;

vacuumizing the reaction chamber of the CVD machine, starting the vacuum adsorption function of the vacuum chuck,

increasing the pressure value in the reaction chamber of the CVD machine table to a second pressure value;

vacuumizing a reaction chamber of the CVD machine table;

increasing the pressure value in the reaction chamber of the CVD machine table to a third pressure value, wherein the third pressure value is larger than the second pressure value;

a silicon dioxide layer is deposited on the wafer by a CVD process.

In some embodiments, the pre-heating the wafer comprises:

increasing the pressure value in the reaction chamber of the CVD machine table to the first pressure value;

and jacking the wafer from the vacuum chuck, carrying out preheating treatment, and lowering the wafer down and placing the wafer back to the vacuum chuck after the preheating treatment is finished.

In some embodiments, the first pressure value is greater than the second pressure value and less than the third pressure value.

In some embodiments, the depositing a silicon dioxide layer on the wafer by a CVD process comprises:

depositing the silicon dioxide layer on the wafer by a HARP CVD process.

In some embodiments, the trench MOS device is an SGT MOS device.

In some embodiments, the warpage of the wafer is greater than 50 microns.

In some embodiments, the oxide layer is formed by a furnace oxidation process.

The technical scheme at least comprises the following advantages:

in the manufacturing process of the groove type MOS device, after the groove and the oxide layer on the surface of the groove are formed, the wafer in the CVD machine table is subjected to preheating treatment, and after the wafer is subjected to stress release pretreatment through the vacuum chuck, the CVD process is performed, so that the adsorption capacity of the chuck can be effectively increased, the wafer and the chuck are tightly attached, the temperature difference of the wafer in the CVD process is reduced, and the uniformity of the CVD process is improved.

Drawings

In order to more clearly illustrate the detailed description of the present application or the technical solutions in the prior art, the drawings needed to be used in the detailed description of the present application or the prior art description will be briefly introduced below, and it is obvious that the drawings in the following description are some embodiments of the present application, and other drawings can be obtained by those skilled in the art without creative efforts.

Fig. 1 is a flowchart of a method for filling a trench according to an exemplary embodiment of the present application;

FIG. 2 is a cross-sectional view of a wafer placed on a vacuum chuck;

FIG. 3 is a schematic cross-sectional view of a wafer after being lifted from a vacuum chuck;

fig. 4 is a schematic cross-sectional view after stress relief.

Detailed Description

The technical solutions in the present application will be described clearly and completely with reference to the accompanying drawings, and it is obvious that the described embodiments are some, but not all embodiments of the present application. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.

In the description of the present application, it should be noted that the terms "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer", and the like indicate orientations or positional relationships based on the orientations or positional relationships shown in the drawings, and are only for convenience of description and simplicity of description, and do not indicate or imply that the device or element being referred to must have a particular orientation, be constructed and operated in a particular orientation, and thus, should not be construed as limiting the present application. Furthermore, the terms "first," "second," and "third" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance.

In the description of the present application, it should be noted that, unless otherwise explicitly stated or limited, the terms "mounted," "connected," and "connected" are to be construed broadly, and may be, for example, a fixed connection, a detachable connection, or an integral connection; the connection can be mechanical connection or electrical connection; the two elements may be directly connected or indirectly connected through an intermediate medium, or may be communicated with each other inside the two elements, or may be wirelessly connected or wired connected. The specific meaning of the above terms in the present application can be understood in a specific case by those of ordinary skill in the art.

In addition, the technical features mentioned in the different embodiments of the present application described below may be combined with each other as long as they do not conflict with each other.

Referring to fig. 1, which shows a flowchart of a method for filling a trench according to an exemplary embodiment of the present application, the method may be applied to a process for manufacturing a trench MOS device (which may be an SGT MOS device), as shown in fig. 1, and the method includes:

s1, placing the wafer on a vacuum chuck of a CVD machine.

The wafer is used for integrating a groove type MOS device, a groove is formed on the wafer (the groove is used for forming a groove grid), an oxide layer is formed on the surfaces of the wafer and the groove (the oxide layer is formed on the surfaces of the wafer and the groove through a furnace tube oxidation process), and the vacuum chuck is arranged in a reaction chamber of a CVD machine table.

Referring to fig. 2, a cross-sectional view of a wafer placed on a vacuum chuck is shown. Illustratively, as shown in fig. 2, the wafer 200 has warpage, so that when it is placed on the heating tray 300 of the vacuum chuck, which includes the heating tray 300 and lift pins 310 (shown in fig. 3), the edge region thereof cannot be attached to the heating tray 300. In the embodiment of the present application, a height difference Δ h between the edge region and the central region is used as a warpage of the wafer (in calculation, a difference between a highest region and a lowest region when the wafer is placed can be used as a warpage), and the warpage of the wafer related to the embodiment of the present application is greater than 50 micrometers (μm).

And S2, carrying out preheating treatment on the wafer, wherein the pressure value in the reaction chamber of the CVD machine is a first pressure value during the preheating treatment.

Illustratively, step S2 includes, but is not limited to: increasing the pressure value in the reaction chamber of the CVD machine table to a first pressure value; the wafer is lifted from the vacuum chuck, and is subjected to a preheating treatment (the time of the preheating treatment is 50 seconds to 100 seconds, and the pressure of the preheating treatment is 150 torr to 450 torr), and after that, the wafer is lowered and placed back to the vacuum chuck.

And S3, vacuumizing the reaction chamber of the CVD machine, starting the vacuum adsorption function of the vacuum chuck, and increasing the pressure value in the reaction chamber of the CVD machine to a second pressure value.

And S4, carrying out vacuum pumping treatment on the reaction chamber of the CVD machine.

Referring to fig. 3, a schematic cross-sectional view of a wafer after being lifted from a heating tray is shown; referring to fig. 4, a cross-sectional schematic view after stress relief is shown. As shown in fig. 3, the thimble 310 is extended to lift the wafer 200 for preheating; as shown in fig. 4, after the preheating process, the pressure value in the reaction chamber is increased to the second pressure value, and then the vacuum process is performed, so that the stress of the wafer 200 is released, the warpage of the wafer is reduced, and the edge of the wafer is tightly attached to the heating tray 300.

And S5, increasing the pressure value in the reaction chamber of the CVD machine to a third pressure value.

In the embodiment of the application, the first pressure value is greater than the second pressure value and smaller than a third pressure value, and the third pressure value is greater than the second pressure value. The first pressure value may be 150 torr to 450 torr, the second pressure value may be 50 torr to 300 torr, and the third pressure value may be 450 torr to 800 torr.

Referring to fig. 2 to 4, the bottom of the vacuum chuck is communicated with a vacuum pipeline (not shown in fig. 2 to 4), the vacuum chuck can have a vacuum absorption function by opening a valve of the vacuum pipeline, then slowly increasing the pressure value in the reaction chamber of the CVD tool to a second pressure value, then re-vacuuming, and then increasing the pressure value in the reaction chamber of the CVD tool to a third pressure value.

And S6, depositing a silicon dioxide layer on the wafer through a CVD (chemical vapor deposition) process.

After the pressure value in the reaction chamber of the CVD tool is stabilized for a predetermined time (e.g., 15 seconds(s) to 60 seconds), a silicon dioxide layer may be deposited by the HARP CVD process. And after the deposition is finished and the vacuumizing treatment is continuously carried out, the vacuum adsorption function of the vacuum chuck is closed, and the wafer is transferred out of the reaction chamber.

In summary, in the embodiment of the present application, in the manufacturing process of the trench type MOS device, after the oxide layer on the surface of the trench and the trench is formed, the wafer in the CVD machine is preheated, and after the stress release pretreatment is performed on the wafer by the vacuum chuck, the CVD process is performed, so that the adsorption capacity of the chuck can be effectively increased, and the wafer and the chuck are tightly attached to each other, thereby reducing the temperature difference of the wafer in the CVD process and improving the uniformity of the CVD process.

It should be understood that the above examples are only for clarity of illustration and are not intended to limit the embodiments. Other variations and modifications will be apparent to persons skilled in the art in light of the above description. This need not be, nor should it be exhaustive of all embodiments. And obvious variations or modifications of this invention are intended to be covered by the scope of the invention as expressed herein.

Claims

1. A method for filling a trench, comprising:

vacuumizing a reaction chamber of the CVD machine table;

a silicon dioxide layer is deposited on the wafer by a CVD process.

2. The method of claim 1, wherein the pre-heating the wafer comprises:

3. The method of claim 2, wherein the first pressure value is greater than the second pressure value and less than the third pressure value.

4. The method of claim 3, wherein depositing a silicon dioxide layer on the wafer by a CVD process comprises:

depositing the silicon dioxide layer on the wafer by a HARP CVD process.

5. The method of any of claims 1 to 4, wherein the trench MOS device is an SGT MOS device.

6. The method of claim 5, wherein the wafer has a warp of greater than 50 microns.

7. The method of claim 6, wherein the oxide layer is formed by a furnace oxidation process.