CN102437100A - Method for simultaneously forming copper contact hole and first metal layer by dual damascene technique - Google Patents
Method for simultaneously forming copper contact hole and first metal layer by dual damascene technique Download PDFInfo
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- CN102437100A CN102437100A CN2011102653085A CN201110265308A CN102437100A CN 102437100 A CN102437100 A CN 102437100A CN 2011102653085 A CN2011102653085 A CN 2011102653085A CN 201110265308 A CN201110265308 A CN 201110265308A CN 102437100 A CN102437100 A CN 102437100A
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Abstract
The invention relates to the field of semiconductor manufacturing, particularly a method for simultaneously forming a copper contact hole and a first metal layer by a dual damascene technique. The invention discloses a method for simultaneously forming a copper contact hole and a first metal layer by a dual damascene technique. A dual damascene technique is utilized to simultaneously form a contact hole and a first metal layer; copper is used instead of tungsten as the material of the contact hole; and a TaN/WSiN or TaSiN/WSiN material is used instead of TaN/Ta as the material of the barrier layer. Thus, the technical steps are simplifies, and the contact resistance of the contact hole is reduced to effectively improve the lag characteristic of the subsequent technique and effectively enhance the copper diffusion barrier capacity of the barrier layer, thereby preventing copper diffusion from damaging the semiconductor device.
Description
Technical field
The present invention relates to field of semiconductor manufacture, relate in particular to a kind of method of using dual damascene process to form copper contact hole and ground floor metal simultaneously.
Background technology
As shown in Figure 1, in the ic manufacturing process now, postchannel process (Back End Of Line is called for short BEOL) Integrated Solution generally adopts the material of tungsten (W) as contact hole 1.Lasting miniature along with technology; The lag characteristic that the lag characteristic of BEOL has surmounted device becomes leading factor, wherein, because the resistivity and the lattice constant of tungsten are all bigger; By the contact hole structure of tungsten material, increasing to the contribution proportion that whole BEOL postpones as main electric conducting material.
United States Patent (USP) (application number US20090641945; A kind of production method of copper contact hole (METHOD FOR PRODUCING A COPPER CONTACT)) though in a kind of production method that adopts the copper contact hole of single Damascus technics is disclosed; But he adopts single Damascus technics to accomplish the formation of copper contact hole, needs more processing step to accomplish.
Microelectronics research center (Interuniversity Microelectronics Centre in 2006; Be called for short IMEC) reported a kind of copper (copper) contact hole (contact that S.Demuynck etc. writes; Abbreviation CT) scheme; Adopt TaN/Ta and Ti/TiN material in this scheme, but article shows that simultaneously the diffusion of copper (Cu) very easily takes place this scheme as diffusion impervious layer.And international electronic device conference in 2008 (International Electron Devices Meeting; Be called for short IEDM) reported a kind of employing dual damascene process (dual-damascene that J.Kawahara etc. writes; Abbreviation DD) copper contact hole structure (RF Performance Boostiong for 40nm-node CMOS Device by Low-k/Cu Dual Damascene Contact); Use therein diffusion impervious layer material also is TaN/Ta, and the diffusion of copper equally very easily takes place.
United States Patent (USP) (patent No. US2003034560; WIRING STRUCTURE OF SEMICONDUCTOR DEVICE; ELECTRODE; AND METHOD FOR FORMING THEM) disclose a kind of structure that is used for semiconductor device, the material of the diffusion impervious layer that it uses is WSiN, and interconnecting material is Cu or W.And ECS's magazine (journal of the electrochemical society) has been reported use WSiN structure that M.T.Wang etc. writes article (the Barrier Capabilities of Chemical Vapor Deposited W Films and WSiN/WSi for the diffusion barrier property of Cu
x/ W Stacked Layers Against Cu Diffusion); Point out in its article that electrical junction really shows; Through the high annealing of 750C, adopt the sample electric leakage of WSiN diffusion impervious layer not change a lot, it is good in the Cu diffusion barrier property to show that WSiN has.But the structure that article uses is the WSiN/Wsix/W structure, and this structure is non-existent in present deep submicron process.And its result shows that pure W sample still has good electrology characteristic when 700C, so, the good diffusion barrier property of WSiN for Cu can not be described fully.
People such as Qing-Tang Jiang disclose the article of TaSiN material to the diffusion barrier property of copper; Wherein point out because TaSiN is a kind of decrystallized material; And between TaSiN and the copper (Cu) stronger key and power are arranged, shown that all the TaSiN material can use as the diffusion barrier material with good adhesion separately.
Summary of the invention
The invention discloses a kind of method of using dual damascene process to form copper contact hole and ground floor metal simultaneously; Its anterior layer is for accomplishing the wafer of device formation and metal silicide deposit; Be provided with first and second grid above well region that in a substrate, forms and the STI isolated area; And on the sidewall of first and second grid, be coated with the skew side wall, metal silicide layer covers the upper surface of first and second grid and the source-drain electrode of first grid, and is provided with a gate oxide between first grid and its well region; Wherein, may further comprise the steps:
Step S1: source-drain electrode, first grid skew side wall and the second grid skew side wall of deposit dielectric layer to cover thin oxide layer metal silicide layer, first grid.
Step S2: adopt dual damascene process; The dielectric layer that etching is positioned at first grid source-drain electrode top is the metal silicide layer to the source-drain electrode of first grid respectively; Form first grid source electrode contact hole and ground floor metal groove and first grid drain contact hole and ground floor metal groove thereof; The while etching is positioned at the dielectric layer of second grid top to metal silicide layer, forms second grid contact hole and ground floor metal groove thereof.
Step S3: the deposit adhesion layer covers the source-drain electrode contact hole of first grid and the sidewall and the bottom thereof of ground floor metal groove and second grid contact hole and ground floor metal groove thereof thereof; Afterwards, after the deposit diffusion impervious layer covers adhesion layer, depositing metal copper and it is carried out planarization again.
Above-mentioned use dual damascene process forms the method for copper contact hole and ground floor metal simultaneously; Wherein, Adopt electrochemistry copper-plating technique cement copper, with source-drain electrode contact hole and ground floor metal groove and second grid contact hole and the ground floor metal groove thereof that is full of first grid.
Above-mentioned use dual damascene process forms the method for copper contact hole and ground floor metal simultaneously, wherein, adopts chemical mechanical milling tech that metals deposited copper is carried out planarization.
Above-mentioned use dual damascene process forms the method for copper contact hole and ground floor metal simultaneously, and wherein, in the said dual damascene process, the order of preparation contact hole and the first metal layer groove can be inverted.
Above-mentioned use dual damascene process forms the method for copper contact wire and ground floor metal simultaneously, and wherein, said adhesion layer material is TaN or TaSiN, and the material of said diffusion impervious layer is WSiN, to form TaN/WSiN or TaSiN/WSiN barrier layer.
In sum; Owing to adopted a kind of method of using dual damascene process to form copper contact hole and ground floor metal simultaneously of the present invention, form contact hole and the first metal layer simultaneously through dual damascene process, and use copper to replace the material of tungsten as contact hole; Utilize TaN/WSiN or TaSiN/WSiN material to replace the material of TaN/Ta simultaneously as the barrier layer; Not only simplified processing step, reduced the contact resistance of contact hole, with effective lag characteristic of improving postchannel process; And effectively increased the blocking capability of barrier layer, to avoid the damage of copper diffusion for semiconductor device for the copper diffusion.
Description of drawings
Fig. 1 adopts the structural representation of tungsten as traditional postchannel process of contact hole material in the background technology of the present invention;
Fig. 2-the 7th, the present invention use dual damascene process to form the schematic flow sheet of the method for copper contact hole and ground floor metal simultaneously.
Embodiment
Be further described below in conjunction with the accompanying drawing specific embodiments of the invention:
Shown in Fig. 2-7; A kind of method of using dual damascene process to form copper contact hole and ground floor metal simultaneously; On the STI isolated area 28 that above the well region 206 that in substrate 2, forms first grid 201 is set, in substrate 2, forms second grid 202 is set; And on the sidewall of first grid 201 and second grid 202, be coated with first grid skew side wall 203 and second grid skew side wall 204, metal silicide (silicide) 205 covers first grid 201, the upper surface of second grid 202 and the source-drain electrode of first grid, wherein; Between the well region 206 of first grid 201 and first grid 201 gate oxide 207 is set, sees Fig. 2.
Deposit dielectric layer (dielectric) 208 with source-drain electrode, first grid skew side wall 203 and the second grid skew side wall 204 that covers metal silicide layer 205, first grid 201, is seen Fig. 3; Afterwards, adopt dual damascene process (dual-damascene is called for short DD), the dielectric layer that etching is positioned at first grid source-drain electrode top is the metal silicide 205 to the source-drain electrode of first grid respectively
1, 205
2Form first grid source electrode contact hole 210 and ground floor metal groove 209 and first grid drain contact hole 212 and ground floor metal groove 211 thereof; Etching is positioned at the dielectric layer of second grid 202 tops simultaneously, forms second grid contact hole hole 214 and ground floor metal groove 213 thereof.Wherein, Guarantee contact hole 210 through the control etching technics; 212; 214 are parked on the metal silicide layer 205 in the technology, can prepare first grid source electrode contact hole 210, first grid drain contact hole 212 and second grid contact hole 214 earlier, prepare the ground floor metal groove 209 of first grid source electrode contact hole 210, the ground floor metal groove 211 in first grid drain contact hole hole 212 and the ground floor metal groove 213 in second grid contact hole hole 214 afterwards; Also can prepare the ground floor metal groove 209 of first grid source electrode contact hole 210, the ground floor metal groove 211 in first grid drain contact hole hole 212 and the ground floor metal groove 213 of second grid contact hole 214 earlier; After, prepare first grid source electrode contact hole 210, first grid drain contact hole 212 and second grid contact hole 214 again, see Fig. 4.
Afterwards, deposit adhesion layer 215 is to cover remaining dielectric layer 208
1Sidewall and the bottom thereof of upper surface, first grid source electrode contact hole 210 and ground floor metal groove 209, first grid drain contact hole 212 and ground floor metal groove 211 thereof and second grid contact hole 214 and ground floor metal groove 213 thereof on behind the remaining dielectric layer of etching, deposit diffusion impervious layer 216 covers adhesion layers 215; Wherein, the material of adhesion layer 215 is TaN or TaSiN, and the material of diffusion impervious layer 216 is WSiN, to form TaN/WSiN or TaSiN/WSiN barrier layer, sees Fig. 5.
At last, adopt electrochemistry copper-plating technique (electrochemical plating copper process is called for short ECP) cement copper (Cu) 217, to be full of the first grid source electrode contact hole 210 that is coated with diffusion impervious layer 216 and adhesion layer 215
1And ground floor metal groove 209
1, first grid drain contact hole 212
1And ground floor metal groove 211
1With second grid contact hole 214
1And ground floor metal groove 213
1, see Fig. 6; Adopt chemical mechanical milling tech (Chemical Mechanical Polishing is called for short CMP) that metals deposited copper 217 is carried out planarization, remove remaining dielectric layer 208
1Metallic copper, diffusion impervious layer and the adhesion layer of upper surface top, form first grid source interconnect lines 218, first grid drain electrode interconnection line 219, second grid interconnection line 220 and contact hole 221,222,223, see Fig. 7.
In sum, owing to adopted technique scheme, the present invention proposes to form simultaneously with dual damascene process the method and the structure of copper contact hole and ground floor metal; Through adopting dual damascene process to form contact hole and the first metal layer simultaneously; And use copper to replace the material of tungsten as contact hole, and utilize TaN/WSiN or TaSiN/WSiN material to replace the material of TaN/Ta simultaneously as the barrier layer, not only simplified processing step; Reduce the contact resistance of contact hole; With effective lag characteristic of improving postchannel process, and effectively increased the blocking capability of barrier layer, to avoid the damage of copper diffusion for semiconductor device for the copper diffusion.
More than specific embodiment of the present invention is described in detail, but it is just as example, the present invention is not restricted to the specific embodiment of above description.To those skilled in the art, any equivalent modifications that the present invention is carried out with substitute also all among category of the present invention.Therefore, not breaking away from impartial conversion and the modification of being done under the spirit and scope of the present invention, all should contain within the scope of the invention.
Claims (5)
1. method of using dual damascene process to form copper contact hole and ground floor metal simultaneously; Its anterior layer is for accomplishing the wafer of device formation and metal silicide deposit; Be provided with first and second grid above well region that in a substrate, forms and the STI isolated area; And on the sidewall of first and second grid, be coated with the skew side wall, metal silicide layer covers the upper surface of first and second grid and the source-drain electrode of first grid, and is provided with a gate oxide between first grid and its well region; It is characterized in that, may further comprise the steps:
Step S1: source-drain electrode, first grid skew side wall and the second grid skew side wall of deposit dielectric layer to cover thin oxide layer metal silicide layer, first grid;
Step S2: adopt dual damascene process; The dielectric layer that etching is positioned at first grid source-drain electrode top is the metal silicide layer to the source-drain electrode of first grid respectively; Form first grid source electrode contact hole and ground floor metal groove and first grid drain contact hole and ground floor metal groove thereof; The while etching is positioned at the dielectric layer of second grid top to metal silicide layer, forms second grid contact hole and ground floor metal groove thereof;
Step S3: the deposit adhesion layer covers the source-drain electrode contact hole of first grid and the sidewall and the bottom thereof of ground floor metal groove and second grid contact hole and ground floor metal groove thereof thereof; Afterwards, after the deposit diffusion impervious layer covers adhesion layer, depositing metal copper and it is carried out planarization again.
2. use dual damascene process according to claim 1 forms the method for copper contact hole and ground floor metal simultaneously; It is characterized in that; Adopt electrochemistry copper-plating technique cement copper, with source-drain electrode contact hole and ground floor metal groove and second grid contact hole and the ground floor metal groove thereof that is full of first grid.
3. use dual damascene process according to claim 1 forms the method for copper contact hole and ground floor metal simultaneously, it is characterized in that, adopts chemical mechanical milling tech that metals deposited copper is carried out planarization.
4. use dual damascene process according to claim 1 forms the method for copper contact hole and ground floor metal simultaneously, it is characterized in that, in the said dual damascene process, the order of preparation contact hole and the first metal layer groove can be inverted.
5. use dual damascene process according to claim 1 forms the method for copper contact wire and ground floor metal simultaneously; It is characterized in that; Said adhesion layer material is TaN or TaSiN, and the material of said diffusion impervious layer is WSiN, to form TaN/WSiN or TaSiN/WSiN barrier layer.
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Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103681508A (en) * | 2012-09-24 | 2014-03-26 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor device and manufacturing method thereof |
| CN103779321A (en) * | 2012-10-25 | 2014-05-07 | 联华电子股份有限公司 | Semiconductor structure with contact plug and formation method of semiconductor structure |
| CN105789114A (en) * | 2012-09-24 | 2016-07-20 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor device and manufacturing method thereof |
| CN110571187A (en) * | 2018-06-05 | 2019-12-13 | 中芯国际集成电路制造(上海)有限公司 | Method for manufacturing semiconductor device |
Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1233856A (en) * | 1998-04-27 | 1999-11-03 | 国际商业机器公司 | Copper interconnection structure incorporating metal seed layer |
| CN1649125A (en) * | 2004-01-26 | 2005-08-03 | 株式会社东芝 | Manufacturing method of semiconductor device |
| CN1674251A (en) * | 2004-01-12 | 2005-09-28 | 三星电子株式会社 | Method of fabricating semiconductor device and semiconductor device fabricated thereby |
| CN101097888A (en) * | 2001-10-04 | 2008-01-02 | 株式会社日立制作所 | Semiconductor integrated circuit device and a method of manufacturing the same |
| CN101373736A (en) * | 2002-09-17 | 2009-02-25 | 株式会社液晶先端技术开发中心 | Interconnect, interconnect forming method, thin film transistor, and display device |
| CN101819944A (en) * | 2010-04-28 | 2010-09-01 | 复旦大学 | Method for forming copper contact interconnection structure |
-
2011
- 2011-09-08 CN CN2011102653085A patent/CN102437100A/en active Pending
Patent Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1233856A (en) * | 1998-04-27 | 1999-11-03 | 国际商业机器公司 | Copper interconnection structure incorporating metal seed layer |
| CN101097888A (en) * | 2001-10-04 | 2008-01-02 | 株式会社日立制作所 | Semiconductor integrated circuit device and a method of manufacturing the same |
| CN101373736A (en) * | 2002-09-17 | 2009-02-25 | 株式会社液晶先端技术开发中心 | Interconnect, interconnect forming method, thin film transistor, and display device |
| CN1674251A (en) * | 2004-01-12 | 2005-09-28 | 三星电子株式会社 | Method of fabricating semiconductor device and semiconductor device fabricated thereby |
| CN1649125A (en) * | 2004-01-26 | 2005-08-03 | 株式会社东芝 | Manufacturing method of semiconductor device |
| CN101819944A (en) * | 2010-04-28 | 2010-09-01 | 复旦大学 | Method for forming copper contact interconnection structure |
Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103681508A (en) * | 2012-09-24 | 2014-03-26 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor device and manufacturing method thereof |
| CN105789114A (en) * | 2012-09-24 | 2016-07-20 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor device and manufacturing method thereof |
| CN103681508B (en) * | 2012-09-24 | 2016-12-21 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor device and manufacture method thereof |
| CN105789114B (en) * | 2012-09-24 | 2019-05-03 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor devices and its manufacturing method |
| CN103779321A (en) * | 2012-10-25 | 2014-05-07 | 联华电子股份有限公司 | Semiconductor structure with contact plug and formation method of semiconductor structure |
| CN110571187A (en) * | 2018-06-05 | 2019-12-13 | 中芯国际集成电路制造(上海)有限公司 | Method for manufacturing semiconductor device |
| CN110571187B (en) * | 2018-06-05 | 2022-03-18 | 中芯国际集成电路制造(上海)有限公司 | Method for manufacturing semiconductor device |
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Application publication date: 20120502 |