CN207818559U - Patch encapsulating structure without ground pin D class power amplifier integrated circuits - Google Patents
Patch encapsulating structure without ground pin D class power amplifier integrated circuits Download PDFInfo
- Publication number
- CN207818559U CN207818559U CN201721414057.1U CN201721414057U CN207818559U CN 207818559 U CN207818559 U CN 207818559U CN 201721414057 U CN201721414057 U CN 201721414057U CN 207818559 U CN207818559 U CN 207818559U
- Authority
- CN
- China
- Prior art keywords
- encapsulating structure
- integrated circuits
- power amplifier
- ground
- pin
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/4911—Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain
- H01L2224/49111—Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain the connectors connecting two common bonding areas, e.g. Litz or braid wires
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/4912—Layout
- H01L2224/49171—Fan-out arrangements
Landscapes
- Amplifiers (AREA)
Abstract
The utility model is related to a kind of patch encapsulating structures of no ground pin D class power amplifier integrated circuits, the patch encapsulating structure includes chip, packaging body and metal fin, the chip has at least two grounding ports, at least two grounding ports are bonded in respectively in the metal fin, and the metal fin is with the chip package in the packaging body.Using the patch encapsulating structure without ground pin D class power amplifier integrated circuits of the utility model, by the way that signal ground and Power Groud are drawn from the metal fin of package bottom, so that there is no signal grounds and Power Groud pin for the pin of integrated circuit, further reduce the pin number of packaging body, while reducing packaging cost, the PCB surface product in complete machine is also saved, there is wider application range.
Description
Technical field
The utility model is related to circuit field more particularly to integrated circuit fields, in particular to a kind of no ground pin D class work(
Put the patch encapsulating structure of integrated circuit.
Background technology
The encapsulation of current D class power amplifiers, be according to the requirement of chip PAD quantity, with the more packing forms of number of pins into
Row assembling all can be drawn the signal ground (SGND) of chip and Power Groud (PGND) by copper wire or gold wire bonding to encapsulation outer pin
Go out.That is, signal ground (SGND) and Power Groud (PGND) are drawn by the outer pin of encapsulation.
Using the packing forms of above-mentioned D classes power amplifier, with packaging cost height, pin spacing is small and be not easy to weld lacks
Point, while also increasing the welding cost of complete machine pcb board, and if be packaged with the less encapsulating structure of pin, can exist
The not enough problem of number of pins.
Utility model content
The shortcomings that the purpose of the utility model is to overcome the above-mentioned prior arts, packaging pin can be reduced by providing one kind
Several patch encapsulating structures without ground pin D class power amplifier integrated circuits.
To achieve the goals above, the patch encapsulating structure tool without ground pin D class power amplifier integrated circuits of the utility model
There is following composition：
The patch encapsulating structure without ground pin D class power amplifier integrated circuits, is mainly characterized by, patch encapsulation knot
Structure includes chip, packaging body and metal fin, and the chip has at least two grounding ports, at least two ground terminal
Mouth is bonded in respectively in the metal fin, and the metal fin is with the chip package in the packaging body
In.
At least two grounding ports of the patch encapsulating structure without ground pin D class power amplifier integrated circuits are bonded in institute respectively
The different location for stating metal fin, for reducing the interference between at least two grounding ports.
At least two grounding ports of the chip of the patch encapsulating structure without ground pin D class power amplifier integrated circuits include letter
Number ground port and Power Groud port.
The signal ground port of the patch encapsulating structure without ground pin D class power amplifier integrated circuits is bonded in the metal and dissipates
The left side of backing, the Power Groud port are bonded in the right of the metal fin.
The metal fin of patch encapsulating structure without ground pin D class power amplifier integrated circuits is connected with the ground of pcb board.
The patch encapsulating structure without ground pin D class power amplifier integrated circuits in the utility model is used, by signal
Ground and Power Groud are drawn from the metal fin of package bottom so that there is no signal grounds and Power Groud to draw for the pin of integrated circuit
Foot further reduces the pin number of packaging body, while reducing packaging cost, also saves the PCB surface product in complete machine,
With wider application range.
Description of the drawings
Fig. 1 is the routing figure of the patch encapsulating structure without ground pin D class power amplifier integrated circuits of the utility model.
Fig. 2 is the pin arrangements figure of the patch encapsulating structure without ground pin D class power amplifier integrated circuits of the utility model.
Fig. 3 is another routing figure of the patch encapsulating structure without ground pin D class power amplifier integrated circuits of the utility model.
Fig. 4 is another pin arrangements of the patch encapsulating structure without ground pin D class power amplifier integrated circuits of the utility model
Figure.
Specific implementation mode
In order to more clearly describe the technology contents of the utility model, come into traveling one with reference to specific embodiment
The description of step.
The patch encapsulating structure without ground pin D class power amplifier integrated circuits, is mainly characterized by, patch encapsulation knot
Structure includes chip, packaging body and metal fin, and the chip has at least two grounding ports, at least two ground terminal
Mouth is bonded in respectively in the metal fin, and the metal fin is with the chip package in the packaging body
In, in a specific embodiment, this can be bonded with to ground terminal of the metal fin as integrated circuit of grounding ports
(GND), the packaging pin quantity of integrated circuit is reduced with this.
At least two grounding ports of the patch encapsulating structure without ground pin D class power amplifier integrated circuits are bonded in institute respectively
The different location for stating metal fin, for reducing the interference between at least two grounding ports.
At least two grounding ports of the chip of the patch encapsulating structure without ground pin D class power amplifier integrated circuits include letter
The signal ground port of chip and Power Groud port can be bonded by number ground port and Power Groud port in a specific embodiment
To the heat dissipation metal on piece of package bottom.
The signal ground port of the patch encapsulating structure without ground pin D class power amplifier integrated circuits is bonded in the metal and dissipates
The left side of backing, the Power Groud port is bonded in the right of the metal fin, to reduce signal ground port and work(
Rate ground interfering with each other between port.
The metal fin of patch encapsulating structure without ground pin D class power amplifier integrated circuits is connected with the ground of pcb board.
In a specific embodiment, since the grounding ports of the patch encapsulating structure chips of the utility model pass through gold
Belong to cooling fin to draw, therefore the outer pin of the encapsulating structure can save grounding pin (refering to Fig. 2 and Fig. 4), therefore by reasonable
Arrange bonding routing that can realize the encapsulating structure (refering to fig. 1) and binary channels D class power amplifiers of single channel D class power amplifier integrated circuits respectively
The encapsulating structure of integrated circuit (refering to Fig. 3).
In the technical solution of the patch encapsulating structure without ground pin D class power amplifier integrated circuits of the utility model, wherein institute
Including each function module and modular unit can correspond to the particular hardware circuit in integrated circuit structure, therefore only relate to
And the improvement of particular hardware circuit, hardware components not only only belong to execute the carrier of control software or computer program, because
This solves corresponding technical problem and obtains corresponding technique effect to be also not directed to any control software or computer program
Application, that is to say, that the utility model is just with changing in terms of the hardware circuit involved by these modules and unit
Into technical problem to be solved can be solved, and corresponding technique effect is obtained, and does not need to auxiliary specifically to control
Corresponding function can be thus achieved in software or computer program processed.
The patch encapsulating structure without ground pin D class power amplifier integrated circuits in the utility model is used, by signal
Ground and Power Groud are drawn from the metal fin of package bottom so that there is no signal grounds and Power Groud to draw for the pin of integrated circuit
Foot further reduces the pin number of packaging body, while reducing packaging cost, also saves the PCB surface product in complete machine,
With wider application range.
In this description, the utility model is described with reference to its specific embodiment.But it is clear that still can be with
The spirit and scope that various modification can be adapted and converts without departing from the utility model.Therefore, the description and the appended drawings should be considered as
It is illustrative and not restrictive.
Claims (5)
1. a kind of patch encapsulating structure of no ground pin D class power amplifier integrated circuits, which is characterized in that the patch encapsulating structure
Including chip, packaging body and metal fin, the chip has at least two grounding ports, at least two grounding ports
It is bonded in respectively in the metal fin, the metal fin is with the chip package in the packaging body
In.
2. the patch encapsulating structure of no ground pin D class power amplifier integrated circuits according to claim 1, which is characterized in that institute
At least two grounding ports stated are bonded in the different location of the metal fin respectively, for reducing at least two ground connection
Interference between port.
3. the patch encapsulating structure of no ground pin D class power amplifier integrated circuits according to claim 1, which is characterized in that institute
At least two grounding ports of the chip stated include signal ground port and Power Groud port.
4. the patch encapsulating structure of no ground pin D class power amplifier integrated circuits according to claim 3, which is characterized in that institute
The signal ground port stated is bonded in the left side of the metal fin, and the Power Groud port is bonded in the metal and dissipates
The right of backing.
5. the patch encapsulating structure of no ground pin D class power amplifier integrated circuits according to claim 1, which is characterized in that institute
The metal fin stated is connected with the ground of pcb board.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201721414057.1U CN207818559U (en) | 2017-10-30 | 2017-10-30 | Patch encapsulating structure without ground pin D class power amplifier integrated circuits |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201721414057.1U CN207818559U (en) | 2017-10-30 | 2017-10-30 | Patch encapsulating structure without ground pin D class power amplifier integrated circuits |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN207818559U true CN207818559U (en) | 2018-09-04 |
Family
ID=63336156
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201721414057.1U Active CN207818559U (en) | 2017-10-30 | 2017-10-30 | Patch encapsulating structure without ground pin D class power amplifier integrated circuits |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN207818559U (en) |
-
2017
- 2017-10-30 CN CN201721414057.1U patent/CN207818559U/en active Active
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US9554453B2 (en) | Printed circuit board structure with heat dissipation function | |
| CN102263094A (en) | Non-interconnected multi-chip package diode | |
| TW200739835A (en) | Land grid array semiconductor device packages, assemblies including same, and methods of fabrication | |
| KR20150016711A (en) | Multi-chip package | |
| CN105489571A (en) | Semiconductor package with cooling fin, and packaging method for semiconductor package | |
| CN207818559U (en) | Patch encapsulating structure without ground pin D class power amplifier integrated circuits | |
| CN204706557U (en) | A kind of Intelligent Power Module | |
| US20070063333A1 (en) | Semiconductor package with internal shunt resistor | |
| KR20010056618A (en) | Semiconductor package | |
| CN203871315U (en) | Electronic equipment | |
| CN104167403B (en) | Lead frame for multi-pin encapsulation | |
| US20050230842A1 (en) | Multi-chip flip package with substrate for inter-die coupling | |
| US8791007B2 (en) | Device having multiple wire bonds for a bond area and methods thereof | |
| CN104966708A (en) | Semiconductor package structure | |
| CN104867913A (en) | Three-dimensional packaging structure for multi-chip mixing integration and processing method thereof | |
| CN201946589U (en) | Improved lead frame | |
| US20030127721A1 (en) | Semiconductor device | |
| CN204361080U (en) | Circuits System and chip package thereof | |
| KR20080067891A (en) | Multi chip package | |
| CN101404271B (en) | Audio power amplifier package | |
| CN205319143U (en) | Be packaged with a plurality of audio power amplifier chip's circuit structure | |
| CN203278755U (en) | Chip with multiple packaged audio power amplifying circuit wafers | |
| CN204315566U (en) | Based on the Novel lead frame that TO-220CE lead frame improves | |
| CN204303801U (en) | The encapsulating structure rerouted after two-sided BUMP chip package | |
| CN211150559U (en) | Multi-chip packaging module |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| GR01 | Patent grant | ||
| GR01 | Patent grant | ||
| CP03 | Change of name, title or address | ||
| CP03 | Change of name, title or address |
Address after: 214135 -6, Linghu Avenue, Wuxi Taihu international science and Technology Park, Wuxi, Jiangsu, China, 180 Patentee after: China Resources micro integrated circuit (Wuxi) Co., Ltd Address before: 214135 Jiangsu city of Wuxi province Taihu international science and Technology Park Linghu Road No. 180 -22 Patentee before: WUXI CHINA RESOURCES SEMICO Co.,Ltd. |