CN207766248U - A kind of isolation circuit - Google Patents
A kind of isolation circuit Download PDFInfo
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- CN207766248U CN207766248U CN201720830285.0U CN201720830285U CN207766248U CN 207766248 U CN207766248 U CN 207766248U CN 201720830285 U CN201720830285 U CN 201720830285U CN 207766248 U CN207766248 U CN 207766248U
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Abstract
The utility model provides a kind of isolation circuit, including：Main isolating capacitor, the second capacitor, secondary isolating capacitor, the 4th capacitor and amplifier, wherein the second end of the main isolating capacitor is connected to the input terminal of the first end and the amplifier of second capacitor；The second end of the secondary isolating capacitor is connected to the input terminal of the first end and the amplifier of the 4th capacitor；The second end of second capacitor and the second end of the 4th capacitor are commonly connected to ground terminal；The input of the first end of the main isolating capacitor and the first end of the secondary isolating capacitor is in reverse phase；And wherein described second capacitor, the 4th capacitor and amplifier are in the second tube core.By one or more embodiments of the utility model, higher isolation voltage may be implemented, and since circuit and isolation capacitance are made of CMOS technology, there is no the problem of aging of optocoupler, the problems such as performance varies with temperature, poor electrical performance, therefore stable quality, long lifespan are at low cost.
Description
Technical field
The utility model is related to circuit fields, more particularly, to the isolation circuit in high-tension circuit field.
Background technology
Optocoupler is to transmit the device of signal using light as medium, and usually photophore and receiver (photosensitive semiconductor pipe) are sealed
In same shell.When input terminal plus current signal, photophore emits beam, and receiver just generates after receiving light
Photoelectric current is exported from output end, to realize " electricity-light-electricity " conversion.Input end signal is coupled to using light as medium defeated
The photoelectrical coupler of outlet, photoelectrical coupler are 50 years pervious technologies, it is realized for the first time is realized by a device
Signal isolation, it is widely applied on power control circuit.
But the shortcomings that optocoupler, is：Because the electrical property of light emitting diode varies with temperature, the electrical property of optocoupler
It varies with temperature, it is unstable.In addition, because light emitting diode and the plastics of isolation have problem of aging, optical coupling isolator
There is performance problem of aging.Further, there is also the low problems of common-mode rejection ratio for optocoupler, because of light emitting diode and receiving electricity
There is parasitic capacitance between road, when there is prodigious common-mode voltage variation on both sides, such as 30kV/us, the electric current of parasitic capacitance can allow hair
Optical diode shines and forms maloperation.Finally, it is additionally based on the principle of optocoupler, there is that speed is low, power consumption is high, it is not easy to is integrated etc.
Disadvantage.
Utility model content
The purpose of this utility model is to provide a kind of isolation circuits that can overcome coupler disadvantage in the prior art.
One side according to the present utility model provides a kind of isolation circuit, including：Main isolating capacitor (C1), second
Capacitor (C2), secondary isolating capacitor (C3), the 4th capacitor (C4) and amplifier (AMP), wherein the main isolating capacitor
(C1) second end is connected to the input terminal of the first end and the amplifier (AMP) of second capacitor (C2)；Described time
The second end of isolating capacitor (C3) is connected to the input of the first end and the amplifier (AMP) of the 4th capacitor (C4)
End；The second end of second capacitor (C2) and the second end of the 4th capacitor (C4) are commonly connected to ground terminal (GND)；Institute
The input for stating the first end of main isolating capacitor (C1) and the first end of the secondary isolating capacitor (C2) is in reverse phase；And wherein
Second capacitor (C2), the 4th capacitor (C4) and amplifier (AMP) are in the second tube core.
An embodiment according to the present utility model, wherein the input terminal of the amplifier (AMP) includes the first input
End and the second input terminal, and wherein, the second end of the main isolating capacitor (C1) is connected to second capacitor (C2)
First end and the amplifier (AMP) first input end；The second end of the secondary isolating capacitor (C3) is connected to described
Second input terminal of the first end and the amplifier (AMP) of the 4th capacitor (C4).
An embodiment according to the present utility model further comprises that latch (L1), the latch (L1) include
The second end of first input end, the second input terminal and output end, the main isolating capacitor (C1) is connected to the latch
(L1) first input end；The second end of the secondary isolating capacitor (C3) is connected to the second input of the latch (L1)
End；The output end of the latch (L1) is connected to the input terminal of the amplifier (AMP).
An embodiment according to the present utility model, further comprises phase inverter (12), the phase inverter (12) it is defeated
Enter one that end is connected in the first end of the main isolating capacitor (C1) and the first end of the secondary isolating capacitor (C2),
To receive the input of the isolating capacitor；And the output end of the phase inverter (12) is connected to the main isolating capacitor (C1)
First end and the secondary isolating capacitor (C2) first end in another；The phase inverter (12) is in first tube core
In.
An embodiment according to the present utility model, further comprises buffer (11), the buffer (11) it is defeated
Outlet is connected to the input terminal of the phase inverter (12), and is connected to the first end of the main isolating capacitor (C1) and described time
One in the first end of isolating capacitor (C2)；The buffer (11) is in first tube core.
An embodiment according to the present utility model, wherein the main isolating capacitor (C1) and time isolating capacitor
At least one of (C3) in first tube core.
An embodiment according to the present utility model, wherein the main isolating capacitor (C1) and time isolating capacitor
At least one of (C3) in the second tube core.
An embodiment according to the present utility model, wherein the main isolating capacitor (C1) includes concatenated first
Main isolating capacitor (C11) and the second main isolating capacitor (C12), the first main isolating capacitor (C11) are in the first pipe
In core, the second main isolating capacitor (C12) is in the second tube core；The secondary isolating capacitor (C3) includes concatenated
Isolating capacitor (C31) and second of isolating capacitor (C32), the first time isolating capacitor (C31) are in first
In tube core, second of isolating capacitor (C32) is in the second tube core.
An embodiment according to the present utility model, wherein the first main isolating capacitor (C11) and second master every
Capacitance from capacitor (C12) is equal；The first time isolating capacitor (C31) and second isolating capacitor (C32)
Capacitance is equal.
An embodiment according to the present utility model, wherein the ground terminal (GND) is the ground terminal of the second tube core.
An embodiment according to the present utility model, wherein the main isolating capacitor (C1) and second capacitance
Ratio between device (C2) is 1:0 to 1:1000.
An embodiment according to the present utility model, wherein the main isolating capacitor (C1) and second capacitance
Ratio between device (C2) is 1:100.
An embodiment according to the present utility model, wherein the main isolating capacitor (C1) and second capacitance
Ratio between device (C2) is equal to the ratio between the secondary isolating capacitor (C3) and the 4th capacitor (C4).
An embodiment according to the present utility model, wherein the main isolating capacitor (C1) and described isolation electricity
The capacitance of container (C3) is equal；And the capacitance of second capacitor (C2) and the 4th capacitor (C4) is equal.
Another aspect according to the present utility model provides a kind of multichannel isolation circuit, including on arranged side by side at least two
State isolation circuit.
By one or more embodiments of the utility model, higher isolation voltage may be implemented, and due to device
Part is silicon dioxide device, the problem of aging of optocoupler is not present, therefore stable quality, long lifespan are at low cost.
Further, two input terminals of the utility model use inversion signal, advantageously allow output signal obtain it is double
Amplify again, to realize better signal-to-noise ratio.
Description of the drawings
By reading the detailed description of hereafter preferred embodiment, various other advantages and benefit are common for this field
Technical staff will become clear.Attached drawing only for the purpose of illustrating preferred embodiments, and is not considered as to this practicality
Novel limitation.And throughout the drawings, the same reference numbers will be used to refer to the same parts.In the accompanying drawings：
Fig. 1 is the circuit diagram according to the isolation circuit of one embodiment of the utility model；
Fig. 2 is the circuit diagram according to the isolation circuit of one embodiment of the utility model；
Fig. 3 is the waveform diagram according to each node of circuit shown in the utility model Fig. 2；
Fig. 4 is the circuit diagram according to the isolation circuit with enhancing signal-to-noise ratio of one embodiment of the utility model；
Fig. 5 is the circuit diagram according to the isolation circuit of the utility model another embodiment；
Fig. 6 shows the circuit diagram of the isolation circuit including phase inverter according to one embodiment of the utility model；
Fig. 7 shows the circuit diagram of the isolation circuit according to one preferred embodiment of the utility model；
Fig. 8 shows the waveform diagram of circuit according to figure 6；
Fig. 9 shows the block diagram for the multichannel isolation circuit that two isolation circuits form side by side.
Specific implementation mode
The exemplary embodiment of the disclosure is more fully described below with reference to accompanying drawings.Although showing the disclosure in attached drawing
Exemplary embodiment, it being understood, however, that may be realized in various forms the disclosure without should be by embodiments set forth here
It is limited.On the contrary, these embodiments are provided to facilitate a more thoroughly understanding of the present invention, and can be by the scope of the present disclosure
Completely it is communicated to those skilled in the art.
Fig. 1 is the circuit diagram according to the isolation circuit of one embodiment of the utility model.
As shown in Figure 1, isolation circuit provided by the utility model includes：Buffer 11, main isolating capacitor C1, the second electricity
Container C2, secondary isolating capacitor C3, the 4th capacitor C4 and amplifier AMP, wherein the input terminal of buffer 11 is for receiving this
The first end of the input of isolation circuit, main isolating capacitor C1 is connected to the output end of the buffer 11, the main isolating capacitor
The second end of C1 is connected to the first input end of the first end and amplifier AMP of the second capacitor C2；Secondary isolating capacitor
The second end of C3 is connected to the second input terminal of the first end and the amplifier AMP of the 4th capacitor C4；Described second
The second end of capacitor C2 and the second end of the 4th capacitor C4 are commonly connected to ground terminal GND；The of secondary isolating capacitor C3
One end is connected to the first ground terminal GND1.
In Fig. 1, buffer 11 is dispensed, and main function is to eliminate noise.
It is the very low capacitance of capacitance generally, due to main isolating capacitor C1 and the second capacitor C2, C1 is generally in flying method
(fF) rank, and circuit generally has leakage current.Even if leakage current can only maintain if being in pico-ampere (pA) rank capacitance itself
Millisecond rank, and certain voltage cannot be maintained for a long time, to output be maintained constant inputting constant situation, thus
Voltage isolation is adversely affected.
For this reason, it may be necessary to stablize the output of main isolating capacitor C1, so that the signal of the output end of amplifier keeps stablizing,
In particular, it is desirable to specific voltage be maintained in the long period, so that maintaining output to stablize in the case where inputting constant.
Fig. 2 is the circuit diagram according to the isolation circuit of one embodiment of the utility model.
As shown in Fig. 2, on the basis of Fig. 1, an embodiment according to the present utility model further comprises latch
L1.Specifically, the isolation circuit of Fig. 2 includes buffer 11, and main isolating capacitor C1, the second capacitor C2, secondary isolation capacitance
Device C3, the 4th capacitor C4 and amplifier AMP, wherein the input terminal of buffer 11 is used to receive the input of the isolation circuit, main
The first end of isolating capacitor C1 is connected to the output end of the buffer 11, and the second end of the main isolating capacitor C1 is connected to institute
State the first input end of the first end and latch L1 of the second capacitor C2；The second end of secondary isolating capacitor C3 is connected to described
Second input terminal of the first end of the 4th capacitor C4 and the latch L1；The second end and the 4th of the second capacitor C2
The second end of capacitor C4 is commonly connected to ground terminal GND；The first end of secondary isolating capacitor C3 is connected to the first ground terminal
GND1；The output end of latch L1 is connected to the input terminal of amplifier AMP.
Fig. 3 is the waveform diagram according to each node of circuit shown in the utility model Fig. 2.Show Fig. 2 interior joints
A, the waveform of the waveform diagram at B, C, D and E, wherein A and B is similar or identical, and difference lies in the waveforms at node A to deposit
The situations such as noise or non-square-wave signal (these noises are not shown at the waveform of Fig. 2 nodes A), buffer 11 acts on
In these noises of elimination.If the high level at node A is Vdd, therefore the high level at node B is also Vdd.
As shown in figure 3, the oscillogram of node A and B are, for example, square-wave signal, and after main isolating capacitor C1, waveform
Figure becomes the square-wave signal as shown in Fig. 2 interior joints C, and level is C1/ (C1+C2) * Vdd.By reaching D after latch L1
Point.Due to the presence of latch, the level of C points is will remain in, therefore, the level at node C and D can be C1/ (C1+
C2)*Vdd.According to the utility model another embodiment, the level at D can have certain amplification, such as D relative to C points
The level at place is 2-3 times of level at C.Finally, E points are reached by digital amplifier, signal is enlarged into institute after amplification
The level needed is for further processing.
It is to be appreciated that for the amplifier AMP in Fig. 1-2, the amplifier of single ended input may be used, can also adopt
With the amplifier of double input end, those skilled in the art can select suitable amplifier according to actual demand.
In fig. 1 and 2, the first end of secondary isolating capacitor C3 is connected to the first ground terminal GND1, this is advantageously reduced
Or the common-mode noise in elimination isolation circuit.In order to further increase the signal-to-noise ratio of isolation circuit, the utility model carried out into
The improvement of one step.
Fig. 4 is the circuit diagram according to the isolation circuit with enhancing signal-to-noise ratio of one embodiment of the utility model.
As shown in figure 4, isolation circuit provided by the utility model includes：Main isolating capacitor C1, the second capacitor C2, it is secondary
Isolating capacitor C3, the 4th capacitor C4 and amplifier AMP, wherein the second end of main isolating capacitor C1 is connected to described
The input terminal of the first end and amplifier AMP of two capacitor C2；The second end of secondary isolating capacitor C3 is connected to the 4th electricity
The input terminal of the first end of container C4 and the amplifier AMP；The second end and the 4th capacitor C4 of the second capacitor C2
Second end be commonly connected to ground terminal GND；First input INPUT1 of the first end of main isolating capacitor C1 and the septum secundum
Second input INPUT2 of the first end from capacitor C2 is in reverse phase；And wherein, the second capacitor C2, the 4th capacitor C4 and
Amplifier AMP is in the second tube core.
In Fig. 4, the first input INPUT1 and the second input INPUT2 is in reverse phase, i.e., when INPUT1 is digital signal " 1 "
When, the input of INPUT2 is digital signal " 0 ", then relative to the circuit described in Fig. 2, the output of amplifier AMP shown in Fig. 4 can
To be enlarged into original twice, to significantly increase signal-to-noise ratio.
An embodiment according to the present utility model, as shown in figure 4, the input terminal of the amplifier AMP may include
First input end and the second input terminal, and wherein, the second end of the main isolating capacitor C1 is connected to second capacitance
The first input end of the first end of device C2 and the amplifier AMP；The second end of the secondary isolating capacitor C3 is connected to described
Second input terminal of the first end of the 4th capacitor C4 and the amplifier AMP.
As noted previously, as main isolating capacitor C1, the second capacitor C2, secondary isolating capacitor C3 and the 4th capacitor
C4 is the very low capacitance of capacitance, and C1 and C3 are generally in flying method (fF) rank, and circuit generally has leakage current.Even if leakage current
In pico-ampere (pA) rank, capacitance itself can only also maintain millisecond rank, and cannot maintain certain voltage for a long time, to
Output cannot be maintained constant inputting constant situation, thus voltage isolation is adversely affected.
For this reason, it may be necessary to stablize the output of main isolating capacitor C1 and time isolating capacitor C3, so that the output of amplifier
The signal at end keeps stablizing, in particular, it is desirable to specific voltage be maintained in the long period, so that in the case where inputting constant
Output is maintained to stablize.
Fig. 5 is the circuit diagram according to the isolation circuit of the utility model another embodiment.
As shown in figure 5, on the basis of Fig. 4, the utility model further comprises latch L1, latch (L1) packet
First input end, the second input terminal and output end are included, the second end of the main isolating capacitor C1 is connected to the latch L1
First input end；The second end of the secondary isolating capacitor C3 is connected to the second input terminal of the latch L1；The lock
The output end of storage L1 is connected to the input terminal of the amplifier AMP.
It is to be appreciated that although amplifier AMP shown in Fig. 5 is only single input terminal, this is only to illustrate,
Can be two input terminals, for example, as shown in figure 4 as.
Fig. 6 shows the circuit diagram of the isolation circuit including phase inverter according to one embodiment of the utility model.
In order to realize that the first input end INPUT1 and the second input terminal INPUT2 of isolating capacitor are in reverse phase, according to this reality
With a novel embodiment, phase inverter 12 may be used, the input terminal of the phase inverter 12 is connected to the main isolation electricity
One in the first end of container C1 and the first end of the secondary isolating capacitor C3, to receive the defeated of the isolating capacitor
Enter；And the output end of the phase inverter 12 is connected to the first end of the main isolating capacitor C1 and the secondary isolating capacitor C3
First end in another；The phase inverter 12 is in first tube core.
In fig. 6 it is shown that the input terminal of phase inverter 12 is connected to the first end of main isolating capacitor C1, and phase inverter 12
Output end be connected to the first end of time isolating capacitor C3.Although being not shown, but it is understood that, the output of phase inverter 12
End may be coupled to the first end of main isolating capacitor C1, and the input terminal of phase inverter 12 may be coupled to time isolating capacitor C3
First end.
In figure 6, the first end of main isolating capacitor C1 can be directly connected to the first input end of the isolation circuit
INPUT1, since there may be some noises by INPUT1, then preferably, an embodiment according to the present utility model, into one
Step includes buffer 11, and the output end of the buffer 11 is connected to the input terminal of the phase inverter 12, and is connected to the master
One in the first end of isolating capacitor C1 and the first end of the secondary isolating capacitor C2；The buffer 11 is in first
In tube core.
For main isolating capacitor C1 and time isolating capacitor C3, a variety of set-up modes may be used.Main isolating capacitor
At least one of C1 and time isolating capacitor C3 are in first tube core or the second tube core.For example, it may be main isolation capacitance
Device C1 and time isolating capacitor C3 are in first tube core；Alternatively, only main isolating capacitor C1 is in first tube core,
And secondary isolating capacitor C3 is in the second tube core；Alternatively, only main isolating capacitor C1 is in the second tube core, and septum secundum
It is in first tube core from capacitor C3；Alternatively, can be that main isolating capacitor C1 and time isolating capacitor C3 are in second
In tube core.
Above-mentioned setting brings many convenience to design, and designer can be outputting and inputting circuit design in same pipe
In core, then allows input circuit to work according to the market demand or output circuit works.This brings more spirits to design and market
Activity.
An embodiment according to the present utility model, between the main isolating capacitor C1 and the second capacitor C2
Ratio be equal to ratio between the secondary isolating capacitor C3 and the 4th capacitor C4, i.e. C1：C2=C3：C4.
In the above-described embodiment, may exist following possibility, i.e. C1=n*C3, and C2=n*C4, wherein n are
The arbitrary number more than 0, thus, it is possible to realize C1：C2=C3：C4.Preferably, C1=C3, C2=C4, this is conducive to component
Batch production and buying, reduce system cost, and since the numerical value between capacitor is identical, but also system is more stable.
Fig. 7 shows the circuit diagram of the isolation circuit according to one preferred embodiment of the utility model.
A preferred embodiment according to the present utility model, the main isolating capacitor C1 include it is concatenated first master every
Isolating capacitor C12 main from capacitor C11 and second, the first main isolating capacitor C11 are in first tube core, and described
Two main isolating capacitor C12 are in the second tube core；The secondary isolating capacitor C3 includes concatenated first time isolating capacitor
C31 and second of isolating capacitor C32, the first time isolating capacitor C31 is in first tube core, described to be isolated for the second time
Capacitor C32 is in the second tube core.
Preferably, the capacitance of the described first main main isolating capacitor C12 of isolating capacitor C11 and second is equal；It is described
The first time capacitance of isolating capacitor C31 and second of isolating capacitor C32 is equal.It is highly preferred that the first main isolation capacitance
Device C11, the second main isolating capacitor C12 first time isolating capacitors C31, the capacitance of second of isolating capacitor C32 are equal.
An embodiment according to the present utility model, the ground terminal GND can be the ground terminal of the second tube core.
An embodiment according to the present utility model, between the main isolating capacitor C1 and the second capacitor C2
Ratio and C3 and C4 between ratio be 1:0 to 1:1000, preferably 1:10 to 1:1000, more preferably 1:100.
It can be seen from figure 7 that assuming that incoming level INPUT1 is Vdd, then the level at the second capacitor C2 is C1/
(C1+C2) * Vdd, and pass through after phase inverter 12, the level at the 4th capacitor C4 is-C3/ (C3+C4) * Vdd.Therefore,
Two capacitor C2 and the 4th capacitance C4 theoretically and most preferably 0, i.e., the second end of main isolation capacitance C1 and secondary isolation
The second end of capacitor C3 is disconnected with ground terminal GND.But it also will produce parasitic capacitance in fact, disconnecting.This reality
With it is novel from principle it is also possible that the capacitance of C2 and C4 is ad infinitum close to 0, therefore be also at the guarantor of the utility model
Within the scope of shield.Second capacitor C2 and the 4th capacitor C4 can also be input capacitance and parasitic capacitance of circuit etc. other
The combination of capacitance.
From the angle of performance, the preferred C1 of the utility model：C2=C3：C4=1:0, this will show best property
Energy.But from cost for, C1 and C3 then influence whether cost very much greatly.An embodiment according to the present utility model, it is excellent
Select C1：The ratio of C2 is smaller.The utility model can also use the capacitance of other ratios, such as C1:C2=C3:C4=1:10,
1:30,1:50,1:150,1:200 etc..
By one or more embodiments of the utility model, higher isolation voltage may be implemented, and due to device
Part is silicon dioxide device, the problem of aging of optocoupler is not present, therefore stable quality, long lifespan are at low cost.The utility model can
In a manner of by isolation capacitance so that signal can be directly through spacer medium, and simple in structure, loss is small, at low cost.
In addition, the scheme relative to Fig. 1 and Fig. 2, Fig. 4 to scheme shown in Fig. 7 can realize the gain and more preferably of bigger
Signal-to-noise ratio.
Fig. 8 shows the waveform diagram of circuit according to figure 6.
As shown in figure 8, node A, B and B ' oscillogram be, for example, square-wave signal, the waveform of B points and B ' points is in reverse phase, warp
It crosses after main isolating capacitor C1 and time isolating capacitor C3, oscillogram becomes such as Fig. 8 interior joints C and the C ' (letter of C points and C ' points
Number be in reverse phase) shown in square-wave signal, level is respectively C1/ (C1+C2) * Vdd and-C3/ (C3+C4) * Vdd.By latching
D points are reached after device L1, the level of D points will be C1/ (C1+C2) * Vdd+C3/ (C3+C4) * Vdd.It is another according to the utility model
A embodiment, the level at D can have certain amplification, such as the level at D is 3 times of level at C or more.Finally,
E points are reached by digital amplifier, signal is enlarged into required level for further processing after amplification.
Furthermore, it is possible to multiple isolation circuits provided by the utility model are got up side by side, the input of multichannel and defeated is formed
Go out.
Fig. 9 shows the block diagram for the multichannel isolation circuit that two isolation circuits form side by side.
As shown in figure 9, the multichannel isolation circuit 900 includes two 910 Hes of single channel isolation circuit module arranged side by side
920, wherein for the clear and succinct reason of description, circuit diagram as shown in Figure 6 and Figure 7 be simplified shown as module 910 or
920.Multichannel isolation circuit will effectively promote the rate of data.
It is to be appreciated that although Fig. 9 shows two arranged side by side but channel separation circuit modules, people in the art
Member may include more single channel isolation circuit modules.
The utility model is limited it should be noted that above-described embodiment illustrates rather than the utility model,
And those skilled in the art can design alternative embodiment without departing from the scope of the appended claims.In right
In it is required that, any reference mark between bracket should not be configured to limitations on claims.Word "comprising" is not arranged
Except there are element or steps not listed in the claims.Word "a" or "an" before element does not exclude the presence of more
A such element.The utility model can be by means of including the hardware of several different elements and by means of properly programmed
Computer is realized.In the unit claims listing several devices, several in these devices can be by same
One hardware branch embodies.The use of word first, second, and third does not indicate that any sequence.
Claims (19)
1. a kind of isolation circuit, including：Main isolating capacitor (C1), the second capacitor (C2), secondary isolating capacitor (C3), the 4th
Capacitor (C4) and amplifier (AMP), wherein
The second end of the main isolating capacitor (C1) is connected to the first end of second capacitor (C2) and the amplifier
(AMP) input terminal；
The second end of the secondary isolating capacitor (C3) is connected to the first end of the 4th capacitor (C4) and the amplifier
(AMP) input terminal；
The second end of second capacitor (C2) and the second end of the 4th capacitor (C4) are commonly connected to ground terminal (GND)；
The input of the first end of the main isolating capacitor (C1) and the first end of the secondary isolating capacitor (C2) is in reverse phase；And
And wherein
Second capacitor (C2), the 4th capacitor (C4) and amplifier (AMP) are in the second tube core.
2. isolation circuit according to claim 1, wherein the input terminal of the amplifier (AMP) includes first input end
With the second input terminal, and wherein,
The second end of the main isolating capacitor (C1) is connected to the first end of second capacitor (C2) and the amplifier
(AMP) first input end；
The second end of the secondary isolating capacitor (C3) is connected to the first end of the 4th capacitor (C4) and the amplifier
(AMP) the second input terminal.
3. isolation circuit according to claim 1 further comprises that latch (L1), the latch (L1) include first
Input terminal, the second input terminal and output end,
The second end of the main isolating capacitor (C1) is connected to the first input end of the latch (L1)；
The second end of the secondary isolating capacitor (C3) is connected to the second input terminal of the latch (L1)；
The output end of the latch (L1) is connected to the input terminal of the amplifier (AMP).
4. isolation circuit according to claim 1 further comprises phase inverter (12), the input terminal of the phase inverter (12)
One be connected in the first end of the main isolating capacitor (C1) and the first end of the secondary isolating capacitor (C2), to connect
Receive the input of the isolating capacitor；And the output end of the phase inverter (12) is connected to the of the main isolating capacitor (C1)
Another in the first end of one end and the secondary isolating capacitor (C2)；The phase inverter (12) is in first tube core.
5. isolation circuit according to claim 2 further comprises phase inverter (12), the input terminal of the phase inverter (12)
One be connected in the first end of the main isolating capacitor (C1) and the first end of the secondary isolating capacitor (C2), to connect
Receive the input of the isolating capacitor；And the output end of the phase inverter (12) is connected to the of the main isolating capacitor (C1)
Another in the first end of one end and the secondary isolating capacitor (C2)；The phase inverter (12) is in first tube core.
6. isolation circuit according to claim 3 further comprises phase inverter (12), the input terminal of the phase inverter (12)
One be connected in the first end of the main isolating capacitor (C1) and the first end of the secondary isolating capacitor (C2), to connect
Receive the input of the isolating capacitor；And the output end of the phase inverter (12) is connected to the of the main isolating capacitor (C1)
Another in the first end of one end and the secondary isolating capacitor (C2)；The phase inverter (12) is in first tube core.
7. isolation circuit according to claim 4 further comprises buffer (11), the output end of the buffer (11)
It is connected to the input terminal of the phase inverter (12), and is connected to the first end of the main isolating capacitor (C1) and the secondary isolation
One in the first end of capacitor (C2)；The buffer (11) is in first tube core.
8. isolation circuit according to claim 5 further comprises buffer (11), the output end of the buffer (11)
It is connected to the input terminal of the phase inverter (12), and is connected to the first end of the main isolating capacitor (C1) and the secondary isolation
One in the first end of capacitor (C2)；The buffer (11) is in first tube core.
9. isolation circuit according to claim 6 further comprises buffer (11), the output end of the buffer (11)
It is connected to the input terminal of the phase inverter (12), and is connected to the first end of the main isolating capacitor (C1) and the secondary isolation
One in the first end of capacitor (C2)；The buffer (11) is in first tube core.
10. according to the isolation circuit described in any one of claim 1-9, wherein the main isolating capacitor (C1) and time
At least one of isolating capacitor (C3) is in first tube core.
11. according to the isolation circuit described in any one of claim 1-9, wherein the main isolating capacitor (C1) and time
At least one of isolating capacitor (C3) is in the second tube core.
12. according to the isolation circuit described in any one of claim 1-9, wherein
The main isolating capacitor (C1) includes the concatenated first main isolating capacitor (C11) and the second main isolating capacitor
(C12), the described first main isolating capacitor (C11) is in first tube core, and the second main isolating capacitor (C12) is in the
In two tube cores；
The secondary isolating capacitor (C3) includes concatenated first time isolating capacitor (C31) and second of isolating capacitor
(C32), the first time isolating capacitor (C31) is in first tube core, and second of isolating capacitor (C32) is in the
In two tube cores.
13. isolation circuit according to claim 12, wherein the first main isolating capacitor (C11) and second master every
Capacitance from capacitor (C12) is equal；The first time isolating capacitor (C31) and second isolating capacitor (C32)
Capacitance is equal.
14. isolation circuit according to claim 1, wherein the ground terminal (GND) is the ground terminal of the second tube core.
15. isolation circuit according to claim 1, wherein the main isolating capacitor (C1) and second capacitor
(C2) ratio between is 1:0 to 1:1000.
16. isolation circuit according to claim 15, wherein the main isolating capacitor (C1) and second capacitor
(C2) ratio between is 1:100.
17. isolation circuit according to claim 1, wherein the main isolating capacitor (C1) and second capacitor
(C2) ratio between is equal to the ratio between the secondary isolating capacitor (C3) and the 4th capacitor (C4).
18. isolation circuit according to claim 1, wherein
The capacitance of the main isolating capacitor (C1) and the secondary isolating capacitor (C3) is equal；And
The capacitance of second capacitor (C2) and the 4th capacitor (C4) is equal.
19. a kind of multichannel isolation circuit, including arranged side by side at least two as described in any one of claim 1-18 every
From circuit.
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201720830285.0U CN207766248U (en) | 2017-07-10 | 2017-07-10 | A kind of isolation circuit |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201720830285.0U CN207766248U (en) | 2017-07-10 | 2017-07-10 | A kind of isolation circuit |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107222195A (en) * | 2017-07-10 | 2017-09-29 | 荣湃半导体（上海）有限公司 | A kind of isolation circuit |
| CN113395064A (en) * | 2021-06-30 | 2021-09-14 | 荣湃半导体（上海）有限公司 | Isolated circuit system and method thereof |
-
2017
- 2017-07-10 CN CN201720830285.0U patent/CN207766248U/en active Active
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107222195A (en) * | 2017-07-10 | 2017-09-29 | 荣湃半导体（上海）有限公司 | A kind of isolation circuit |
| CN113395064A (en) * | 2021-06-30 | 2021-09-14 | 荣湃半导体（上海）有限公司 | Isolated circuit system and method thereof |
| CN113395064B (en) * | 2021-06-30 | 2023-07-21 | 荣湃半导体（上海）有限公司 | Isolation circuit system and method thereof |
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