CN107918439A - APD dark current compensations analog front circuit and APD dark current compensation methods - Google Patents
APD dark current compensations analog front circuit and APD dark current compensation methods Download PDFInfo
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Abstract
The present invention relates to a kind of APD dark current compensations analog front circuit and APD dark current compensation methods, which includes APD opto-electronic conversions sub-circuit 101, APD dark current compensations sub-circuit 102, binary channels matching sub-circuit 103, fully differential amplification sub-circuit 104 and buffering sub-circuit 105；Wherein, the first input end of the binary channels matching sub-circuit 103 and the second input terminal are electrically connected the APD opto-electronic conversions sub-circuit 101 and the APD dark current compensations sub-circuit 102；The fully differential amplification sub-circuit 104 is electrically connected between the binary channels matching sub-circuit 103 and the buffering sub-circuit 105.The present invention uses APD dark current compensation sub-circuits, produce the compensation electric current equal with dark current in APD opto-electronic conversion sub-circuits, and the input terminal of fully differential amplifying circuit is inputted at the same time, it is capable of the ability of suppression common mode signal using differential amplifier circuit, influence of the APD dark current to output voltage is eliminated, and this is simple in structure.
Description
Technical field
The invention belongs to laser radar technique field, more particularly to a kind of APD dark current compensations analog front circuit and APD are dark
Current compensation method.
Background technology
In laser radar system, its receiver module is reception optical echo signal and converts optical signals into telecommunications
Number, receiver module is mainly made of photoelectric converter and analog front circuit.Due to avalanche photodide (avalanche
Photodiode, abbreviation APD) have compared with high detection sensitivity, faint optical signal can be detected；For equal-wattage Laser emission
Device, detection range is remote, the extensive use in laser radar receiver.
However, avalanche photodide under non-illuminated conditions, produces intrinsic electric current, i.e. dark current, cause laser thunder
Certain voltage signal can be also exported in no light up to receiver, easily produces error signal.Before existing laser radar simulation
Terminal circuit technology does not have suitable treatments to APD dark current.
The content of the invention
In order to solve the above-mentioned technical problem, before being simulated An embodiment provides a kind of APD dark current compensations
Terminal circuit.The circuit 100 includes APD opto-electronic conversions sub-circuit 101, APD dark current compensations sub-circuit 102, binary channels matching
Circuit 103, fully differential amplification sub-circuit 104 and buffering sub-circuit 105；Wherein,
The first input end and the second input terminal of binary channels matching sub-circuit 103 are electrically connected APD opto-electronic conversions son electricity
Road 101 and APD dark current compensations sub-circuit 102；
Fully differential amplification sub-circuit 104 is electrically connected between binary channels matching sub-circuit 103 and buffering sub-circuit 105.
In one embodiment of the invention, APD dark current compensations sub-circuit 102 include operational amplifier A MP, can power transformation
Hinder device REXT, first the second metal-oxide-semiconductors of metal-oxide-semiconductor M1 M2, the 3rd metal-oxide-semiconductor M3；Wherein,
Second metal-oxide-semiconductor M2, the first metal-oxide-semiconductor M1 and variable resistance REXTIt is sequentially connected in series in power end VDD and ground terminal GND
Between；
The in-phase input end of operational amplifier A MP is electrically connected reference voltage end Vref, the first MOS of inverting input electrical connection
The source electrode of pipe M1, output terminal are electrically connected the grid of the first metal-oxide-semiconductor M1；
The grid of second metal-oxide-semiconductor M2 is connected with drain electrode；
The grid of 3rd metal-oxide-semiconductor M3 is electrically connected the grid of the second metal-oxide-semiconductor M2, and source electrode electric connection of power supply end VDD, drain conduct
The output terminal of APD dark current compensations sub-circuit 102 is electrically connected the second input terminal of binary channels matching sub-circuit 103.
In one embodiment of the invention, stating binary channels matching sub-circuit 103 includes the first Open-loop amplifier A1, second
Open-loop amplifier A2, the first feedback device X1 and the second feedback device X2；Wherein,
The source electrode electric connection of power supply end VDD of PMOS tube, the source electrode of NMOS tube are electrically connected ground connection in first Open-loop amplifier A1
Hold GND；
The source electrode electric connection of power supply end VDD of PMOS tube, the source electrode of NMOS tube are electrically connected ground connection in second Open-loop amplifier A2
Hold GND；
First feedback device X1 is electrically connected between the input terminal and output terminal of the first Open-loop amplifier A1；
Second feedback device X2 is electrically connected between the input terminal and output terminal of the second Open-loop amplifier A2；
The first input end that the input terminal of first Open-loop amplifier A1 matches sub-circuit 103 for binary channels is electrically connected APD light
Electric conversion sub-circuit 101；Second input terminal electricity of the input terminal of second Open-loop amplifier A2 as binary channels matching sub-circuit 103
Connect APD dark current compensations sub-circuit 102；
It is complete poor that the output terminal of first Open-loop amplifier A1 is electrically connected as the first output terminal of binary channels matching sub-circuit 103
Divide amplification 104 first input end of sub-circuit；The output terminal of second Open-loop amplifier A2 as binary channels matching sub-circuit 103 the
Two output terminals are electrically connected fully differential amplification 104 second input terminal of sub-circuit.
In one embodiment of the invention, the first feedback device X1 and the second feedback device X2 is resistor.
In one embodiment of the invention, fully differential amplification sub-circuit 104 is amplified by the identical fully differential of multiple structures
Device cascades to be formed successively；Wherein,
The in-phase input end of rear stage fully-differential amplifier is electrically connected the reversed-phase output of previous stage fully-differential amplifier；
The inverting input of rear stage fully-differential amplifier is electrically connected the in-phase output end of previous stage fully-differential amplifier.
In one embodiment of the invention, fully-differential amplifier includes the 8th metal-oxide-semiconductor M8, the 9th metal-oxide-semiconductor M9, the tenth
Metal-oxide-semiconductor M10, the 11st metal-oxide-semiconductor M11 and the first current source ID1；Wherein,
Tenth metal-oxide-semiconductor M10, the 8th metal-oxide-semiconductor M8 and the first current source ID1It is sequentially connected in series in power end VDD and ground terminal GND
Between；
11st metal-oxide-semiconductor M11 and the 9th metal-oxide-semiconductor M9 are sequentially connected in series in power end VDD and the 8th metal-oxide-semiconductor M8 and the first electric current
Source ID1Between the node for concatenating formation；
The grid of tenth metal-oxide-semiconductor M10 is electrically connected with drain electrode；
The grid of 11st metal-oxide-semiconductor M11 is electrically connected with drain electrode；
The grid of 9th metal-oxide-semiconductor M9 is the in-phase input end of fully-differential amplifier；
The grid of 8th metal-oxide-semiconductor M8 is the inverting input of fully-differential amplifier；
Tenth metal-oxide-semiconductor M10 concatenates the in-phase output end that the node to be formed is fully-differential amplifier with the 8th metal-oxide-semiconductor M8；
11st metal-oxide-semiconductor M11 concatenates the reversed-phase output that the node to be formed is fully-differential amplifier with the 9th metal-oxide-semiconductor M9.
In one embodiment of the invention, buffering sub-circuit 105 includes the 12nd metal-oxide-semiconductor M12, the 13rd metal-oxide-semiconductor
M13, first resistor R1, second resistance R2 and the second current source ID2；Wherein,
First resistor R1, the 12nd metal-oxide-semiconductor M12 and the second current source ID2It is sequentially connected in series in power end VDD and ground terminal GND
Between；
Second resistance R2 and the 13rd metal-oxide-semiconductor M13 is sequentially connected in series in the electricity of power end VDD and the 12nd metal-oxide-semiconductor M12 and second
Stream source ID2Between the node for concatenating formation；
The grid of 13rd metal-oxide-semiconductor M13 is the in-phase input end of buffering sub-circuit 105；
The grid of 12nd metal-oxide-semiconductor M12 is the inverting input of buffering sub-circuit 105；
First resistor R1 concatenates in-phase output end of the node to be formed for buffering sub-circuit 105 with the 12nd metal-oxide-semiconductor M12；
Second resistance R2 concatenates reversed-phase output of the node to be formed for buffering sub-circuit 105 with the 13rd metal-oxide-semiconductor M13.
In one embodiment of the invention, the resistance value of first resistor R1 and second resistance R2 is 50 Ω or is
75Ω。
In one embodiment of the invention, there is provided a kind of APD dark current compensations method, this method include：
1st step, convert optical signals to electric signal；
2nd step, form compensation electric current according to the electric signal；
3rd step, according to the electric signal with it is described compensation electric current formed doubleway output voltage；
4th step, by the doubleway output voltage amplification and be output in load.
Compared with prior art, the invention has the advantages that：
APD dark current compensations analog front circuit provided by the invention, using APD dark current compensation sub-circuits, produce with
The equal compensation electric current of dark current in APD opto-electronic conversion sub-circuits, and the input terminal of fully differential amplifying circuit is inputted at the same time, utilize
Differential amplifier circuit is capable of the ability of suppression common mode signal, eliminates influence of the APD dark current to output voltage.
Brief description of the drawings
Below in conjunction with attached drawing, the embodiment of the present invention is described in detail.
Fig. 1 is a kind of structure diagram of APD dark current compensations analog front circuit provided in an embodiment of the present invention；
Fig. 2 is a kind of structure diagram of APD dark current compensations sub-circuit provided in an embodiment of the present invention；
Fig. 3 is the structure diagram that a kind of binary channels provided in an embodiment of the present invention matches sub-circuit；
Fig. 4 is the structure diagram that a kind of fully differential provided in an embodiment of the present invention amplifies sub-circuit；
Fig. 5 is a kind of structure diagram of fully-differential amplifier provided in an embodiment of the present invention；
Fig. 6 is a kind of structure diagram for buffering sub-circuit provided in an embodiment of the present invention；
Fig. 7 is a kind of APD dark current compensations method provided in an embodiment of the present invention.
Embodiment
Below in conjunction with the attached drawing in the embodiment of the present invention, the technical solution in the embodiment of the present invention is carried out clear, complete
Site preparation describes, it is clear that described embodiment is only part of the embodiment of the present invention, instead of all the embodiments.It is based on
Embodiment in the present invention, those of ordinary skill in the art are obtained every other without creative efforts
Embodiment, belongs to the scope of protection of the invention.
The present invention is described in further details below in conjunction with the accompanying drawings.
Embodiment one
Fig. 1 is referred to, Fig. 1 is a kind of structure of APD dark current compensations analog front circuit provided in an embodiment of the present invention
Schematic diagram.The circuit 100 includes APD opto-electronic conversions sub-circuit 101, APD dark current compensations sub-circuit 102, binary channels matching
Circuit 103, fully differential amplification sub-circuit 104 and buffering sub-circuit 105；Wherein,
The first input end and the second input terminal of binary channels matching sub-circuit 103 are electrically connected APD opto-electronic conversions son electricity
Road 101 and APD dark current compensations sub-circuit 102；
Fully differential amplification sub-circuit 104 is electrically connected between binary channels matching sub-circuit 103 and buffering sub-circuit 105.
APD dark current compensations analog front circuit provided in this embodiment, using APD dark current compensation sub-circuits, produces
The compensation electric current equal with dark current in APD opto-electronic conversion sub-circuits, and the input terminal of fully differential amplifying circuit is inputted at the same time, profit
It is capable of the ability of suppression common mode signal with differential amplifier circuit, eliminates influence of the APD dark current to output voltage.
Embodiment two
Fig. 2 is referred to, Fig. 2 is a kind of structure diagram of APD dark current compensations sub-circuit provided in an embodiment of the present invention.
The APD dark current compensations sub-circuit 102 includes operational amplifier A MP, variable resistance REXT, the first metal-oxide-semiconductor M1, the second metal-oxide-semiconductor
M2, the 3rd metal-oxide-semiconductor M3；Wherein,
Second metal-oxide-semiconductor M2, the first metal-oxide-semiconductor M1 and variable resistance REXTIt is sequentially connected in series in power end VDD and ground terminal GND
Between；
The in-phase input end of operational amplifier A MP is electrically connected reference voltage end Vref, the first MOS of inverting input electrical connection
The source electrode of pipe M1, output terminal are electrically connected the grid of the first metal-oxide-semiconductor M1；
The grid of second metal-oxide-semiconductor M2 is connected with drain electrode；
The grid of 3rd metal-oxide-semiconductor M3 is electrically connected the grid of the second metal-oxide-semiconductor M2, and source electrode electric connection of power supply end VDD, drain conduct
The output terminal of APD dark current compensations sub-circuit 102 is electrically connected the second input terminal of binary channels matching sub-circuit 103.
Wherein, the first metal-oxide-semiconductor M1 is NMOS tube, and the second metal-oxide-semiconductor M2 and the 3rd metal-oxide-semiconductor M3 are PMOS tube.
In the present embodiment, the second metal-oxide-semiconductor M2 and the 3rd metal-oxide-semiconductor M3 form the circuit structure of current mirror, the advantage is that
With good.Variable resistance REXTIt can be used as external resistor, can be by adjusting variable resistance R in practical applicationEXTResistance value
To match the dark current of arbitrary size.
Embodiment three
Fig. 3 is referred to, Fig. 3 is the structure diagram that a kind of binary channels provided in an embodiment of the present invention matches sub-circuit.Should
Binary channels matching sub-circuit 103 includes the first Open-loop amplifier A1, the second Open-loop amplifier A2, the first feedback device X1 and second
Feedback device X2；Wherein,
First Open-loop amplifier A1 is concatenated by the 5th metal-oxide-semiconductor M5 with the 4th metal-oxide-semiconductor M4 to be formed, in the first Open-loop amplifier A1
The source electrode electric connection of power supply end VDD of PMOS tube, the source electrode of NMOS tube are electrically connected ground terminal GND, the 5th metal-oxide-semiconductor M5 and the 4th MOS
The grid of pipe M4 is connected to form the input terminal of the first Open-loop amplifier A1, and the 5th metal-oxide-semiconductor M5 is connected with the drain electrode of the 4th metal-oxide-semiconductor M4
Form the output terminal of the first Open-loop amplifier A1；
Second Open-loop amplifier A2 is concatenated by the 7th metal-oxide-semiconductor M7 with the 6th metal-oxide-semiconductor M6 to be formed, in the second Open-loop amplifier A2
The source electrode electric connection of power supply end VDD of PMOS tube, the source electrode of NMOS tube are electrically connected ground terminal GND, the 7th metal-oxide-semiconductor M7 and the 6th MOS
The grid of pipe M6 is connected to form the input terminal of the second Open-loop amplifier A2, and the 7th metal-oxide-semiconductor M7 is connected with the drain electrode of the 6th metal-oxide-semiconductor M6
Form the output terminal of the second Open-loop amplifier A2；
First feedback device X1 is electrically connected between the input terminal and output terminal of the first Open-loop amplifier A1；
Second feedback device X2 is electrically connected between the input terminal and output terminal of the second Open-loop amplifier A2；
The first input end that the input terminal of first Open-loop amplifier A1 matches sub-circuit 103 for binary channels is electrically connected APD light
Electric conversion sub-circuit 101；Second input terminal electricity of the input terminal of second Open-loop amplifier A2 as binary channels matching sub-circuit 103
Connect APD dark current compensations sub-circuit 102；
It is complete poor that the output terminal of first Open-loop amplifier A1 is electrically connected as the first output terminal of binary channels matching sub-circuit 103
Divide amplification 104 first input end of sub-circuit；The output terminal of second Open-loop amplifier A2 as binary channels matching sub-circuit 103 the
Two output terminals are electrically connected fully differential amplification 104 second input terminal of sub-circuit.
Preferably, the first feedback device X1 and the second feedback device X2 is resistor.
Example IV
Fig. 4 is referred to, Fig. 4 is the structure diagram that a kind of fully differential provided in an embodiment of the present invention amplifies sub-circuit.Should
Fully differential amplification sub-circuit 104 is cascaded successively by the identical fully-differential amplifier of multiple structures to be formed；Wherein,
The in-phase input end of rear stage fully-differential amplifier is electrically connected the reversed-phase output of previous stage fully-differential amplifier；
The inverting input of rear stage fully-differential amplifier is electrically connected the in-phase output end of previous stage fully-differential amplifier.
In practical applications, can be using the fully-differential amplifier shape of different series according to different amplification factor needs
Help differential amplification sub-circuit 104.In typical applications, the fully-differential amplifier of three cascades of generally use forms fully differential and puts
Big sub-circuit 104.
Embodiment five
Fig. 5 is referred to, Fig. 5 is a kind of structure diagram of fully-differential amplifier provided in an embodiment of the present invention.This is complete poor
Amplifier is divided to include the 8th metal-oxide-semiconductor M8, the 9th metal-oxide-semiconductor M9, the tenth metal-oxide-semiconductor M10, the 11st metal-oxide-semiconductor M11 and the first current source
ID1；Wherein,
Tenth metal-oxide-semiconductor M10, the 8th metal-oxide-semiconductor M8 and the first current source ID1It is sequentially connected in series in power end VDD and ground terminal GND
Between；
11st metal-oxide-semiconductor M11 and the 9th metal-oxide-semiconductor M9 are sequentially connected in series in power end VDD and the 8th metal-oxide-semiconductor M8 and the first electric current
Source ID1Between the node for concatenating formation；
The grid of tenth metal-oxide-semiconductor M10 is electrically connected with drain electrode；
The grid of 11st metal-oxide-semiconductor M11 is electrically connected with drain electrode；
The grid of 9th metal-oxide-semiconductor M9 is the in-phase input end of fully-differential amplifier；
The grid of 8th metal-oxide-semiconductor M8 is the inverting input of fully-differential amplifier；
Tenth metal-oxide-semiconductor M10 concatenates the in-phase output end that the node to be formed is fully-differential amplifier with the 8th metal-oxide-semiconductor M8；
11st metal-oxide-semiconductor M11 concatenates the reversed-phase output that the node to be formed is fully-differential amplifier with the 9th metal-oxide-semiconductor M9.
The 8th metal-oxide-semiconductor M8 and the 9th metal-oxide-semiconductor M9NMOS is managed in the structure, and the tenth metal-oxide-semiconductor M10 and the 11st metal-oxide-semiconductor M11 is
PMOS tube.
Fully-differential amplifier provided in this embodiment, it is small to the advantage is that amplification factor is affected by temperature, and amplification factor is permanent
It is fixed.
Embodiment six
Fig. 6 is referred to, Fig. 6 is a kind of structure diagram for buffering sub-circuit provided in an embodiment of the present invention.The buffer sublayer
Circuit 105 includes the 12nd metal-oxide-semiconductor M12, the 13rd metal-oxide-semiconductor M13, first resistor R1, second resistance R2 and the second current source ID2；
Wherein,
First resistor R1, the 12nd metal-oxide-semiconductor M12 and the second current source ID2It is sequentially connected in series in power end VDD and ground terminal GND
Between；
Second resistance R2 and the 13rd metal-oxide-semiconductor M13 is sequentially connected in series in the electricity of power end VDD and the 12nd metal-oxide-semiconductor M12 and second
Stream source ID2Between the node for concatenating formation；
The grid of 13rd metal-oxide-semiconductor M13 is the in-phase input end of buffering sub-circuit 105；
The grid of 12nd metal-oxide-semiconductor M12 is the inverting input of buffering sub-circuit 105；
First resistor R1 concatenates in-phase output end of the node to be formed for buffering sub-circuit 105 with the 12nd metal-oxide-semiconductor M12；
Second resistance R2 concatenates reversed-phase output of the node to be formed for buffering sub-circuit 105 with the 13rd metal-oxide-semiconductor M13.
Preferably, the resistance value of first resistor R1 and second resistance R2 is 50 Ω or is 75 Ω.
In the structure, the grid of the 12nd metal-oxide-semiconductor M12 and the 13rd metal-oxide-semiconductor M13 respectively constitute buffering sub-circuit 105
First input end and the second input terminal, the first input end and the second input terminal are Differential Input mode, first resistor R1, second
Resistance R2 is matched resistor, the second current source ID2It is that the 12nd metal-oxide-semiconductor M12 and the 13rd metal-oxide-semiconductor M13 provide bias current.
Embodiment seven
Fig. 7 is referred to, Fig. 7 is a kind of APD dark current compensations method provided in an embodiment of the present invention, and this method includes：
1st step, convert optical signals to electric signal；
2nd step, form compensation electric current according to electric signal；
3rd step, according to electric signal with compensation electric current formed doubleway output voltage；
4th step, by doubleway output voltage amplification and be output in load.
Wherein, in step 1, optical signal is received using photoelectric converter, and the optical signal is converted into electric signal, telecommunications
Number it is current signal.The photoelectric converter includes APD units, since APD units itself can form dark current, therefore in electric signal
Including changing the electric signal and dark current that are formed by optical signal.
In step 2, produced and the equal-sized compensation electric current of dark current in step 1 using dark current compensation module.
In step 3, after its purpose is to which the current signal in the 1st step and the 2nd step is converted to voltage signal progress
Resume defeated.
To sum up, specific case used herein is set forth the structure and embodiment of the present invention, and the above is implemented
The explanation of example is only intended to help the method and its core concept for understanding the present invention；Meanwhile for the general technology people of this area
Member, according to the thought of the present invention, there will be changes in specific embodiments and applications, to sum up, in this specification
Appearance should not be construed as limiting the invention, and protection scope of the present invention should be subject to appended claim.
Claims (9)
1. a kind of APD dark current compensations analog front circuit (100), it is characterised in that including APD opto-electronic conversion sub-circuits
(101), APD dark current compensations sub-circuit (102), binary channels matching sub-circuit (103), fully differential amplification sub-circuit (104) and
Buffer sub-circuit (105)；Wherein,
The first input end and the second input terminal of the binary channels matching sub-circuit (103) are electrically connected the APD photoelectricity and turn
Change sub-circuit (101) and the APD dark current compensations sub-circuit (102)；
The fully differential amplification sub-circuit (104) is electrically connected to the binary channels matching sub-circuit (103) and buffer sublayer electricity
Between road (105).
2. APD dark current compensations analog front circuit (100) according to claim 1, it is characterised in that the APD is dark
Current compensation sub-circuit (102) includes operational amplifier (AMP), variable resistance (REXT), the second metal-oxide-semiconductor of the first metal-oxide-semiconductor (M1)
(M2), the 3rd metal-oxide-semiconductor (M3)；Wherein,
Second metal-oxide-semiconductor (M2), first metal-oxide-semiconductor (M1) and the variable resistance (REXT) be sequentially connected in series in power end
(VDD) between ground terminal (GND)；
The in-phase input end of the operational amplifier (AMP) is electrically connected reference voltage end (Vref), inverting input be electrically connected described in
The source electrode of first metal-oxide-semiconductor (M1), output terminal are electrically connected the grid of first metal-oxide-semiconductor (M1)；
The grid of second metal-oxide-semiconductor (M2) is connected with drain electrode；
The grid of 3rd metal-oxide-semiconductor (M3) is electrically connected the grid of second metal-oxide-semiconductor (M2), and source electrode is electrically connected the power end
(VDD), drain electrode is electrically connected the binary channels matching sub-circuit as the output terminal of the APD dark current compensations sub-circuit (102)
(103) the second input terminal.
3. amplifier according to claim 2, it is characterised in that the binary channels matching sub-circuit (103) includes first
Open-loop amplifier (A1), the second Open-loop amplifier (A2), the first feedback device (X1) and the second feedback device (X2)；Wherein,
The source electrode of PMOS tube is electrically connected the power end (VDD), the source electrode electricity of NMOS tube in first Open-loop amplifier (A1)
Connect the ground terminal (GND)；
The source electrode of PMOS tube is electrically connected the power end (VDD), the source electrode electricity of NMOS tube in second Open-loop amplifier (A2)
Connect the ground terminal (GND)；
First feedback device (X1) is electrically connected between the input terminal and output terminal of first Open-loop amplifier (A1)；
Second feedback device (X2) is electrically connected between the input terminal and output terminal of second Open-loop amplifier (A2)；
The first input end that the input terminal of first Open-loop amplifier (A1) matches sub-circuit (103) for the binary channels is electrically connected
Connect the APD opto-electronic conversions sub-circuit (101)；The input terminal of second Open-loop amplifier (A2) is matched as the binary channels
Second input terminal of sub-circuit (103) is electrically connected the APD dark current compensations sub-circuit (102)；
First output terminal electricity of the output terminal of first Open-loop amplifier (A1) as binary channels matching sub-circuit (103)
Connect described fully differential amplification sub-circuit (104) first input end；The output terminal of second Open-loop amplifier (A2) is as institute
The second output terminal for stating binary channels matching sub-circuit (103) is electrically connected fully differential amplification (104) second input terminal of sub-circuit.
4. APD dark current compensations analog front circuit (100) according to claim 3, it is characterised in that described first is anti-
It is resistor that device (X1), which is presented, with the second feedback device (X2).
5. APD dark current compensations analog front circuit (100) according to claim 1, it is characterised in that the fully differential
Amplification sub-circuit (104) is cascaded successively by the identical fully-differential amplifier of multiple structures to be formed；Wherein,
The in-phase input end of rear stage fully-differential amplifier is electrically connected the reversed-phase output of previous stage fully-differential amplifier；
The inverting input of rear stage fully-differential amplifier is electrically connected the in-phase output end of previous stage fully-differential amplifier.
6. APD dark current compensations analog front circuit (100) according to claim 5, it is characterised in that the fully differential
Amplifier includes the 8th metal-oxide-semiconductor (M8), the 9th metal-oxide-semiconductor (M9), the tenth metal-oxide-semiconductor (M10), the 11st metal-oxide-semiconductor (M11) and the first electricity
Stream source (ID1)；Wherein,
Tenth metal-oxide-semiconductor (M10), the 8th metal-oxide-semiconductor (M8) and the first current source (ID1) be sequentially connected in series in the electricity
Between source (VDD) and the ground terminal (GND)；
11st metal-oxide-semiconductor (M11) and the 9th metal-oxide-semiconductor (M9) are sequentially connected in series in the power end (VDD) and described the
Eight metal-oxide-semiconductors (M8) and the first current source (ID1) concatenation formed node between；
The grid of tenth metal-oxide-semiconductor (M10) is electrically connected with drain electrode；
The grid of 11st metal-oxide-semiconductor (M11) is electrically connected with drain electrode；
The grid of 9th metal-oxide-semiconductor (M9) is the in-phase input end of the fully-differential amplifier；
The grid of 8th metal-oxide-semiconductor (M8) is the inverting input of the fully-differential amplifier；
It is the same of the fully-differential amplifier that tenth metal-oxide-semiconductor (M10), which concatenates the node formed with the 8th metal-oxide-semiconductor (M8),
Phase output terminal；
It is the fully-differential amplifier that 11st metal-oxide-semiconductor (M11), which concatenates the node formed with the 9th metal-oxide-semiconductor (M9),
Reversed-phase output.
7. APD dark current compensations analog front circuit (100) according to claim 1, it is characterised in that the buffer sublayer
Circuit (105) includes the 12nd metal-oxide-semiconductor (M12), the 13rd metal-oxide-semiconductor (M13), first resistor (R1), second resistance (R2) and the
Two current source (ID2)；Wherein,
The first resistor (R1), the 12nd metal-oxide-semiconductor (M12) and the second current source (ID2) be sequentially connected in series in the electricity
Between source (VDD) and the ground terminal (GND)；
The second resistance (R2) is sequentially connected in series in the power end (VDD) and the described tenth with the 13rd metal-oxide-semiconductor (M13)
Two metal-oxide-semiconductors (M12) and the second current source (ID2) concatenation formed node between；
The grid of 13rd metal-oxide-semiconductor (M13) is the in-phase input end for buffering sub-circuit (105)；
The grid of 12nd metal-oxide-semiconductor (M12) is the inverting input for buffering sub-circuit (105)；
It is the buffering sub-circuit (105) that the first resistor (R1), which concatenates the node formed with the 12nd metal-oxide-semiconductor (M12),
In-phase output end；
It is the buffering sub-circuit (105) that the second resistance (R2), which concatenates the node formed with the 13rd metal-oxide-semiconductor (M13),
Reversed-phase output.
8. APD dark current compensations analog front circuit (100) according to claim 7, it is characterised in that first electricity
The resistance value of resistance (R1) and the second resistance (R2) is 50 Ω or is 75 Ω.
A kind of 9. APD dark current compensations method, it is characterised in that this method includes：
1st step, convert optical signals to electric signal；
2nd step, form compensation electric current according to the electric signal；
3rd step, according to the electric signal with it is described compensation electric current formed doubleway output voltage；
4th step, by the doubleway output voltage amplification and be output in load.
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