CN109002075B - Base current mirror circuit, RSSI circuit and chip of bipolar transistor - Google Patents

Base current mirror circuit, RSSI circuit and chip of bipolar transistor Download PDF

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Publication number
CN109002075B
CN109002075B CN201710423128.2A CN201710423128A CN109002075B CN 109002075 B CN109002075 B CN 109002075B CN 201710423128 A CN201710423128 A CN 201710423128A CN 109002075 B CN109002075 B CN 109002075B
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circuit
current
mirror
bipolar transistor
current mirror
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CN109002075A (en
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孟钒
李威
李旋
李小勇
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Shanghai Muju Microelectronics Co., Ltd
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Suzhou Hanchen Technology Co Ltd
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    • G—PHYSICS
    • G05—CONTROLLING; REGULATING
    • G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
    • G05F3/00—Non-retroactive systems for regulating electric variables by using an uncontrolled element, or an uncontrolled combination of elements, such element or such combination having self-regulating properties
    • G05F3/02—Regulating voltage or current
    • G05F3/08—Regulating voltage or current wherein the variable is dc
    • G05F3/10—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics
    • G05F3/16—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics being semiconductor devices
    • G05F3/20—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics being semiconductor devices using diode- transistor combinations
    • G05F3/26—Current mirrors

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  • General Physics & Mathematics (AREA)
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  • Automation & Control Theory (AREA)
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Abstract

The invention discloses a base current mirror circuit, an RSSI circuit and a chip of a bipolar transistor, wherein the base current mirror circuit is used for mirroring the base current of the bipolar transistor to be mirrored and comprises a circuit input end, a circuit output end, the bipolar transistor to be mirrored, a clamping circuit, a first current mirror, a first current source, a second current source and a first load circuit, wherein the circuit input end is led out by a collector of the bipolar transistor to be mirrored; and the clamping circuit is used for clamping the voltages of the collector electrode of the bipolar transistor to be mirrored and the collector electrode of the mirror image bipolar transistor. The invention can copy three parts of current of the input current of the trans-impedance amplifier in proportion, and the copied current is used as the received signal strength indication information. The RSSI circuit provided by the invention has higher precision and can meet the application requirements of a PIN type photodiode and an APD type photodiode.

Description

Base current mirror circuit, RSSI circuit and chip of bipolar transistor
Technical Field
The invention belongs to the technical field of integrated circuits, and particularly relates to a base current mirror circuit, an RSSI (Received Signal Strength Indication) circuit and a chip of a bipolar transistor.
Background
As shown in fig. 1, three components constitute a simple optical fiber communication system, and the three components are respectively: (1) an opto-electrical converter, such as a laser 10, which converts an electrical signal into an optical signal; (2) an optical fiber 20 for transmitting light generated by the laser; (3) photodetectors, such as photodiode 30, which are sensitive to the light of the fiber optic termination and capable of converting optical signals into electrical signals, are commonly classified into PIN type photodiodes and APD type photodiodes. The optical signal energy will generate loss before reaching the photodiode at the far end through the optical fiber, and in order to facilitate signal processing by a subsequent circuit, the photodiode converts the light intensity into current according to a certain proportion, and then the current needs to be converted into voltage through a TIA (transimpedance amplifier). FIG. 2 is a circuit diagram of a conventional TIA, IinIs the input current of TIA, which is numerically equal to Ib、IRf、IDCRThe sum of the three, wherein IbIs the current, I, flowing through the base of a bipolar transistor Q2RfIs passed through a resistor RfCurrent of (I)DCRIs the current flowing through the collector of bipolar transistor Q1. In the application of the transimpedance amplifier, it is usually necessary to monitor the received signal strength, and a module capable of implementing this function is called an RSSI circuit, and some TIA chips also include the RSSI circuit inside in addition to the TIA circuit shown in fig. 2.
The photodiode requires a suitable bias voltage to operate. As shown in fig. 3, the PIN photodiode requires a low bias voltage, so the required bias voltage is usually generated inside the TIA chip 4, and the TIA chip 4 includes a PIN bias circuit and a TIA circuit. However, the APD photodiode requires a high bias voltage and cannot be realized inside a TIA chip. As shown in fig. 4, the bias voltage for the APD type photodiode is typically provided by an APD type bias circuit external to the TIA chip 4'. A common PIN type bias circuit is realized by adding a resistor between a cathode PIN of a photodiode and VDD in a TIA chip, and RSSI information can be obtained by measuring the voltage of the cathode of the photodiode; another common PIN-type photodiode biasing circuit is shown in fig. 5, where a point a in fig. 5 is connected to a cathode PIN of a PIN-type photodiode, and RSSI information can also be obtained by copying a current in M0, that is, a current flowing through the PIN-type photodiode, through a current mirror in fig. 5. In the two cases, the RSSI information can be acquired by means of a PIN type bias circuit inside the TIA chip, but since the APD type photodiode is biased by an external voltage, for the TIA chip externally connected with the APD type photodiode, the RSSI information acquisition mode similar to that of the PIN type photodiode cannot be realized inside the chip, that is, the RSSI circuit function cannot be realized inside the TIA chip.
Disclosure of Invention
The invention aims to overcome the defect that the RSSI circuit function aiming at the APD type photodiode cannot be realized inside a TIA chip in the prior art, and provides a base current mirror circuit, an RSSI circuit and a chip of a bipolar transistor, which can test the base current of the bipolar transistor in the TIA circuit and further realize the received signal strength indication function aiming at the APD type photodiode inside the TIA chip.
The invention solves the technical problems through the following technical scheme:
a base current mirror circuit of a bipolar transistor is characterized by being used for mirroring a base current of the bipolar transistor to be mirrored and comprising a circuit input end, a circuit output end, the bipolar transistor to be mirrored, a clamping circuit, a first current mirror, a first current source, a second current source and a first load circuit, wherein the circuit input end of the base current mirror circuit is led out from a collector of the bipolar transistor to be mirrored;
the clamping circuit comprises a first input end, a second input end and an output end, the first input end of the clamping circuit is electrically connected with the circuit input end of the base current mirror circuit, the second input end of the clamping circuit is electrically connected with the collector of the mirror bipolar transistor, and the output end of the clamping circuit is electrically connected with the first current mirror;
the clamping circuit is used for clamping the voltages of the collector electrode of the bipolar transistor to be mirrored and the collector electrode of the mirror image bipolar transistor;
the input end of the first current mirror, the base electrode of the mirror bipolar transistor and one end of the first current source are electrically connected;
the output end of the first current mirror, one end of the second current source and the input end of the first load circuit are electrically connected;
the output end of the first load circuit is electrically connected with the circuit output end of the base current mirror circuit.
In the scheme, the mirror image bipolar transistor and the bipolar transistor to be mirrored are the same type of bipolar transistor, the collector voltages of the mirror image bipolar transistor and the bipolar transistor to be mirrored are equal through the clamping circuit, the proportional relation of the base currents of the mirror image bipolar transistor and the bipolar transistor to be mirrored can be further realized, the mirror image output is further carried out on the base current of the mirror image bipolar transistor, and finally the base current of the bipolar transistor to be mirrored is copied at the output end of the circuit.
In this scheme, the first load circuit is used for outputting the current output by the first current mirror, and the current can be used for testing.
In the scheme, the base current of the bipolar transistor to be mirrored can be copied at the output end of the circuit through the base current mirror circuit under the condition that the base current of the bipolar transistor to be mirrored is not influenced. When the scheme is used in the TIA circuit in fig. 2, the base current of the bipolar transistor Q2 can be copied, and the current output by the output end of the circuit can be used for acquiring RSSI information.
Preferably, the clamping circuit includes a differential input single-ended output amplifier, a non-inverting input terminal of the amplifier is the first input terminal of the clamping circuit, an inverting input terminal of the amplifier is the second input terminal of the clamping circuit, and an output terminal of the amplifier is an output terminal of the clamping circuit.
In the scheme, the amplifier has the function of clamping the voltages of the collector electrodes of the mirror image bipolar transistor and the bipolar transistor to be mirrored, so that the voltage values of the two are equal.
Preferably, the first current mirror comprises a first MOS (metal-oxide-semiconductor) transistor and a second MOS transistor, and the output terminal of the clamp circuit, the gate of the first MOS transistor and the gate of the second MOS transistor are electrically connected; the drain electrode of the first MOS tube is electrically connected with the base electrode of the mirror image bipolar transistor; the drain electrode of the second MOS tube is electrically connected with the input end of the first load circuit;
the ratio of the width-length ratio of the first MOS transistor to the width-length ratio of the second MOS transistor is equal to the ratio of the current of the first current source to the current of the second current source.
In the scheme, the grids of the first MOS tube and the second MOS tube are connected to form a first current mirror, the ratio of the width-length ratio of the first MOS tube to the width-length ratio of the second MOS tube is equal to the ratio of the current of the first current source to the current of the second current source, and the current output by the drain electrode of the second MOS tube can be equal to the drain current of the first MOS tube.
Preferably, the first load circuit includes a second current mirror, an input terminal of the second current mirror is connected to an input terminal of the first load circuit, an output terminal of the second current mirror is output to an output terminal of the first load circuit, and a ratio of a current of an input branch of the second current mirror to a current of an output branch of the second current mirror is 1: n, wherein n is a positive real number.
In the scheme, the first load circuit is realized by the second current mirror, and the second current mirror is used for carrying out n times of mirror image output on the current output by the first current mirror.
Preferably, the collector of the bipolar transistor to be mirrored is connected in series with the first load, and the collector of the bipolar transistor to be mirrored is connected in series with the second load.
In the scheme, the types of the first load and the second load can be selected according to the circuit requirements.
Preferably, the first load and the second load are both resistors.
In this scheme, a resistive load is employed.
Preferably, the emitter of the bipolar transistor to be mirrored is connected in series with a first resistor, the resistance of the first resistor is R1, the emitter of the bipolar transistor to be mirrored is connected in series with a second resistor, the resistance of the second resistor is R2, and the area of the emitter of the bipolar transistor to be mirrored is aQ1The area of an emitter of the mirror image bipolar transistor is AQ2R2/R1 equal to AQ2/AQ1。
In the scheme, if the source electrode of the bipolar transistor to be mirrored is provided with the first resistor for suppressing noise, the source electrode of the bipolar transistor to be mirrored must be provided with the second matched resistor, and the resistance ratio of the two resistors is adapted to the area ratio of the emitting electrodes of the two transistors, so that the base currents of the two transistors are in an expected proportional relationship.
The RSSI circuit of the present invention is used for a transimpedance amplifier including a first bipolar transistor, a second bipolar transistor and a third resistor, and an input current of the transimpedance amplifier is divided into a collector current of the first bipolar transistor, a current of the third resistor and a base current of the second bipolar transistor,
the RSSI circuit comprises a resistance current mirror circuit, a collector current mirror circuit and the base current mirror circuit of the bipolar transistor;
the second bipolar transistor is the bipolar transistor to be mirrored;
the resistance current mirror circuit is used for mirroring the current of the third resistor;
the collector current mirror circuit is used for mirroring the current of the collector of the first bipolar transistor.
In the scheme, under the condition that the normal work of the trans-impedance amplifier is not influenced, the current of the third resistor, the collector current of the first bipolar transistor and the base current of the second bipolar transistor are respectively output in a mirror mode through the resistor current mirror circuit, the collector current mirror circuit and the base current mirror circuit, and then the RSSI information is obtained through the three output currents.
Preferably, the collector current mirror circuit includes a third bipolar transistor and a third current mirror, a gate of the third bipolar transistor is electrically connected to a gate of the first bipolar transistor, and the third current mirror is configured to mirror a collector current of the third bipolar transistor.
In this embodiment, the gate of the third bipolar transistor is electrically connected to the gate of the first bipolar transistor, so that the collector current of the first bipolar transistor can be reproduced at the collector of the third bipolar transistor and can be output through the third current mirror.
Preferably, the resistance current mirror circuit is used for mirroring the current of the resistor to be mirrored, and comprises a first input end of the mirror circuit, a second input end of the mirror circuit, an output end of the mirror circuit and a common source circuit with a differential structure and source negative feedback;
the first input end of the mirror image circuit and the second input end of the mirror image circuit are respectively led out from two ends of the resistor to be mirrored;
the common source circuit comprises a mirror resistor, a first input end of the common source circuit, a second input end of the common source circuit, a first output end of the common source circuit and a second output end of the common source circuit; the first input end of the common source circuit is electrically connected with the first input end of the mirror image circuit, and the second input end of the common source circuit is electrically connected with the second input end of the mirror image circuit; the current difference between the first output end of the common source circuit and the second output end of the common source circuit is equal to the current flowing through the mirror resistor;
the resistance current mirror circuit further comprises a fourth current mirror, a fifth current mirror, a sixth current mirror and a second load circuit, wherein the second load circuit comprises a load input end and a load output end;
the input end of the fourth current mirror is electrically connected with the first output end of the common source circuit, and the output end of the fourth current mirror is electrically connected with the load input end;
the input end of the fifth current mirror is electrically connected with the second output end of the common source circuit, and the output end of the fifth current mirror is electrically connected with the input end of the sixth current mirror;
the output end of the sixth current mirror is electrically connected with the load input end;
the ratio of the current of the input branch of the fifth current mirror to the current of the output branch of the fifth current mirror is 1: m, the ratio of the current of the input branch of the sixth current mirror to the current of the output branch of the sixth current mirror is 1: k, the ratio of the current of the input branch of the fourth current mirror to the current of the output branch of the fourth current mirror is 1: (m × k);
the load output end is electrically connected with the output end of the mirror image circuit, and the ratio of the current of the load output end to the current of the load input end is 1: n; m, k and n are all positive real numbers.
In the scheme, the voltage difference between two ends of the mirror resistor is equal to the voltage difference between two ends of the mirror resistor to be mirrored under an ideal state, and the current on the mirror resistor to be mirrored can be copied to the mirror resistor through the common source circuit, specifically to the first output end of the common source circuit and the common source circuitThe current difference of the second output terminal is equal to the current flowing through the mirror resistor. On the basis, the output of the positive real number multiple of the current on the mirror resistor is realized by combining three current mirrors, and the current can be measured through the output end of the load circuit. When the scheme is used in a TIA circuit in FIG. 2, the resistor R can be copiedfCurrent I ofRfAt this time, the current output by the output end of the mirror circuit can be used for obtaining the RSSI information.
Preferably, the common-source circuit further comprises a third MOS transistor, a fourth MOS transistor, a third current source, and a fourth current source; the current provided by the third current source is equal to the current provided by the fourth current source;
the grid electrode of the third MOS tube is electrically connected with the first input end of the mirror image circuit, and the grid electrode of the fourth MOS tube is electrically connected with the second input end of the mirror image circuit;
the source electrode of the third MOS tube, one end of the third current source and one end of the mirror resistor are electrically connected, and the source electrode of the fourth MOS tube, one end of the fourth current source and the other end of the mirror resistor are electrically connected;
the drain electrode of the third MOS tube is electrically connected with the first output end of the common source circuit; and the drain electrode of the fourth MOS tube is electrically connected with the second output end of the common source circuit.
In the scheme, the currents provided by the third current source and the fourth current source are equal, the difference value between the grid voltage of the third MOS tube and the grid voltage of the fourth MOS tube is the voltage value on the mirror resistor, namely the voltage difference value between two ends of the resistor to be mirrored, so that the difference value between the current of the drain electrode of the third MOS tube and the current of the drain electrode of the fourth MOS tube is the current on the mirror resistor, the current of the drain electrode of the third MOS tube is output to the load input end in m x k times of the mirror image through the fourth current mirror, the current of the drain electrode of the fourth MOS tube is output to the load input end in k times of the mirror image through the fifth current mirror after being output to the sixth current mirror in m times of the mirror image, and the current on the mirror resistor in m x k times is obtained at the load input end.
Preferably, the second load circuit includes a fifth current source and a seventh current mirror, an input terminal of the seventh current mirror is electrically connected to the load input terminal and one terminal of the fifth current source, an output terminal of the seventh current mirror is electrically connected to the load output terminal, and a current ratio between an input branch of the seventh current mirror and an output branch of the seventh current mirror is 1: n is the same as the formula (I).
In the scheme, the second load circuit is realized by a fifth current source and a seventh current mirror, and the current output by the output end of the seventh current mirror can be used for obtaining the RSSI information.
Preferably, the resistance current mirror circuit further comprises a source follower, and the source follower is connected in series between the resistance to be mirrored and the common source circuit;
the source follower comprises a first follower input end, a second follower input end, a first follower output end and a second follower output end;
the first input end of the follower is electrically connected with the first input end of the mirror image circuit, and the second input end of the follower is electrically connected with the second input end of the mirror image circuit;
the first output end of the follower is electrically connected with the first input end of the common source circuit, and the second output end of the follower is electrically connected with the second input end of the common source circuit;
the source follower is used for adjusting the voltage of the first input end of the follower and the second input end of the follower to adapt to the voltage of the common source circuit.
In the scheme, the source electrode follower can adjust the voltage of two points of the first input end of the mirror image circuit and the second input end of the mirror image circuit so as to adapt to the requirement of a subsequent circuit.
Preferably, the source follower comprises a first branch and a second branch;
the first branch circuit comprises a sixth current source and a fifth MOS tube which are connected between a power supply and the ground in series, the source electrode of the fifth MOS tube is electrically connected with the sixth current source, and the grid electrode of the fifth MOS tube is electrically connected with the first input end of the follower;
the second branch circuit comprises a seventh current source and a sixth MOS tube which are connected between a power supply and the ground in series, the source electrode of the sixth MOS tube is electrically connected with the seventh current source, and the grid electrode of the sixth MOS tube is electrically connected with the second input end of the follower;
the current provided by the sixth current source is equal to the current provided by the seventh current source.
In the scheme, the source electrode follower is realized by two MOS tubes and two current sources with the same current value, the first input end of the follower and the second input end of the follower are respectively connected to the grids of the two MOS tubes, and the output voltage of the first output end of the follower and the second output end of the follower is controlled by controlling the current values of the two current sources or the width-length ratio of the two MOS tubes.
The invention also provides a chip which comprises the transimpedance amplifier and is characterized by also comprising the RSSI circuit.
In the scheme, the chip integrates the transimpedance amplifier and the RSSI circuit, the RSSI circuit can perform mirror image output on the input current of the transimpedance amplifier, and the current output by the mirror image is used as received signal strength indication information. The RSSI circuit in the chip provided by the scheme has higher precision and can meet the application requirements of a PIN type photodiode and an APD type photodiode.
The positive progress effects of the invention are as follows: the base current mirror circuit, the RSSI circuit and the chip of the bipolar transistor can copy three parts of current of input current of a trans-impedance amplifier, namely collector current of a first bipolar transistor, current of a third resistor and base current of a second bipolar transistor in proportion, and the copied current is used as received signal strength indication information. The RSSI circuit provided by the invention has higher precision and can meet the application requirements of a PIN type photodiode and an APD type photodiode.
Drawings
Fig. 1 is a schematic diagram of a simple optical fiber communication system in the prior art.
Fig. 2 is a circuit diagram of a TIA of the prior art.
Fig. 3 is a schematic diagram of the operation of a PIN photodiode and a TIA chip in the prior art.
Fig. 4 is a schematic diagram of the operation of an APD photodiode and a TIA chip in the prior art.
Fig. 5 is a circuit diagram of a conventional PIN photodiode biasing circuit in the prior art.
Fig. 6 is a circuit diagram of a base current mirror of the bipolar transistor in embodiment 1 of the present invention.
Fig. 7 is a schematic diagram of an RSSI circuit module in embodiment 2 of the present invention.
Fig. 8 is a circuit diagram of an implementation of the collector current mirror circuit 303 in fig. 7.
Fig. 9 is a block diagram of an implementation of the resistor current mirror circuit 302 of fig. 7.
Fig. 10 is a circuit diagram of an embodiment of the source follower 3026 in fig. 9.
Fig. 11 is a circuit diagram of an implementation of the common source circuit 3024 in fig. 9.
Fig. 12 is a circuit diagram of an implementation of the second load circuit 3025 in fig. 9.
Fig. 13 is a circuit diagram of an implementation of the resistor current mirror circuit 302 in fig. 7.
Fig. 14 is a circuit diagram of a base current mirror of a bipolar transistor according to embodiment 4 of the present invention.
Fig. 15 is a circuit diagram of an implementation of the source follower 3026 in embodiment 5 of the invention.
Fig. 16 is a circuit diagram of an implementation of the second load circuit 3025 in embodiment 6 of the present invention.
Fig. 17 is a circuit diagram of a base current mirror of the bipolar transistor according to embodiment 7 of the present invention.
Detailed Description
The invention is further illustrated by the following examples, which are not intended to limit the scope of the invention.
Example 1
As shown in fig. 6, the circuit comprises a single-stage common emitter amplifier circuit 2 and a base current mirror circuit 1 of a bipolar transistor for mirroring the base current I of the bipolar transistor Q4 to be mirroredb1. In which the bipolar transistor isThe base current mirror circuit 1 comprises a circuit input terminal 101, a circuit output terminal 102, a mirror bipolar transistor Q5, a clamping circuit 103, a first current mirror 104, and a first current source Ic1A second current source Ic2And a first load circuit 105. The circuit input end 101 of the base current mirror circuit 1 is led out from the collector of the bipolar transistor Q4 to be mirrored, and the circuit output end 102 outputs the output current IOUT1. The bipolar transistor Q4 to be mirrored and the bipolar transistor Q5 to be mirrored are both NPN-type bipolar transistors.
The clamp circuit 103 comprises a first input 1031, a second input 1032 and an output 1033, the first input 1031 of the clamp circuit 103 being electrically connected to the circuit input 101 of the base current mirror circuit 1, the second input 1032 of the clamp circuit 103 being electrically connected to the collector of the mirror bipolar transistor Q5, the output of the clamp circuit 103 being electrically connected to the first current mirror 104. The clamp circuit 103 is used to clamp the voltage at the collector of the bipolar transistor Q4 to be mirrored and the collector of the mirror bipolar transistor Q5.
The input terminal 1041 of the first current mirror 104, the base of the mirror bipolar transistor Q5, and the first current source Ic1Is electrically connected with one end of the first connecting rod; the output terminal 1042 of the first current mirror 104 and the second current source Ic2Is electrically connected to the input 1051 of the first load circuit 105; a first current source Ic1And a second current source Ic2The other ends of the two are all grounded.
The output 1052 of the first load circuit 105 is electrically connected to the circuit output 102 of the base current mirror circuit 1.
In this embodiment, the clamping circuit 103 includes a differential-input single-ended-output amplifier AMP1, a non-inverting input terminal of the amplifier AMP1 is a first input terminal 1031 of the clamping circuit 103, an inverting input terminal of the amplifier AMP1 is a second input terminal 1032 of the clamping circuit 103, and an output terminal of the amplifier AMP1 is an output terminal 1033 of the clamping circuit 103.
In this embodiment, the first current mirror 104 includes a first MOS transistor M1 and a second MOS transistor M2, and both the first MOS transistor M1 and the second MOS transistor M2 are PMOS transistors. The output terminal 1033 of the clamping circuit 103, the gate of the first MOS transistor M1 and the second MOS transistor M1The grid of the OS tube M2 is electrically connected; the drain electrode of the first MOS transistor M1 is electrically connected with the base electrode of the mirror image bipolar transistor Q5; the drain of the second MOS transistor M2 is electrically connected to the input 1051 of the first load circuit 105. The ratio of the width-length ratio of the first MOS transistor M1 to the width-length ratio of the second MOS transistor M2 is equal to the first current source Ic1Current of and a second current source Ic2The ratio of the currents of (a).
In this embodiment, the first load circuit 105 includes a second current mirror CM2, an input terminal of the second current mirror CM2 is connected to an input terminal 1051 of the first load circuit 105, an output terminal of the second current mirror CM2 is output to an output terminal 1052 of the first load circuit 105, a ratio of a current of an input branch of the second current mirror CM2 to a current of an output branch of the second current mirror CM2 is 1: n, where n is a positive real number.
In this embodiment, the collector of the bipolar transistor Q4 to be mirrored is connected in series with the first load and has a resistance Ra, and the collector of the bipolar transistor Q5 to be mirrored is connected in series with the second load and has a resistance Rb.
In this embodiment, the emitter of the bipolar transistor Q4 to be mirrored is connected in series with a first resistor, the resistance of the first resistor is R1, the emitter of the bipolar transistor Q5 to be mirrored is connected in series with a second resistor, the resistance of the second resistor is R2, and the area of the emitter of the bipolar transistor Q4 to be mirrored is aQ3The emitter of the mirror bipolar transistor Q5 has an area AQ4R2/R1 equal to AQ4/AQ3。
In this embodiment, if the single-stage common emitter amplifier circuit does not have the first resistor, the second resistor can be omitted; the first load and the second load are both resistive loads, and other types of loads are also possible. The base current of the bipolar transistor Q4 to be mirrored can be copied by the base current mirror circuit 1 of the bipolar transistor.
In this embodiment, the output current IOUT1The expression is [ (n x I)b1*Ic2*Ra)/(Ic1*Rb)]。
Example 2
As shown in fig. 7, the present embodiment further provides an RSSI circuit 3 for the transimpedance amplifier shown in fig. 2, which includes a first pairA bipolar transistor Q1, a second bipolar transistor Q2, and a third resistor RfInput current I of transimpedance amplifierinDivided into collector currents I of a first bipolar transistor Q1DCRA third resistor RfCurrent of (I)RfAnd base current I of second bipolar transistor Q2b。
The RSSI circuit 3 includes a resistance current mirror circuit 302, a collector current mirror circuit 303, and a base current mirror circuit 301, wherein the base current mirror circuit 301 is implemented by using the base current mirror circuit 1 of the bipolar transistor in embodiment 1. The second bipolar transistor Q2 corresponds to the bipolar transistor Q4 to be mirrored in fig. 6. The resistor current mirror circuit 302 is used for mirroring the third resistor RfCurrent of (I)RfTo output the second output current I in FIG. 7OUT2(ii) a The collector current mirror circuit 303 is for mirroring the current I of the collector of the first bipolar transistor Q1DCRTo output the third output current I in FIG. 7OUT3In FIG. 7, the base current mirror circuit 301 mirrors the base current I of the second bipolar transistor Q2bThe mirror image output is the first output current IOUT1(ii) a The resulting three output currents are used to generate RSSI information.
In this embodiment, as shown in fig. 8, the collector current mirror circuit 301 includes a third bipolar transistor Q3 and a third current mirror CM3, the gate of the third bipolar transistor Q3 is electrically connected to the gate of the first bipolar transistor Q1 in fig. 2, and the third current mirror CM3 is used for mirroring the collector current of the third bipolar transistor Q3 to output a third output current IOUT3。
In this embodiment, a block diagram of a specific implementation module of the resistor current mirror circuit 302 is shown in fig. 9, and is used for mirroring a resistor to be mirrored (a third resistor R in fig. 2)f) The resistor current mirror circuit 302 includes a mirror circuit first input terminal 3021, a mirror circuit second input terminal 3022, a mirror circuit output terminal 3023, a source follower 3026, a common source circuit with source degeneration in a differential configuration 3024, a fourth current mirror CM4, a fifth current mirror CM5, a sixth current mirror CM6, and a second load circuit 3025. Mirror image circuit first input terminal 3021 and mirror image circuitThe second input terminals 3022 are respectively provided with third resistors RfIs led out from both ends.
The source follower 3026 includes a follower first input a1, a follower second input a2, a follower first output A3, and a follower second output a 4. The source follower 3026 is used to adjust the voltage of the follower first input terminal a1 and the follower second input terminal a2 to meet the voltage requirement of the common-source circuit 3024. The common-source circuit 3024 includes a common-source circuit first input terminal B1, a common-source circuit second input terminal B2, a common-source circuit first output terminal B3, and a common-source circuit second output terminal B4. The second load circuit 3025 includes a load input terminal F1 and a load output terminal F2. The follower first input terminal a1 is electrically connected to the mirror circuit first input terminal 3021, the follower second input terminal a2 is electrically connected to the mirror circuit second input terminal 3022, the follower first output terminal A3 is electrically connected to the common-source circuit first input terminal B1, the follower second output terminal a4 is electrically connected to the common-source circuit second input terminal B2, the common-source circuit first output terminal B3 is electrically connected to the input terminal C1 of the fourth current mirror CM4, the common-source circuit second output terminal B4 is electrically connected to the input terminal D1 of the fifth current mirror CM5, the output terminal D2 of the fifth current mirror CM5 is electrically connected to the input terminal E1 of the sixth current mirror CM6, the output terminal C2 of the fourth current mirror CM4, the output terminal E2 of the sixth current mirror CM6 is electrically connected to the load input terminal F1, and the load output terminal F2 is electrically connected to the mirror circuit output terminal 3023.
As shown in fig. 10, the source follower 3026 further includes a first branch and a second branch; the first branch comprises a sixth current source I connected in series between the power supply and groundc6And a fifth MOS transistor M5, a source electrode of the fifth MOS transistor M5 and a sixth current source Ic6One end of the fifth MOS transistor M5 is electrically connected to the first output end A3 of the follower, and the gate of the fifth MOS transistor M5 is electrically connected to the first input end a1 of the follower through a resistor and a capacitor; the second branch comprises a seventh current source I connected in series between the power supply and groundc7And a sixth MOS transistor M6, a source electrode of the sixth MOS transistor M6 and a seventh current source Ic7And the gate of the sixth MOS transistor M6 is electrically connected to the second input terminal a2 of the follower through a resistor and a capacitor. Fifth MOS transistor M5 and sixth MOS transistor in this embodimentThe MOS transistor M6 is a PMOS (P-type metal-oxide-semiconductor) transistor.
As shown in fig. 11, the common-source circuit 3024 further includes a mirror resistor RdA third MOS transistor M3, a fourth MOS transistor M4, a third current source Ic3And a fourth current source Ic4. The third MOS transistor M3 and the fourth MOS transistor M4 are both NMOS (N-type metal-oxide-semiconductor) transistors. Mirror resistance RdIs equal to the third resistor RfResistors of the same type, third resistor RfAnd mirror resistance RdThe ratio of the resistances of (a) to (b) is p. Mirror resistance RdIs approximately equal to the third resistor RfIs measured. The difference between the currents at the first output terminal B3 of the common source circuit 3024 and the second output terminal B4 of the common source circuit is equal to the current flowing through the mirror resistor RdThe current in the capacitor. A third current source Ic3And a fourth current source Ic4The currents supplied are equal.
The grid electrode of the third MOS transistor M3 is electrically connected with the first input end B1 of the common source circuit, and the grid electrode of the fourth MOS transistor M4 is electrically connected with the second input end B2 of the common source circuit; the source electrode of the third MOS transistor M3 and a third current source Ic3One terminal of (1) and mirror resistor RdIs electrically connected with the source of the fourth MOS transistor M4, the fourth current source Ic4One terminal of (1) and mirror resistor RdThe other end of the first and second electrodes is electrically connected; the drain electrode of the third MOS transistor M3 is electrically connected with the first output end B3 of the common source circuit; the drain of the fourth MOS transistor M4 is electrically connected to the second output terminal B4 of the common source circuit. A third current source Ic3And the other end of the fourth current source Ic4The other ends of the two are all grounded.
As shown in fig. 12, the second load circuit 3025 includes a fifth current source Ic5And a seventh current mirror CM7, the input of which is CM7 connected to the load input F1 and to a fifth current source Ic5Is electrically connected to the output of the seventh current mirror CM7, is electrically connected to the load output F2, and is connected to the fifth current source Ic5Is grounded, the current ratio of the input branch of the seventh current mirror CM7 to the output branch of the seventh current mirror CM7 is 1: n is the same as the formula (I).
FIG. 13 is a circuit diagram of a specific implementation of the resistor current mirror circuit 302, in which a fourth current mirror CM4 is shown for convenience of illustrationTwo parts CM4, a and CM4, b, where CM4, a is the input branch of the fourth current mirror CM4 and CM4, b is the output branch of the fourth current mirror CM 4. The current ratio of the input branch of the fifth current mirror CM5 to the output branch of the fifth current mirror CM5 is 1: m, the current ratio of the input branch of the sixth current mirror CM6 to the output branch of the sixth current mirror CM6 is 1: k, the ratio of the current in the input branch of the fourth current mirror CM4 to the current in the output branch of the fourth current mirror CM4 is 1: (m × k); the current ratio of the input branch of the seventh current mirror CM7 to the output branch of the seventh current mirror CM7 is 1: n, m, k, n are all positive real numbers. Second output current IOUT2Expression is [ n x IC5+(2*m*n*k*IRf/p)]。
Example 3
A chip includes the transimpedance amplifier shown in fig. 2 and the RSSI circuit in embodiment 2.
Example 4
The present embodiment provides a base current mirror circuit of a bipolar transistor, as shown in fig. 14, a single-stage common emitter amplifier circuit 2 and a base current mirror circuit 1 of a bipolar transistor, and is different from embodiment 1 in that the bipolar transistor Q4 to be mirrored and the mirror bipolar transistor Q5 are both PNP type bipolar transistors, and the first current source Ic1And a second current source Ic2The other ends of the first and second MOS transistors M1 and M2 are both NMOS transistors.
Example 5
The present embodiment provides an RSSI circuit, which is different from embodiment 2 in that an implementation circuit of a source follower 3026 is shown in fig. 15, in which a fifth MOS transistor M5 and a sixth MOS transistor M6 are NMOS transistors.
Example 6
The present embodiment provides an RSSI circuit, and is different from embodiment 2 in that an implementation circuit of a second load circuit 3025 is shown in fig. 16, in which a fifth current source Ic5The other end of the switch is connected with a power supply.
Example 7
The present embodiment provides an RSSI circuit, as shown in fig. 17, which is different from embodiment 2 in that: a third MOS transistor M3 and a fourth MOS transistorThe MOS transistors M4 are PMOS transistors, and the third current source Ic3And the other end of the fourth current source Ic4The other ends of the two ends; the fifth MOS transistor M5 and the sixth MOS transistor M6 are NMOS transistors; a fifth current source Ic5The other end of the switch is connected with a power supply.
The invention is based on the current I across the transimpedance amplifier in FIG. 2b、IRf、IDCRAre copied according to the proportion, and then the copied currents are added to obtain the sum of the input current I and the sum of the input current IinThe RSSI circuit has high precision and can simultaneously meet the application of PIN type photodiodes and APD type photodiodes by taking the current in proportional relation in value as the received signal strength indication information.
While specific embodiments of the invention have been described above, it will be appreciated by those skilled in the art that this is by way of example only, and that the scope of the invention is defined by the appended claims. Various changes and modifications to these embodiments may be made by those skilled in the art without departing from the spirit and scope of the invention, and these changes and modifications are within the scope of the invention.

Claims (15)

1. A base current mirror circuit of a bipolar transistor is characterized by being used for mirroring a base current of the bipolar transistor to be mirrored and comprising a circuit input end, a circuit output end, the bipolar transistor to be mirrored, a clamping circuit, a first current mirror, a first current source, a second current source and a first load circuit, wherein the circuit input end of the base current mirror circuit is led out from a collector of the bipolar transistor to be mirrored;
the clamping circuit comprises a first input end, a second input end and an output end, the first input end of the clamping circuit is electrically connected with the circuit input end of the base current mirror circuit, the second input end of the clamping circuit is electrically connected with the collector of the mirror bipolar transistor, and the output end of the clamping circuit is electrically connected with the first current mirror;
the clamping circuit is used for clamping the voltages of the collector electrode of the bipolar transistor to be mirrored and the collector electrode of the mirror image bipolar transistor;
the input end of the first current mirror, the base electrode of the mirror bipolar transistor and one end of the first current source are electrically connected;
the output end of the first current mirror, one end of the second current source and the input end of the first load circuit are electrically connected;
the output end of the first load circuit is electrically connected with the circuit output end of the base current mirror circuit.
2. The bipolar transistor base current mirror circuit of claim 1 wherein said clamp circuit comprises a differential input single ended output amplifier, a non-inverting input of said amplifier being said first input of said clamp circuit, an inverting input of said amplifier being said second input of said clamp circuit, and an output of said amplifier being an output of said clamp circuit.
3. The base current mirror circuit of a bipolar transistor according to claim 1, wherein said first current mirror comprises a first MOS transistor and a second MOS transistor, and wherein an output terminal of said clamp circuit, a gate of said first MOS transistor and a gate of said second MOS transistor are electrically connected; the drain electrode of the first MOS tube is electrically connected with the base electrode of the mirror image bipolar transistor; the drain electrode of the second MOS tube is electrically connected with the input end of the first load circuit;
the ratio of the width-length ratio of the first MOS transistor to the width-length ratio of the second MOS transistor is equal to the ratio of the current of the first current source to the current of the second current source.
4. The base current mirror circuit of claim 1, wherein said first load circuit comprises a second current mirror, an input of said second current mirror is connected to an input of said first load circuit, an output of said second current mirror is connected to an output of said first load circuit, a ratio of a current of an input branch of said second current mirror to a current of an output branch of said second current mirror is 1: n, wherein n is a positive real number.
5. The base current mirror circuit of claim 1 wherein the collector of said bipolar transistor to be mirrored is connected in series with a first load and the collector of said mirrored bipolar transistor is connected in series with a second load.
6. The base current mirror circuit of a bipolar transistor according to claim 5, wherein said first load and said second load are both resistors.
7. The base current mirror circuit of claim 1, wherein the emitter of the bipolar transistor to be mirrored is connected in series with a first resistor having a resistance of R1, the emitter of the bipolar transistor to be mirrored is connected in series with a second resistor having a resistance of R2, and the emitter of the bipolar transistor to be mirrored has an area of aQ1The area of an emitter of the mirror image bipolar transistor is AQ2R2/R1 equal to AQ2/AQ1。
8. An RSSI circuit for a transimpedance amplifier comprising a first bipolar transistor, a second bipolar transistor and a third resistor, an input current of the transimpedance amplifier being split into a collector current of the first bipolar transistor, a current of the third resistor and a base current of the second bipolar transistor,
the RSSI circuit comprises a resistance current mirror circuit, a collector current mirror circuit and a base current mirror circuit of the bipolar transistor according to any one of claims 1 to 7;
the second bipolar transistor is the bipolar transistor to be mirrored;
the resistance current mirror circuit is used for mirroring the current of the third resistor;
the collector current mirror circuit is used for mirroring the current of the collector of the first bipolar transistor.
9. The RSSI circuit of claim 8, wherein the collector current mirror circuit comprises a third bipolar transistor having a gate electrically connected to the gate of the first bipolar transistor and a third current mirror for mirroring the collector current of the third bipolar transistor.
10. The RSSI circuit of claim 8, wherein the resistor current mirror circuit is configured to mirror the current of the resistor to be mirrored, the resistor current mirror circuit comprising a mirror circuit first input, a mirror circuit second input, a mirror circuit output, and a differential common source circuit with source degeneration;
the first input end of the mirror image circuit and the second input end of the mirror image circuit are respectively led out from two ends of the resistor to be mirrored;
the common source circuit comprises a mirror resistor, a first input end of the common source circuit, a second input end of the common source circuit, a first output end of the common source circuit and a second output end of the common source circuit; the first input end of the common source circuit is electrically connected with the first input end of the mirror image circuit, and the second input end of the common source circuit is electrically connected with the second input end of the mirror image circuit; the current difference between the first output end of the common source circuit and the second output end of the common source circuit is equal to the current flowing through the mirror resistor;
the resistance current mirror circuit further comprises a fourth current mirror, a fifth current mirror, a sixth current mirror and a second load circuit, wherein the second load circuit comprises a load input end and a load output end;
the input end of the fourth current mirror is electrically connected with the first output end of the common source circuit, and the output end of the fourth current mirror is electrically connected with the load input end;
the input end of the fifth current mirror is electrically connected with the second output end of the common source circuit, and the output end of the fifth current mirror is electrically connected with the input end of the sixth current mirror;
the output end of the sixth current mirror is electrically connected with the load input end;
the ratio of the current of the input branch of the fifth current mirror to the current of the output branch of the fifth current mirror is 1: m, the ratio of the current of the input branch of the sixth current mirror to the current of the output branch of the sixth current mirror is 1: k, the ratio of the current of the input branch of the fourth current mirror to the current of the output branch of the fourth current mirror is 1: (m × k);
the load output end is electrically connected with the output end of the mirror image circuit, and the ratio of the current of the load output end to the current of the load input end is 1: n; m, k and n are all positive real numbers.
11. The RSSI circuit of claim 10, wherein said common-source circuit further comprises a third MOS transistor, a fourth MOS transistor, a third current source, and a fourth current source; the current provided by the third current source is equal to the current provided by the fourth current source;
the grid electrode of the third MOS tube is electrically connected with the first input end of the mirror image circuit, and the grid electrode of the fourth MOS tube is electrically connected with the second input end of the mirror image circuit;
the source electrode of the third MOS tube, one end of the third current source and one end of the mirror resistor are electrically connected, and the source electrode of the fourth MOS tube, one end of the fourth current source and the other end of the mirror resistor are electrically connected;
the drain electrode of the third MOS tube is electrically connected with the first output end of the common source circuit; and the drain electrode of the fourth MOS tube is electrically connected with the second output end of the common source circuit.
12. The RSSI circuit of claim 10, wherein said second load circuit comprises a fifth current source and a seventh current mirror, an input of said seventh current mirror being electrically connected to said load input and to one terminal of said fifth current source, an output of said seventh current mirror being electrically connected to said load output, a current ratio of an input branch of said seventh current mirror to an output branch of said seventh current mirror being 1: n is the same as the formula (I).
13. The RSSI circuit of claim 10, wherein said resistance current mirror circuit further comprises a source follower connected in series between said resistance to be mirrored and said common source circuit;
the source follower comprises a first follower input end, a second follower input end, a first follower output end and a second follower output end;
the first input end of the follower is electrically connected with the first input end of the mirror image circuit, and the second input end of the follower is electrically connected with the second input end of the mirror image circuit;
the first output end of the follower is electrically connected with the first input end of the common source circuit, and the second output end of the follower is electrically connected with the second input end of the common source circuit;
the source follower is used for adjusting the voltage of the first input end of the follower and the second input end of the follower to adapt to the voltage of the common source circuit.
14. The RSSI circuit of claim 13, wherein said source follower comprises a first leg and a second leg;
the first branch circuit comprises a sixth current source and a fifth MOS tube which are connected between a power supply and the ground in series, the source electrode of the fifth MOS tube is electrically connected with the sixth current source, and the grid electrode of the fifth MOS tube is electrically connected with the first input end of the follower;
the second branch circuit comprises a seventh current source and a sixth MOS tube which are connected between a power supply and the ground in series, the source electrode of the sixth MOS tube is electrically connected with the seventh current source, and the grid electrode of the sixth MOS tube is electrically connected with the second input end of the follower;
the current provided by the sixth current source is equal to the current provided by the seventh current source.
15. A chip comprising a transimpedance amplifier, characterized in that it further comprises an RSSI circuit according to any of claims 8 to 14.
CN201710423128.2A 2017-06-07 2017-06-07 Base current mirror circuit, RSSI circuit and chip of bipolar transistor Active CN109002075B (en)

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CN109002076B (en) * 2017-06-07 2021-10-29 苏州瀚宸科技有限公司 Resistance current mirror circuit, RSSI circuit and chip
CN111327282B (en) * 2018-12-17 2024-02-20 深圳市中兴微电子技术有限公司 Control circuit, transimpedance amplifying circuit and control method
CN113114196B (en) * 2021-04-29 2023-10-13 全球能源互联网研究院有限公司 Photoelectric amplification integrated triode chip
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