CN111092601A - Limiting amplifier and TIA circuit - Google Patents
Limiting amplifier and TIA circuit Download PDFInfo
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- CN111092601A CN111092601A CN201811242122.6A CN201811242122A CN111092601A CN 111092601 A CN111092601 A CN 111092601A CN 201811242122 A CN201811242122 A CN 201811242122A CN 111092601 A CN111092601 A CN 111092601A
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F1/00—Details of amplifiers with only discharge tubes, only semiconductor devices or only unspecified devices as amplifying elements
- H03F1/08—Modifications of amplifiers to reduce detrimental influences of internal impedances of amplifying elements
- H03F1/18—Modifications of amplifiers to reduce detrimental influences of internal impedances of amplifying elements by use of distributed coupling, i.e. distributed amplifiers
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F1/00—Details of amplifiers with only discharge tubes, only semiconductor devices or only unspecified devices as amplifying elements
- H03F1/26—Modifications of amplifiers to reduce influence of noise generated by amplifying elements
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F1/00—Details of amplifiers with only discharge tubes, only semiconductor devices or only unspecified devices as amplifying elements
- H03F1/32—Modifications of amplifiers to reduce non-linear distortion
- H03F1/3211—Modifications of amplifiers to reduce non-linear distortion in differential amplifiers
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F1/00—Details of amplifiers with only discharge tubes, only semiconductor devices or only unspecified devices as amplifying elements
- H03F1/42—Modifications of amplifiers to extend the bandwidth
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
- H03F3/45—Differential amplifiers
- H03F3/45071—Differential amplifiers with semiconductor devices only
- H03F3/45479—Differential amplifiers with semiconductor devices only characterised by the way of common mode signal rejection
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04B—TRANSMISSION
- H04B10/00—Transmission systems employing electromagnetic waves other than radio-waves, e.g. infrared, visible or ultraviolet light, or employing corpuscular radiation, e.g. quantum communication
- H04B10/60—Receivers
- H04B10/66—Non-coherent receivers, e.g. using direct detection
Abstract
A limiting amplifier (10) is provided with a first input end (11), a second input end (12), a first output end (13) and a second output end (14), the limiting amplifier (10) comprises a first inductor L1, a second inductor (L2), a first load (R1), a second load (R2), a first triode (T1) and a second triode (T2), the collectors of the first triode (T1) and the second triode (T2) are grounded through a current source (15), and the first inductor L1 and the second inductor L2 are a pair of differential coupling inductors which are respectively connected with the loads (R1 and R2) in series. Thus, the limiting amplifier (10) with the structure has the function of converting a single-ended input signal into a double-ended differential output signal, and the addition of the differential coupling inductor can reduce the phase difference between the two output signals, so that the swing of the total output signal is closer to the output of a real differential amplifier.
Description
Technical Field
The application belongs to the technical field of photoelectric communication, and particularly relates to a limiting amplifier and a TIA circuit.
Background
In both optical sensors and fiber optic communication systems, TIA (Trans-Impedance Amplifier) belongs to the optical receiver section. TIAs are typically used in conjunction with photodiodes that receive optical signals and convert the optical signals to electrical signals. Most of the optical signals are directly converted into weak electrical signals, so the TIA is required to amplify the electrical signals converted by the photodiode. Typically, a photodiode converts an optical signal into a single-ended electrical signal, and the TIA only needs to amplify the single-ended electrical signal. However, in the optical fiber communication system, for very high speed signals, the TIA has to convert the single-ended electrical signal into the double-ended differential signal, which can increase the signal transmission bandwidth, reduce noise, and better perform the next signal processing.
A TIA circuit of a typical digital optical fiber communication system receiver generally includes modules such as a pre-transimpedance amplifier circuit and a limiting amplifier circuit. Incident light is converted into photocurrent through a photodiode, the photocurrent converts a single-ended current signal into a single-ended voltage signal through a pre-transimpedance amplifier, and a limiting amplifier is used for further amplifying a small voltage signal output by the pre-transimpedance amplifier to a large enough amplitude, so that a subsequent data judgment circuit can work better to reduce the bit error rate. In addition, the CML (Current-Mode Logic) limiting amplifier is also used as a converter for converting a single-ended voltage signal into a double-ended voltage differential signal, and the single-ended voltage signal is converted into a double-ended voltage differential signal on the CML limiting amplifier through a direct Current feedback loop. Schematic structure of a conventional CML limiting amplifier as shown in fig. 1(a), the CML limiting amplifier has two input terminals, one of which is driven by a single-ended radio frequency signal RF, and the other of which is fixed at a reference voltage DC. For low and medium frequency signals, the two outputs output a good pair of differential output signals Vp and Vn. But as the frequency increases, the phase and amplitude difference between the two differential output signals Vp and Vn becomes more and more pronounced for high frequency signals. As shown in fig. 1(b), this causes the swing Vtotal of the differential output (Vtotal is a vector difference between Vp and Vn) to become small, which results in the decrease of the opening degree of the output eye diagram and the increase of jitter, and this phenomenon occurs because of the signal paths of the two differential signals: one of the signals RF is from the base of the transistor T1 to the collector of the transistor T1, the other DC is from the base of the transistor T2 to the collector of the transistor T2, the transistor T1 operates in a common emitter circuit state, and the transistor T2 operates in a common base circuit state.
Therefore, when the conventional CML limiting amplifier is switched in a high-frequency signal, the phase and amplitude difference between the two output differential signals is obvious, the opening degree of an eye pattern is reduced, and the jitter is increased.
Disclosure of Invention
In view of this, the present application provides a TIA circuit with an improved limiting amplifier structure, which aims to solve the problems that when a high-frequency signal is accessed by a conventional CML limiting amplifier, the phase and amplitude difference between two output differential output signals is obvious, which results in a decrease in the opening degree of an eye pattern and an increase in jitter.
A first aspect of the embodiments of the present application provides a limiting amplifier, which has a first input terminal, a second input terminal, a first output terminal, and a second output terminal, and includes:
the first end of the first inductor is connected with a power supply;
a second inductor, a first end of the second inductor is connected to the power supply, and the second inductor and the first inductor are mutually differentially coupled;
a base electrode of the first triode is used as the first input end, a collector electrode of the first triode is connected with the second end of the first inductor through a first load, and the collector electrode of the first triode is also used as the first output end; and
and the base electrode of the second triode is used as the second input end, the collector electrode of the second triode is connected with the second end of the second inductor through a second load, the collector electrode of the second triode is also used as the second output end, and the emitter electrode of the second triode and the emitter electrode of the first triode are grounded through a current source.
A second aspect of an embodiment of the present application provides a TIA circuit, including:
a pre-transimpedance amplifier;
the limiting amplifier as described above, wherein the first input terminal of the limiting amplifier is connected to the output terminal of the pre-transimpedance amplifier;
two input ends of the output buffer are connected with two output ends of the limiting amplifier, and two output ends of the output buffer are used as output ends of the TIA circuit; and
and two input ends of the feedback loop are connected with two output ends of the output buffer, and the output end of the feedback loop is connected with the second input end of the limiting amplifier.
In order to improve the unbalanced state between the two output signals, the limiting amplifier is added with a pair of differential coupling inductors which are respectively connected with the load in series, and the addition of the differential coupling inductors can reduce the phase difference between the two output signals, so that the swing of the total output signal is closer to the output of the real differential amplifier. So that the degree of opening of the output eye pattern increases and jitter decreases. The addition of the differential inductor can also increase the-3 dB bandwidth of the limiting amplifier by appropriate selection of the time constant. In addition, after the inductor is added, because the two output signals are closer to the real differential signal, the common mode rejection ratio of the limiting amplifier is improved, and alternating current noise superimposed on the power supply can be also suppressed.
Drawings
In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings needed to be used in the embodiments or the prior art descriptions will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the present application, and it is obvious for those skilled in the art to obtain other drawings based on these drawings without inventive exercise.
Fig. 1(a) is a schematic circuit diagram of a conventional limiting amplifier;
fig. 1(b) is a vector diagram of two differential output signals of a conventional limiting amplifier;
fig. 2(a) is a schematic circuit diagram of a limiting amplifier according to an embodiment of the present application;
fig. 2(b) is a vector diagram of two differential output signals of the limiting amplifier shown in fig. 2 (a);
fig. 3 is a schematic structural diagram of a TIA circuit according to an embodiment of the present application.
Detailed Description
In order to make the objects, technical solutions and advantages of the present application more apparent, the present application is described in further detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the present application and are not intended to limit the present application.
Referring to fig. 2(a), the limiting amplifier 10 provided in the present embodiment has a first input terminal 11, a second input terminal 12, a first output terminal 13 and a second output terminal 14, and the limiting amplifier 10 includes a first inductor L1, a second inductor L2, a first load R1, a second load R2, a first transistor T1 and a second transistor T2.
The first terminal of the first inductor L1 is connected with a power supply Vcc; the first terminal of the second inductor L2 is connected to the power supply Vcc, and the second inductor L2 and the first inductor L1 are differentially coupled to each other; a base electrode of the first triode T1 is used as the first input end 11 of the limiting amplifier 10, a collector electrode of the first triode T1 is connected with the second end of the first inductor L1 through a first load R1, and a collector electrode of the first triode T1 is also used as the first output end 13 of the limiting amplifier 10; the base of the second transistor T2 serves as the second input terminal 12 of the limiting amplifier 10, the collector of the second transistor T2 is connected to the second terminal of the second inductor L2 through the second load R2, the collector of the second transistor T2 also serves as the second output terminal 14 of the limiting amplifier 10, and the emitter of the second transistor T2 and the emitter of the first transistor T1 are connected to the ground through the current source 15.
In some embodiments, the second terminal of the first inductor L1 is a dotted terminal; the first end of the second inductor L2 is a dotted terminal; in other embodiments, the first terminal of the first inductor L1 may also be a dotted terminal; the second terminal of the second inductor L2 is a dotted terminal. Optionally, the first load R1 and the second load R2 are both circuits formed by at least one of a resistor, a capacitor, and an inductor. In this embodiment, the first load R1 and the second load R2 are one or more resistors connected in series or parallel. In other embodiments, the first load R1 and the second load R2 may be series-parallel inductors/capacitors, or the like. The first input 11 of the limiting amplifier 10 is a non-inverting input, the second input 12 is an inverting input, the first output 13 is a non-inverting (positive) output, and the second output 14 is an inverting (negative) input.
Optionally, the first transistor T1 and the second transistor T2 are both NPN transistors. In other embodiments, the first transistor T1 and the second transistor T2 may be PNP transistors or N-channel MOS transistors.
The limiting amplifier 10 described above is typically a CML limiting amplifier incorporating a pair of differentially coupled inductors L1, L2 in series with a first load R1 and a second load R2, respectively. The addition of the differential coupling inductance can reduce the phase difference between the two differential output signals Vp and Vn, so that the swing Vtotal of the total output signal (Vtotal being the vector difference between Vp and Vn) is closer to the output of the true differential amplifier (as shown in fig. 2 (b)). So that the degree of opening of the output eye pattern increases and jitter decreases. Furthermore, by properly choosing the time constant τ L/R, the addition of the differential coupling inductor can also increase the 3-dB bandwidth of the limiting amplifier 10. In addition, after the differential coupling inductance is added, since the two differential output signals Vp and Vn are closer to the true differential signals, the Common Mode Rejection Ratio (CMRR) of the limiting amplifier 10 is improved, and the ac current noise superimposed on the power supply Vcc is also suppressed.
Referring to fig. 2(a) and fig. 3, an exemplary TIA circuit includes a pre-transimpedance amplifier 20, the limiting amplifier 10, an output buffer 30, and a feedback loop 40.
The input end of the pre-transimpedance amplifier 20 serves as the input end of the TIA circuit, and the first input end 11 of the limiting amplifier 10 is connected with the output end of the pre-transimpedance amplifier 20; two input ends of the output buffer 30 are connected with two output ends of the limiting amplifier 10, and two output ends of the output buffer 30 are used as output ends of the TIA circuit; two inputs of the feedback loop 40 are connected to two outputs of the output buffer 30, and an output of the feedback loop 40 is connected to the second input terminal 12 of the limiting amplifier 10.
In an optical sensor and an optical fiber communication system, an input end of a pre-transimpedance amplifier 20 is generally connected with an anode of a photodiode D1, a cathode of a photodiode D1 is connected with a power supply voltage VPD, incident light is converted into photocurrent through the photodiode D1, and the photocurrent converts a single-ended current signal into a single-ended voltage signal through the pre-transimpedance amplifier 20. Thereafter, the limiting amplifier 10 converts the single-terminal voltage signal into a double-terminal voltage differential signal, and inputs the double-terminal voltage differential signal to the output buffer 30. Optionally, the limiting amplifier 10 and the output buffer 30 are both a CML limiting amplifier and an output buffer.
In some embodiments, the TIA circuit further includes a first differential load resistor R3 and a second differential load resistor R4, the first differential load resistor R3 and the second differential load resistor R4 being respectively connected between the two output terminals of the output buffer 30 and the power supply Vcc 1. The first and second differential load resistors R3 and R4 also act as load resistors for the entire circuit output.
In some embodiments, the feedback loop 40 includes an operational amplifier 41, two input terminals of the operational amplifier 41 are respectively connected to two output terminals of the output buffer 30, and an output terminal of the operational amplifier 41 is connected to the second input terminal 12 of the limiting amplifier 10. Optionally, two input terminals of the operational amplifier 41 are respectively connected to two output terminals of the output buffer 30 through a current limiting resistor R5 and a current limiting resistor R6, and two input terminals of the operational amplifier 41 are directly connected to a filter capacitor C1.
Optionally, an inverting input terminal of the pre-transimpedance amplifier 20 is connected to an anode of the photodiode D1, a non-inverting input terminal of the operational amplifier 41 is connected to a non-inverting output terminal of the output buffer 30, and an inverting input terminal of the operational amplifier 41 is connected to an inverting output terminal of the output buffer 30.
Various embodiments are described herein for various devices, systems, and/or methods. Numerous specific details are set forth in order to provide a thorough understanding of the overall structure, function, manufacture, and use of the embodiments as described in the specification and illustrated in the accompanying drawings. However, it will be understood by those skilled in the art that the embodiments may be practiced without such specific details. In other instances, well-known operations, components and elements have been described in detail so as not to obscure the embodiments in the description. It will be appreciated by those of ordinary skill in the art that the embodiments herein and shown are non-limiting examples, and thus, it can be appreciated that the specific structural and functional details disclosed herein may be representative and do not necessarily limit the scope of the embodiments.
Reference throughout the specification to "various embodiments," "in an embodiment," "one embodiment," or "an embodiment," etc., means that a particular feature, structure, or characteristic described in connection with the embodiment is included in at least one embodiment. Thus, appearances of the phrases "in various embodiments," "in some embodiments," "in one embodiment," or "in an embodiment," or the like, in places throughout this specification are not necessarily all referring to the same embodiment. Furthermore, the particular features, structures, or characteristics may be combined in any suitable manner in one or more embodiments. Thus, a particular feature, structure, or characteristic illustrated or described in connection with one embodiment may be combined, in whole or in part, with features, structures, or characteristics of one or more other embodiments without presuming that such combination is not an illogical or functional limitation. Any directional references (e.g., plus, minus, upper, lower, upward, downward, left, right, leftward, rightward, top, bottom, above …, below …, vertical, horizontal, clockwise, and counterclockwise) are used for identification purposes to aid the reader's understanding of the present disclosure, and do not create limitations, particularly as to the position, orientation, or use of the embodiments.
Although certain embodiments have been described above with a certain degree of particularity, those skilled in the art could make numerous alterations to the disclosed embodiments without departing from the scope of this disclosure. Joinder references (e.g., attached, coupled, connected, and the like) are to be construed broadly and may include intermediate members between a connection of elements and relative movement between elements. Thus, connection references do not necessarily imply that two elements are directly connected/coupled and in a fixed relationship to each other. The use of "for example" throughout this specification should be interpreted broadly and used to provide non-limiting examples of embodiments of the disclosure, and the disclosure is not limited to such examples. It is intended that all matter contained in the above description or shown in the accompanying drawings shall be interpreted as illustrative only and not limiting. Changes in detail or structure may be made without departing from the disclosure.
Claims (9)
1. A limiting amplifier having a first input, a second input, a first output, and a second output, comprising:
the first end of the first inductor is connected with a power supply;
a second inductor, a first end of the second inductor is connected to the power supply, and the second inductor and the first inductor are mutually differentially coupled;
a base electrode of the first triode is used as the first input end, a collector electrode of the first triode is connected with the second end of the first inductor through a first load, and the collector electrode of the first triode is also used as the first output end; and
and the base electrode of the second triode is used as the second input end, the collector electrode of the second triode is connected with the second end of the second inductor through a second load, the collector electrode of the second triode is also used as the second output end, and the emitter electrode of the second triode and the emitter electrode of the first triode are grounded through a current source.
2. The limiting amplifier according to claim 1, wherein the second terminal of the first inductor is a dotted terminal and the first terminal of the second inductor is a dotted terminal.
3. The limiting amplifier according to claim 1, wherein a first terminal of the first inductor is a dotted terminal and a second terminal of the second inductor is a dotted terminal.
4. The limiting amplifier according to claim 1, wherein the first load and the second load are each a circuit composed of at least one of a resistor, a capacitor, and an inductor.
5. The limiting amplifier according to claim 1, wherein said first input terminal is an inverting input terminal and said second input terminal is a non-inverting input terminal.
6. The limiting amplifier according to claim 1, wherein the first transistor and the second transistor are both NPN type.
7. A TIA circuit, comprising:
a pre-transimpedance amplifier;
the limiting amplifier according to any one of claims 1 to 6, wherein a first input terminal of the limiting amplifier is connected to an output terminal of the pre-transimpedance amplifier;
two input ends of the output buffer are connected with two output ends of the limiting amplifier, and two output ends of the output buffer are used as output ends of the TIA circuit; and
and two input ends of the feedback loop are connected with two output ends of the output buffer, and the output end of the feedback loop is connected with the second input end of the limiting amplifier.
8. A TIA circuit as recited in claim 7, further comprising first and second differential load resistors respectively connected between two output terminals of the output buffer and a power supply.
9. A TIA circuit as claimed in claim 8, wherein the feedback loop comprises an operational amplifier having two inputs connected to two outputs of the output buffer, respectively, and an output of the operational amplifier being connected to the second input of the limiting amplifier.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201811242122.6A CN111092601A (en) | 2018-10-24 | 2018-10-24 | Limiting amplifier and TIA circuit |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201811242122.6A CN111092601A (en) | 2018-10-24 | 2018-10-24 | Limiting amplifier and TIA circuit |
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| CN111092601A true CN111092601A (en) | 2020-05-01 |
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| CN201811242122.6A Pending CN111092601A (en) | 2018-10-24 | 2018-10-24 | Limiting amplifier and TIA circuit |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111600660A (en) * | 2020-05-13 | 2020-08-28 | 成都优博创通信技术股份有限公司 | Optical communication device, OLT equipment and communication link |
| CN113014247A (en) * | 2021-02-23 | 2021-06-22 | 电子科技大学 | Input buffer |
-
2018
- 2018-10-24 CN CN201811242122.6A patent/CN111092601A/en active Pending
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111600660A (en) * | 2020-05-13 | 2020-08-28 | 成都优博创通信技术股份有限公司 | Optical communication device, OLT equipment and communication link |
| CN111600660B (en) * | 2020-05-13 | 2021-08-31 | 成都优博创通信技术股份有限公司 | Optical communication device, OLT equipment and communication link |
| CN113014247A (en) * | 2021-02-23 | 2021-06-22 | 电子科技大学 | Input buffer |
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