CN113395064B

CN113395064B - Isolation circuit system and method thereof

Info

Publication number: CN113395064B
Application number: CN202110738681.1A
Authority: CN
Inventors: 董志伟; 张小龙
Original assignee: Rongpai Semiconductor Shanghai Co ltd
Current assignee: Rongpai Semiconductor Shanghai Co ltd
Priority date: 2021-06-30
Filing date: 2021-06-30
Publication date: 2023-07-21
Anticipated expiration: 2041-06-30
Also published as: CN113395064A

Abstract

A digital isolator device includes a first input buffer configured to receive a first differential signal from a transmitter and provide a second differential signal, the first differential input signal characterized by a first magnitude and the second differential signal characterized by a second magnitude, the first magnitude being greater than the second magnitude. The apparatus also includes a second input buffer configured to receive a third differential signal from the transmitter and provide a fourth differential signal, the second input buffer coupled to a second ground terminal. The apparatus also includes a common mode circuit coupled to the second differential signal and the fourth differential signal, the common mode circuit configured to reduce a common mode transient voltage associated with a voltage difference between the first ground terminal and the second ground terminal.

Description

Isolation circuit system and method thereof

Cross Reference to Related Applications

The present invention is a continuation-in-part application from U.S. patent application Ser. No. 17/025,565 entitled "isolation Circuit" filed on even 18, 9, 2020, which is a continuation-in-part application from U.S. patent application Ser. No. 15/990,571 claiming priority from Chinese patent application Ser. No. 201710386724.8 filed on 26, 5, 2017 and Chinese patent application Ser. No. 201710558211.0 filed on 10, 7, 2017, which are commonly owned and incorporated herein by reference in their entirety.

Technical Field

The present invention relates generally to the field of electronic circuit technology, and more particularly to an isolation circuit and method therefor.

Background

An optocoupler is a device that transmits signals via an optical medium. Typically, the light emitter and receiver (photo-sensing semiconductor) are packaged in the same chip. When the input terminal of the optocoupler receives the current signal, light is emitted from the optical transmitter. After light is received by the receiver, a photocurrent is generated and output from the output terminal of the optocoupler. Thus, an "electro-optical-electrical" conversion is achieved. In an optocoupler, a signal is coupled from an input terminal to an output terminal through an optical medium. Optocouplers are technology that has been used for over 50 years. The optocoupler achieves signal isolation by a single device for the first time, and is widely used in power control circuits.

However, optocouplers have some drawbacks. Because the electrical properties of the light emitting diode vary with temperature and the electrical properties of the optocoupler vary and are unstable with temperature. In addition, optocouplers have a problem of performance degradation due to aging of the light emitting diode and the isolation plastic. In addition, the optocoupler also has a low common mode rejection ratio due to parasitic capacitance between the light emitting diode and the receiving circuit. When there is a large common mode voltage variation (e.g., 30 kV/us) on both sides, the light emitting diode erroneously emits light due to parasitic capacitance current. Finally, optocouplers also have some drawbacks, such as low speed, high power cost, and not easy integration.

Existing isolation circuits are inadequate for various reasons explained below. New and improved isolation devices and methods are needed.

Disclosure of Invention

The invention relates to a circuit and a method. In a particular embodiment, the present invention provides a digital isolation device that includes a pair of buffers storing an incoming signal at a first voltage level. Wherein the common mode circuit is configured to reduce a common mode transient voltage associated with the incoming signal. The latch circuit is coupled to the common mode circuit and stores an intermediate signal and an incoming signal associated with the common mode circuit. Still other embodiments exist.

Particular embodiments provide a digital isolator device that includes a first input buffer configured to receive a first differential signal from a transmitter and to provide a second differential signal, the first differential input signal characterized by a first magnitude and the second differential signal characterized by a second magnitude, the first magnitude being greater than the second magnitude, the transmitter coupled to a first ground terminal, the first input buffer coupled to a second ground terminal. The apparatus also includes a second input buffer configured to receive a third differential signal from the transmitter and provide a fourth differential signal, the second input buffer coupled to the second ground terminal. The apparatus also includes a common mode circuit coupled to the second differential signal and the fourth differential signal, the common mode circuit coupled to the bias voltage and may include a resistor pair, the common mode circuit configured to reduce a common mode transient voltage associated with a voltage difference between the first ground terminal and the second ground terminal. The apparatus also includes a latch circuit configured to store the second differential signal and the fourth differential signal for a time interval.

One common aspect of certain embodiments includes a digital isolator device in which the transmitter is configured on a first die and the common mode circuit is configured on a second die. The digital isolator device may include an amplifier coupled to a latch circuit. The common mode circuit may include a crossover circuit. The crossover circuit may include a first switch coupled to the second differential signal and a second switch coupled to the fourth differential signal. The first switch may include a first drain, a first source, and a first gate, the first source coupled to the bias voltage, the first gate coupled to the second differential signal, the first drain coupled to the fourth differential signal; and the second switch may include a second drain, a second source, and a second gate, the second source coupled to the bias voltage, the second gate coupled to the fourth differential signal, the second drain coupled to the third differential signal. The crossover circuit is coupled to a supply voltage. The crossover circuit is coupled to the second ground terminal. The common mode circuit may include a first crossover circuit coupled to the supply voltage and a second crossover circuit coupled to the second ground terminal. The first crossover circuit may include a first pair of switches in a parallel configuration and the second crossover circuit may include a second pair of switches in a parallel configuration. The common mode circuit may include PMOS transistors configured in a crossover circuit. The common mode circuit may include BJT transistors configured in a crossover circuit. The first input buffer may include a first capacitor directly coupled to the first differential signal and a second capacitor directly coupled to the second ground terminal; and the second input buffer may include a third capacitor directly coupled to the third differential signal and a fourth capacitor directly coupled to the second ground terminal. The digital isolator device may include an inverter configured to generate a third differential signal.

Another common aspect of certain embodiments includes a digital isolator device. The digital isolator device further includes a latch module configured to store the first and second isolation signals for a time interval and output a latch signal, the latch module may include a first latch input terminal configured to receive the first latch input signal and a second latch input terminal configured to receive the second latch input signal. The apparatus also includes a common mode module configured to receive a common mode current generated due to a common mode transient between the first die and the second die, the common mode module may include: a first input terminal coupled to the first latch input terminal and configured to receive a first common mode input signal; a second input terminal coupled to the second latch input terminal and configured to receive a second common mode input signal; a first common mode leg coupled to the first input terminal and characterized by a first impedance value; and a second common mode leg coupled to the second input terminal and characterized by a second impedance value. The latch module and the common mode module are connected in parallel. The common mode current flowing through the common mode block is related to the common mode voltage and the differential mode voltage of the latch block.

In various embodiments, the common mode current is associated with a first impedance value of the first common mode leg, the first impedance value being associated with the first latch input signal. The common mode current is associated with a second impedance value of the second common mode leg, the second impedance value being associated with a second latch input signal of the latch module. The common mode module is coupled to a bias voltage, and the bias voltage is associated with a common mode voltage of the latch module. The first common mode branch is turned on when the input voltage of the latch module is lower than the bias voltage, and the second common mode branch is turned on when the input voltage of the latch module is higher than the bias voltage.

Yet another common aspect includes a method for providing isolation between two dies. The method includes receiving an incoming signal. The method further includes generating a differential signal based on the received incoming signal. The method further includes providing isolation between the first die and the second die, and generating an isolation signal based on the differential input signal, wherein an amplitude of the isolation signal is less than an amplitude of the input signal. The method further includes processing the isolated signal by the common mode module to reduce common mode noise. The method further comprises the steps of: the isolation signal processed by the common mode block is latched at a certain level and a latch signal is output. The method further includes amplifying the latch signal and outputting the amplified signal. The effective differential isolation signal is amplified by the common mode block during a common mode transient.

It should be appreciated that embodiments of the present invention provide a number of advantages over conventional techniques. By adding a common mode circuit to the isolation circuit, the common mode transient voltage associated with the voltage difference between the separate ground terminals can be reduced. In addition, the common mode circuit may amplify the effective differential signal. Thus, the Common Mode Transient Immunity (CMTI) and effective signal transmission of the isolation circuit can be greatly improved. Embodiments of the invention may be implemented in conjunction with existing systems and processes. According to embodiments, the use of common mode circuitry may be readily incorporated into existing systems and methods. There are other benefits.

The present invention achieves these and other benefits in the context of known technology. However, the nature and advantages of the invention may be further understood by reference to the following portions of the specification and the drawings.

Drawings

The following figures are merely examples and should not unduly limit the scope of the claims herein. Those of ordinary skill in the art will recognize many other variations, modifications, and alternatives. It should also be understood that the examples and embodiments described herein are for illustrative purposes only and that various modifications or changes in light thereof will be suggested to persons skilled in the art and are to be included within the spirit and purview of this method and scope of the appended claims.

Fig. 1 schematically illustrates a circuit diagram of an isolation circuit according to an embodiment of the present disclosure;

fig. 2 schematically illustrates a circuit diagram of an isolation circuit according to another embodiment of the present disclosure;

fig. 3 schematically illustrates a circuit diagram of an isolation circuit according to another embodiment of the present disclosure;

FIG. 4 schematically illustrates a timing diagram of the isolation circuit shown in FIG. 3;

fig. 5 schematically illustrates a circuit diagram of an isolation circuit according to another embodiment of the present disclosure;

FIG. 6 schematically illustrates a timing diagram of the isolation circuit shown in FIG. 5;

fig. 7 schematically illustrates a circuit diagram of an isolation circuit according to another embodiment of the present disclosure;

fig. 8 schematically illustrates a circuit diagram of an isolation circuit according to another embodiment of the present disclosure;

fig. 9 schematically illustrates a circuit diagram of an isolation circuit according to another embodiment of the present disclosure;

fig. 10 schematically illustrates a circuit diagram of an isolation circuit according to another embodiment of the present disclosure;

FIG. 11 schematically illustrates a circuit diagram of an isolation circuit according to another embodiment of the present disclosure;

fig. 12 schematically illustrates a flow chart of a method for providing isolation between two dies according to an embodiment of the disclosure; and

Fig. 13 schematically illustrates a flow chart of a method for providing isolation between two dies according to another embodiment of the present disclosure.

Fig. 14 schematically illustrates a circuit diagram of an isolation circuit according to an embodiment of the disclosure;

FIG. 15 schematically shows a timing diagram of the isolation circuit of FIG. 14 when there is no CMT;

FIG. 16 schematically shows a timing diagram of the isolation circuit shown in FIG. 14 when CMT occurs;

fig. 17 schematically illustrates a circuit diagram of an isolation circuit according to another embodiment of the present disclosure;

FIG. 18 schematically illustrates a schematic diagram of a common mode module according to an embodiment of the disclosure;

fig. 19 schematically illustrates a schematic diagram of a common mode module according to another embodiment of the present disclosure;

fig. 20 schematically illustrates a circuit diagram of an isolation circuit according to another embodiment of the present disclosure;

FIG. 21 schematically shows a timing diagram of the isolation circuit shown in FIG. 20 when negative CMT occurs;

FIG. 22 schematically illustrates a schematic diagram of a common mode module according to another embodiment of the disclosure;

FIG. 23 schematically illustrates a schematic diagram of a common mode module according to another embodiment of the disclosure;

FIG. 24 schematically illustrates a schematic diagram of a common mode module according to another embodiment of the disclosure;

Fig. 25 schematically illustrates a schematic diagram of a common-mode module according to another embodiment of the disclosure;

fig. 26 schematically illustrates a schematic diagram of a common mode module according to another embodiment of the present disclosure.

Fig. 27 schematically illustrates a flowchart of a method for providing isolation between two dies, in accordance with an embodiment of the present disclosure; and

fig. 28 schematically illustrates a flow chart of a method for providing isolation between two dies according to another embodiment of the present disclosure.

Detailed Description

As described above, digital isolators use semiconductor process technology to fabricate transformers or capacitors to transfer data. Digital isolators provide a multi-channel isolation solution with a much smaller footprint, which increases system reliability due to lower failure rates, operates over a wider temperature range (-40 ℃ to 125 ℃) and does not age or degrade over time. Furthermore, digital isolators can transmit a wider range of signals from DC to 300MHz, whereas conventional optocouplers can only transmit signals with frequencies less than 100 MHz.

Digital isolation circuitry generally includes, but is not limited to, isolation modules, transmitter circuitry, and receiver circuitry. Interference may occur when data is transferred between two circuits (e.g., a transmitter circuit and a receiver circuit) having a galvanically isolated (e.g., having the effect of blocking direct current) ground terminal. The isolation module is configured to provide isolation between two isolation circuits (e.g., a transmitter circuit and a receiver circuit). Typically, the transmitter circuit and the receiver circuit operate at different voltages and are connected to separate ground terminals, which will cause a large common mode current when there is a high slew rate (high frequency) transient between the transmitter circuit and the receiver circuit, a phenomenon known as Common Mode Transient (CMT). The ability of an isolation circuit to withstand such high slew rate voltage transients without upsets at the isolation circuit output is defined as Common Mode Transient Immunity (CMTI).

The common mode current caused by CMT may cause several problems. For example, when an isolation circuit is disposed between two separate dies (e.g., a first die and a second die), wherein a latch circuit disposed on the second die includes two latch input terminals coupled to the isolation circuit, a common mode current generated by the CMT will cause a common mode voltage to be applied to the two latch input terminals of the latch circuit. Common-mode voltage V _com This can be expressed by the following equation:

V _com ＝i _cmti ×R _in

wherein i is _cmti Is the common mode current generated by CMT, and R _in Is the common mode input impedance of the latch circuit. When the common mode voltage applied to the two latch input terminals is too high, the latch circuit may saturate, thus causing the latch to fail.

On the other hand, although the common-mode input impedance values of the two latch input terminals should be theoretically the same, there may be an impedance mismatch between the two common-mode input impedance values due to the actual manufacturing processΔR _in . Thus impedance mismatch ΔR _in The presence of (2) can convert the common mode voltage to a differential mode voltage that will be superimposed on the differential input signal of the latch circuit, resulting in a signal transmission error. From the difference DeltaR in impedance _in The resulting differential mode voltage can be represented by the following equation:

V _diff ＝i _cmti ×(R _in +ΔR _in )-i _cmti ×R _in ＝i _cmti ×ΔR _in

the following description is presented to enable one of ordinary skill in the art to make and use the invention and is provided in the context of a particular application. Various modifications and various uses in different applications will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to a wide range of embodiments. Thus, the present disclosure is not intended to be limited to the embodiments shown but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

In the following detailed description, numerous specific details are set forth in order to provide a more thorough understanding of the invention. It will be apparent, however, to one skilled in the art that the invention may be practiced without limitation to these specific details. In other instances, well-known structures and devices are shown in block diagram form, rather than in detail, in order to avoid obscuring the present invention.

The reader's attention is directed to all papers and documents which are filed concurrently with this specification and which are open to public inspection with this specification, and the contents of all such papers and documents are incorporated herein by reference. All the features disclosed in this specification (including any accompanying claims, abstract and drawings) may be replaced by alternative features serving the same, equivalent or similar purpose, unless expressly stated otherwise. Thus, unless expressly stated otherwise, each feature disclosed is one example only of a generic series of equivalent or similar features.

Furthermore, any element of a claim that does not explicitly state a "means" for performing a specified function or a "step" for performing a specified function should not be construed as a "means" or "step" clause as specified in 35U.S. C.112 section 6. In particular, the use of "step" or "action" in the claims herein is not intended to invoke 35U.S. C. section 112, paragraph 6.

Note that the designations left, right, front, back, top, bottom, forward, reverse, clockwise, and counterclockwise, if used, are used for convenience only and are not meant to imply any particular fixed orientation. Rather, they are used to reflect the relative position and/or orientation between various portions of the object.

Referring to fig. 1, fig. 1 schematically illustrates a diagram of an isolation circuit according to an embodiment of the present disclosure. As shown in fig. 1, the isolation circuit includes: an isolation module comprising a main isolation leg 11, a latch 12, an amplifier 13 and a buffer 14. Specifically, the main isolation branch 11 includes a main isolation capacitor 111 and a first voltage dividing capacitor 112 connected in series.

In some embodiments, the isolation module is configured to generate an isolation signal based on an input signal from the first die and provide isolation between the first die and the second die.

In some embodiments, the main isolation capacitor 111 in the main isolation leg 11 includes a first plate that receives an input signal and a second plate that is coupled to a first input terminal of the latch 12. The first voltage dividing capacitor 112 includes a first plate that receives the ground signal of the second die GND2 and a second plate coupled to the second plate of the main isolation capacitor 111 and the first input terminal of the latch 12, wherein the voltage (isolation signal) on the first voltage dividing capacitor is output to the first input terminal of the latch 12. Thus, the amplitude of the isolated signal is less than the amplitude of the input signal. Furthermore, the output terminal of the latch 12 is coupled to the input terminal of the amplifier 13. The main isolation capacitor 111 serves to isolate the voltage between the first die and the second die, with a wide range of isolation voltages. In some embodiments, the isolation voltage may be as high as 20,000v.

In some embodiments, the main isolation capacitor 111 may be disposed in the first die or on the second die. In some embodiments, a portion of the main isolation capacitor 111 may be disposed on a first die and another portion of the main isolation capacitor 111 may be disposed on a second die. The flexible location distribution of the main isolation capacitor 111 facilitates the design of the isolation circuit and isolation voltage.

In some embodiments, both the main isolation capacitor 111 and the first voltage dividing capacitor 112 may have very low capacitance values at the fly (fF) level, and the isolation circuit typically has leakage current. In the case where the leakage current is at the picoampere (pA) level, the capacitor can maintain the voltage at a certain level for milliseconds. Therefore, when the input signal remains stable, the isolation signal output from the main isolation branch 11 cannot be maintained, thereby adversely affecting the isolation.

Therefore, it is necessary to stabilize the isolation signal output from the main isolation capacitor 111 so that the output signal from the amplifier 13 remains stable. Therefore, the latch 12 is required to latch the isolation signal at a certain level and output the latch signal.

In some embodiments, latch 12 may have a small flip voltage to identify digital signals having small amplitude differences. So that even small signal differences can be identified. Thus, the main isolation capacitor 111 having a small capacitance value can be manufactured with a thick dielectric, and isolation between two dies having a high voltage difference can be achieved. In some embodiments, latch 12 is a voltage latch.

The amplifier 13 is configured to amplify the latch signal. In some embodiments, the amplifier 13 amplifies the latch signal to the original number of input signals.

In some embodiments, the input signal may be filtered before being sent to the isolation module. As shown in fig. 1, the buffer 14 includes: an input terminal to receive an input signal from a circuit such as an application circuit on a first die; and an output terminal coupled to the first plate of the main isolation capacitor 111. The buffer 14 may be provided in the first die. It should be noted that the buffer 14 is not a mandatory component in the isolation circuit.

Referring to fig. 2, fig. 2 schematically illustrates a diagram of an isolation circuit according to another embodiment of the present disclosure. The isolation circuit includes: an isolation module comprising a main isolation leg 21, a latch 22, an amplifier 23 and a buffer 24. The main isolation branch 21 comprises a first voltage dividing capacitor 213.

The main difference from the isolation circuit shown in fig. 1 is that the first main isolation capacitor 211 and the second main isolation capacitor 212 are connected in series to constitute the main isolation capacitor in fig. 2. The other components are similar to the isolation circuit shown in fig. 1 and will not be described in detail below.

In some embodiments, the first main isolation capacitor 211 and the second main isolation capacitor 212 are disposed in different dies. For example, the first main isolation capacitor 211 may be disposed on a first die and the second main isolation capacitor 212 may be disposed on a second die. By disposing the first isolation capacitor 211 on the first die and the second isolation capacitor 212 on the second die, the isolation circuit may have a higher isolation voltage and the isolation circuit may be designed with more flexibility.

In some embodiments, the first main isolation capacitor 211 and the second main isolation capacitor 212 may have the same capacitance value.

In general, there is common mode noise between the first die and the second die, and common mode noise is generally indistinguishable from the desired signal. When the common mode noise increases significantly, for example, when it reaches a certain proportion of the desired signal or reaches the same level as the desired signal (for example, 100V/ns), the noise signal may have a significant effect on the desired signal and may cause problems such as signal distortion or loss. According to embodiments of the present disclosure, differential input circuitry may be introduced to reduce common mode noise.

Referring to fig. 3, fig. 3 schematically illustrates a diagram of an isolation circuit according to another embodiment of the present disclosure. The isolation circuit includes: an isolation module comprising a main isolation leg 31 and a common mode leg 35, a latch 32, an amplifier 33 and a buffer 34. The amplifier 33 and the buffer 34 are similar to the above circuits, and will not be described in detail hereinafter. The main isolation branch 31 includes a main isolation capacitor 311 and a first voltage dividing capacitor 312 connected in series. Common mode branch 35 is coupled to latch 32 to output a common mode signal to a second input terminal of latch 32 and to reduce common mode noise on the first die and the second die.

In some embodiments, the common mode leg 35 includes an auxiliary isolation capacitor 351 and a second voltage divider capacitor 352 in series. Specifically, a first plate of auxiliary isolation capacitor 351 is coupled to ground signal GND1 of the first die, a first plate of first voltage dividing capacitor 312 and a first plate of second voltage dividing capacitor 352 are coupled to ground signal GND2 of the second die, and a second plate of second voltage dividing capacitor 352 is coupled to a second input terminal of latch 32.

As shown in fig. 3, a first plate of auxiliary isolation capacitor 351 is coupled to ground signal GND1 of the first die so that latch 32 may receive a common mode signal to reduce common mode noise and increase the common mode rejection ratio in the isolation circuit.

Fig. 4 schematically shows a timing diagram of the isolation circuit shown in fig. 3. As shown in fig. 3 and 4, waveforms A, B, C, D and E in fig. 4 represent signals at nodes A, B, C, D and E, respectively, in fig. 3.

If the input signal level is VDD and the capacitance values of the main isolation capacitor 311 and the first voltage dividing capacitor 312 are represented by C1 and C2, respectively, the level of the isolation signal at the node C is C1/(c1+c2) ×vdd. Further, the latch signal level at the node D may also be C1/(c1+c2) VDD due to the presence of the latch 32. However, in some embodiments, the level at node D may have some amplification relative to the level at node C, e.g., the level at node D may be 2 to 3 times higher than the level at node C. Finally, after the latch signal is amplified by amplifier 33, the level at node E may have the same magnitude as the level at node A, or the latch signal may be amplified to a level required for further processing.

Referring to fig. 5, fig. 5 schematically illustrates a diagram of an isolation circuit according to another embodiment of the present disclosure. The isolation circuit includes: an isolation module comprising a main isolation leg 51 and a common mode leg 55, a latch 52, an amplifier 53, a buffer 54 and an inverter 56. The isolation module comprises a main isolation branch 51, the main isolation branch 51 comprising a main isolation capacitor 511 and a first voltage dividing capacitor 512 in series.

The main isolation leg 51, latch 52, amplifier 53 and buffer 54 are similar to the circuits above and will not be described in detail below. The common mode leg 55 comprises an auxiliary isolation capacitor 551 and a second voltage dividing capacitor 552 in series, and the inverter 56 ensures that the signal in the first INPUT terminal INPUT1 and the signal in the second INPUT terminal INPUT2 are opposite in phase. In some embodiments, inverter 56 is disposed in the first die.

In some embodiments, inverter 56 outputs an inverted input signal to common mode leg 55. A first plate of the auxiliary isolation capacitor 551 is coupled to the inverted input signal, a first plate of the first voltage dividing capacitor 512 and a first plate of the second voltage dividing capacitor 552 are coupled to the ground signal of the second die GND2, and a second plate of the second voltage dividing capacitor 552 is coupled to the second input terminal of the latch 52.

In some embodiments, inverter 56 includes an input terminal coupled to a first plate of main isolation capacitor 511 and an output terminal coupled to a first plate of auxiliary isolation capacitor 551. Further, an input terminal of the inverter 56 may be coupled with a first plate of the auxiliary isolation capacitor 551, and an output terminal of the inverter 56 may be coupled with a first plate of the main isolation capacitor 511.

In some embodiments, the main isolation capacitor 511 and the auxiliary isolation capacitor 551 may have various arrangements. In some embodiments, at least one of the main isolation capacitor 511 and the auxiliary isolation capacitor 551 is disposed in the first die or the second die. For example, the main isolation capacitor 511 and the auxiliary isolation capacitor 551 are provided in the first die; alternatively, the main isolation capacitor 511 and the auxiliary isolation capacitor 551 are provided in the second die; alternatively, the main isolation capacitor 511 is disposed in a first die and the auxiliary isolation capacitor 551 is disposed in a second die; alternatively, the main isolation capacitor 511 is disposed in the second die and the auxiliary isolation capacitor 551 is disposed in the first die.

In some embodiments, if the capacitance values of the main isolation capacitor 511, the first voltage dividing capacitor 512, the auxiliary isolation capacitor 551, and the second voltage dividing capacitor 552 are represented by C1, C2, C3, and C4, respectively, the capacitance ratio between the main isolation capacitor 511 and the first voltage dividing capacitor 512 is equal to the capacitance ratio between the auxiliary isolation capacitor 551 and the corresponding second voltage dividing capacitor 552 (i.e., c1:c2=c3:c4).

In some embodiments, the main isolation capacitor 511 and the auxiliary isolation capacitor 551 have the same capacitance value; the first voltage dividing capacitor 512 and the second voltage dividing capacitor 552 have the same capacitance value (i.e., c1=c3; c2=c4), which is advantageous for mass production, component purchase, and reduction of system cost. The system may be stable due to the same value between the capacitors.

Referring to fig. 6, fig. 6 schematically shows a timing diagram of the isolation circuit shown in fig. 5. As shown in fig. 5 and 6, waveforms A, B, C, D and E in fig. 6 represent signals at nodes A, B, C, D and E, respectively, in fig. 5. If the level of the input signal at node a is VDD, the level of the isolation signal at node C is C1/(c1+c2) ×vdd. Due to the inverter INV, the input signal at node B has an opposite phase to the inverted signal at node B'. So that the level at node C' is-C3/(c3+c4) ×vdd. Thus, the level at the node D is C1/(c1+c2) ×vdd+c3/(c3+c4) ×vdd. In some embodiments, the level at node D may have some amplification relative to the level at node C, e.g., the level at node D may be 3 times higher than the level at node C. After the latch signal is amplified by amplifier 53, the level at node E may have the same magnitude as the level at node a, or the latch signal may be amplified to a level required for further processing.

In some embodiments, the capacitance values of the first and second voltage dividing capacitors 512 and 552 may be 0, i.e., the second plates of the main and auxiliary isolation capacitors 511 and 551 do not receive a ground signal from the second chip. In practice, however, parasitic capacitance is also generated when the connection is broken. In some embodiments, the capacitance values of the first voltage dividing capacitor 512 and the second voltage dividing capacitor 552 may also be infinitely close to zero, but this is not meant to be limiting. The first voltage dividing capacitor 512 and the second voltage dividing capacitor 552 may also be a combination of the input capacitance of the circuit and other capacitances such as parasitic capacitance.

In some embodiments, the capacitance ratio between the main isolation capacitor 511 and the first voltage dividing capacitor 512 and the capacitance ratio between the auxiliary isolation capacitor 551 and the corresponding second voltage dividing capacitor 552 may be c1:c2=c3:c4=1:0. In practice, the large capacitance values of the main isolation capacitor 511 and the auxiliary isolation capacitor 551 increase the cost. In some embodiments, the capacitance ratio between the main isolation capacitor 511 and the first voltage dividing capacitor 512 is 1:0 to 1:1000, such as 1:10, 1:30, 1:50, 1:150, 1:200, etc. In some embodiments, the capacitance ratio between the main isolation capacitor 511 and the first voltage dividing capacitor 512 is 1:100.

Referring to fig. 7, fig. 7 schematically illustrates a diagram of an isolation circuit according to another embodiment of the present disclosure. The isolation circuit includes: an isolation module comprising a main isolation leg 71 and a common mode leg 75, a latch 72, an amplifier 73, a buffer 74 and an inverter 76. The main isolation branch 71 comprises a first voltage dividing capacitor 713 and the common mode branch 75 comprises a second voltage dividing capacitor 753.

The main difference from the isolation circuit shown in fig. 5 is that the first main isolation capacitor 711 and the second main isolation capacitor 712 are connected in series to form a main isolation capacitor, and the first auxiliary isolation capacitor 751 and the second auxiliary isolation capacitor 752 are connected in series to form an auxiliary isolation capacitor. The other components are similar to the isolation circuit shown in fig. 5 and will not be described in detail below.

In some embodiments, the first main isolation capacitor 711 and the second main isolation capacitor 712 are disposed in different die, and the first auxiliary isolation capacitor 751 and the second auxiliary isolation capacitor 752 are disposed in different die. For example, the first main isolation capacitor 711 and the first auxiliary isolation capacitor 751 may be disposed on a first die, and the second main isolation capacitor 712 and the second auxiliary isolation capacitor 752 may be disposed on a second die. Thus, the isolation circuit may have a higher isolation voltage, and the isolation circuit may be designed with more flexibility.

In some embodiments, the first main isolation capacitor 711 and the second main isolation capacitor 712 have the same capacitance value; and the first auxiliary isolating capacitor 751 and the second auxiliary isolating capacitor 752 have the same capacitance value.

The isolation circuit in the above embodiment provides a single channel isolation circuit. In some embodiments, two or more channels may be provided, such that the data transmission rate may be increased.

In a multi-channel isolation circuit, an isolation module includes two or more main isolation branches corresponding to two or more channels, respectively, and each of the main isolation branches includes a main isolation capacitor and a first voltage dividing capacitor connected in series. The latch module includes two or more latches corresponding to the two or more main isolation branches, respectively. The amplifier module includes two or more amplifiers corresponding to the two or more latches, respectively. The buffer module includes two or more buffers corresponding to the two or more main isolation branches, respectively.

In some embodiments, the isolation module further includes a common mode leg to reduce common mode noise and output a common mode signal to each of the two or more latches accordingly. All channels share the same common mode leg.

In some embodiments, the common mode leg includes an auxiliary isolation capacitor and a second voltage divider capacitor in series. The first plate of the auxiliary isolation capacitor is coupled to the ground signal of the first die, the first plate of each of the two or more voltage dividing capacitors and the first plate of the second voltage dividing capacitor are coupled to the ground signal of the second die, and the second plate of the second voltage dividing capacitor is respectively coupled to the input terminal of each of the two or more latches.

Referring to fig. 8, fig. 8 schematically illustrates a diagram of an isolation circuit according to another embodiment of the present disclosure. The isolation circuit includes: an isolation module comprising a first main isolation leg 81 and a common mode leg 85, a first latch 82, a first amplifier 83 and a first buffer 84. The main isolation branch 81 comprises a first main isolation capacitor 811 and a first voltage dividing capacitor 812 in series. The common mode leg comprises an auxiliary capacitor 851 and a second voltage divider capacitor 852 in series.

The isolation circuit as shown in fig. 8 further includes a second channel: the second channel includes a second main isolation leg 86, a second latch 87, a second amplifier 88, and a second buffer 89. The main isolation branch 86 includes a second main isolation capacitor 861 and a third voltage dividing capacitor 862 in series. Thus, the isolation circuit as shown in fig. 8 may transmit signals through the first channels of the first main isolation leg 81 and the common mode leg 85 and through the second channels of the second main isolation leg 86 and the common mode leg 85 simultaneously.

Specifically, the main isolation capacitor 861 includes a first plate coupled to the output terminal of the buffer 89 and a second plate coupled to the second plate of the first voltage dividing capacitor 862 and the first input terminal of the latch 87. A first plate of the first voltage dividing capacitor 862 receives a ground signal from the second die GND 2. Latch 87 includes a second plate for receiving a common mode signal from common mode leg 85 and an output terminal for outputting a latch signal to amplifier 88. The capacitance values of the capacitor 811, the capacitor 812, the capacitor 851, the capacitor 852, the capacitor 861, and the capacitor 862 are denoted by C1 to C6, respectively.

In some embodiments, the capacitance ratio between the main isolation capacitor and the respective voltage dividing capacitor in each main isolation branch is equal to the capacitance ratio between the auxiliary isolation capacitor and the respective second voltage dividing capacitor. That is, in the isolation circuit shown in fig. 8, c1:c2=c3:c4=c5:c6.

In some embodiments, the main isolation capacitor and the auxiliary isolation capacitor 851 in two or more main isolation branches have the same capacitance value; and the first voltage dividing capacitor and the second voltage dividing capacitor 852 in two or more main isolation branches have the same capacitance value. That is, in the isolation circuit shown in fig. 8, c1=c3=c5; c2 =c4=c6.

In some embodiments, the isolation circuit may also include multiple channels.

Since the capacitor is a silicon dioxide device, there is no aging problem of the optocoupler. Furthermore, the isolation circuit provides isolation through the isolation capacitor so that the input signal can pass directly through the isolation medium. Therefore, the isolation circuit has stable quality, long service life and low cost.

Referring to fig. 9, fig. 9 schematically illustrates a diagram of an isolation circuit according to another embodiment of the present disclosure. The isolation circuit includes: an isolation module comprising a main isolation leg 91, a latch 92, an amplifier 93 and a buffer 94. The isolation module shown in fig. 8 includes a first inductor 911 and a second inductor 912. There is no electrical connection between the first inductor 911 and the second inductor 912 and the signal is sent through the magnetic field, so that electrical isolation can be achieved. The latch 92 is required to latch the isolation signal to a certain level and output a latch signal. The isolation signal in the inductive isolation module is a current signal.

The first inductor 911 includes a first terminal coupled to an output terminal of the buffer 94 to receive an input signal, and a second terminal coupled to a fixed voltage V1. The second inductor 912 includes a first terminal coupled with the first input terminal of the latch 92 to output an isolation signal to the latch module, and a second terminal coupled with the fixed voltage V2. The amplifier 93 is similar to the amplifier in the above isolation circuit, and will not be described in detail hereinafter.

Referring to fig. 10, fig. 10 schematically illustrates a diagram of an isolation circuit according to another embodiment of the present disclosure. The isolation circuit includes: an isolation module comprising a main isolation leg 101 and a common mode leg 105, a latch 102, an amplifier 103 and a buffer 104. The main isolation leg 101 includes a first inductor 1011 and a second inductor 1012.

In comparison to fig. 9, the isolation circuit in fig. 10 further comprises a common mode leg 105. The common mode leg 105 is coupled to the ground signal GND1 of the first die and the input terminal of the latch 102 to reduce common mode noise on the first die and the second die and output the common mode signal to the latch 102. Specifically, common mode leg 116 includes a third inductor 1051 and a fourth inductor 1052. The third inductor 1051 includes a first terminal for receiving a ground signal GND1 of the first die and a second terminal coupled to a fixed voltage V1. The fourth inductor 1052 includes a first terminal that outputs a common mode signal to the latch 102 and a second terminal coupled to a fixed voltage V2. In some embodiments, latch 102 may be a current latch. The other components are similar to the isolation circuit shown in fig. 9 and will not be described in detail below.

Referring to fig. 11, fig. 11 schematically illustrates a diagram of an isolation circuit according to another embodiment of the present disclosure. The isolation circuit includes: an isolation module comprising a main isolation leg 111 and a common mode leg 116, a latch 112, an amplifier 113, a buffer 114 and an inverter 115. The main isolation leg 111 includes a first inductor 1111 and a second inductor 1112.

In comparison to fig. 9, the isolation circuit in fig. 11 further comprises an inverter 115 and a common mode leg 116. The inverter 115 is configured to invert an input signal into an inverted input signal, and includes an input terminal coupled with the input signal, and an output terminal for outputting the inverted input signal. The common mode leg 116 is used to reduce common mode noise on the first die and the second die and to output a common mode signal to the latch 112. Specifically, common-mode leg 116 includes a third inductor 1161 and a fourth inductor 1162. The third inductor 1161 includes a first terminal for receiving an inverted input signal and a second terminal coupled to a fixed voltage V1. The fourth inductor 1162 includes a first terminal outputting a common mode signal to the latch 112 and a second terminal coupled to a fixed voltage V2. The other components are similar to the isolation circuit shown in fig. 9 and will not be described in detail below.

In some embodiments, the fixed voltage V1 and the fixed voltage V2 may be VDD or 1/2VDD or other values.

In some embodiments, the latch module includes at least one latch, each of the latches having a roll-over voltage of 10 mV-60 mV or a roll-over current of 30 uA-1 mA corresponding to the voltage signal or the current signal, respectively.

Embodiments of the present disclosure also provide a method for providing isolation between two dies. Fig. 12 schematically illustrates a flow chart of a method for providing isolation between two dies according to an embodiment of the disclosure; and fig. 13 schematically illustrates a flow chart of a method for providing isolation between two dies according to another embodiment of the present disclosure.

As shown in fig. 12, the method includes S11, S13, and S15.

In S11: an isolation signal is generated based on the input signal from the first die and isolation is provided between the first die and the second die, wherein an amplitude of the isolation signal is less than an amplitude of the input signal.

In S13: the isolated signal is latched at a level to form a latched signal.

In S15: the latch signal is amplified.

In some embodiments, the method further comprises a filtering step. As shown in fig. 13, the method for isolating two dies includes S21, S23, S25, and S27. In S21, the input signal is filtered before the isolated voltage is generated. The other steps of S23, S25 and S27 are similar to the corresponding steps in fig. 12. The methods of fig. 12 and 13 may be implemented in any system that includes isolation circuitry according to embodiments of the present disclosure. For more details of this method reference is made to the description of the isolation circuit and will not be described in detail below.

Fig. 14 schematically illustrates a diagram of an isolation system 1400 according to an embodiment of the disclosure. The diagram is merely an example, which should not unduly limit the scope of the claims. Those of ordinary skill in the art will recognize many variations, alternatives, and modifications. As shown in fig. 14, the isolation system 1400 includes two stages: an input stage 1410 and an isolation stage 1420. Input stage 1410 converts a single input into a pair of differential inputs. The isolation stage 1420 includes a first input buffer 1401 and a second input buffer 1405, a latch 1402, and an amplifier 1403. For example, the first input buffer 1401 may be referred to as a first isolation module. The second input buffer 1405 may be referred to as a second isolation module. The first isolation module 1401 may include a main isolation capacitor 1411 and a first voltage dividing capacitor 1412 in series. In some cases, the latch 1402 may be referred to as a latch circuit.

The first input buffer 1401 is configured to receive a first differential signal (i.e. from node B) and to provide a second differential signal (at node "C"). For example, the first differential signal may be characterized by a first magnitude, the second differential signal may be characterized by a second magnitude (e.g., measured in voltage magnitude), and the first magnitude may be greater than the second magnitude. It should be appreciated that one of the functions of the isolation system 1400 is to accommodate different voltage levels between different circuits. In some embodiments, the transmitter is configured on a first die (e.g., die 1) and is coupled to a first ground terminal (e.g., GND 1). The first input buffer 1401 is shown coupled to a second ground terminal (e.g., GND 2). According to some embodiments, the second input buffer 1405 may be configured to receive a third differential signal (from node B ') and provide a fourth differential signal (at node C'). For example, the first differential signal and the third differential signal may constitute a pair of differential signals. Similarly, the second differential signal and the fourth differential signal may constitute a pair of differential signals. The second input buffer 1405 is coupled to a second ground terminal (e.g., GND 2). As described below, the difference between the first ground GND1 and the second ground GND2 may generate a common mode transient problem, which needs to be solved (see fig. 17 and the following description thereof).

In some embodiments, the main isolation capacitor 1411 in the first isolation module 1401 may include a first plate configured to receive a first input signal (i.e., a first differential signal) and a second plate coupled to a first input terminal of the latch 1402. The first voltage dividing capacitor 1412 may include a first plate coupled to a second ground terminal (e.g., GND 2) and a second plate coupled to the second plate of the main isolation capacitor 1411 and the first input terminal of the latch 1402. For example, the main isolation capacitor 1411 of the first isolation module 1401 may be referred to as a first capacitor, and the first voltage dividing capacitor 1412 of the first isolation module 1401 may be referred to as a second capacitor. In some embodiments, the first capacitor may be directly coupled to the first differential signal and the second capacitor may be directly coupled to the second ground terminal (e.g., GND 2).

In some embodiments, the second isolation module 1405 may be configured to generate a second isolation signal (i.e., a fourth differential signal) based on the second input signal (i.e., the third differential signal) and provide isolation between the first die and the second die.

According to some embodiments, the first input signal and the second input signal may be configured as differential pairs. Thus, the first isolated signal (i.e., the second differential signal) and the second isolated signal (i.e., the fourth differential signal) may also be configured as differential pairs. When the common mode noise increases significantly, for example, when it reaches the same level as the desired signal (for example, 100V/ns), the noise signal may have a significant effect on the desired signal and may cause problems such as signal distortion or loss. The first input signal and the second input signal configured as differential pairs may reduce common mode noise.

As a physical isolation mechanism, the isolation circuit may be configured to separate dies. For example, the isolation circuit may include a transmitter and a receiver, with the transmitter being configured on a first die and the receiver being configured on a second die. The transmitter circuit operates on a first supply voltage VDD1 and a first ground GND1, and the receiver circuit operates on a second supply voltage VDD2 and a second ground GND 2. The transmitter may convert an input signal into a digital signal as a first input signal (i.e., a first differential signal) and drive the first isolation module 1401. The inverter 1406 may be configured to invert the first input signal and generate a second input signal (i.e., a third differential signal) and drive the second isolation module 1405. The first input signal and the second input signal may be configured as a pair of differential signals, which reduces common mode transients during signal transmission.

In some embodiments, the second isolation module 1405 may include an auxiliary isolation capacitor 1451 and a second voltage dividing capacitor 1452 configured in series. Auxiliary isolation capacitor 1451 may include a first plate configured to receive a second input signal (i.e., a third differential signal) and a second plate coupled to a second input terminal of latch 1402. The second voltage divider capacitor 1452 may include a first plate coupled to a second ground terminal (e.g., GND 2) and a second plate coupled to the second plate of the auxiliary isolation capacitor 1451 and the second input terminal of the latch 1402. For example, the auxiliary isolation capacitor 1451 of the second isolation module 1405 may also be referred to as a third capacitor, and the second voltage dividing capacitor 1452 may also be referred to as a fourth capacitor. In some embodiments, the third capacitor may be directly coupled to the third differential signal and the fourth capacitor may be directly coupled to the second ground terminal (e.g., GND 2).

Due to the voltage dividing capability of the capacitor, the magnitude of the first isolation signal may be less than the magnitude of the first input signal and the magnitude of the second isolation signal may be less than the magnitude of the second input signal. For example, a first differential signal may be characterized by a first magnitude, a second differential signal may be characterized by a second magnitude, and the first magnitude may be greater than the second magnitude. Similarly, the third differential input signal may be characterized by a third magnitude, the fourth differential signal may be characterized by a fourth magnitude, and the third magnitude may be greater than the fourth magnitude. That is, the magnitudes of the levels of the isolation signals at nodes C and C 'may be lower than the magnitudes of the levels of the input signals at nodes B and B', respectively. The main isolation capacitor 1411 and the auxiliary isolation capacitor 1451 may be configured to provide isolation between the first die and the second die. The isolation voltage has a wide range and can be as high as 20,000v.

In some embodiments, the main isolation capacitor 1411 and the auxiliary isolation capacitor 1451 may have various arrangements. In some embodiments, at least one of the main isolation capacitor 1411 and the auxiliary isolation capacitor 1451 may be configured on the first die or the second die. The flexible arrangement of the main isolation capacitor 1411 and the auxiliary isolation capacitor 1451 facilitates circuit design and digital isolation.

In some embodiments, the capacitance values of the main isolation capacitor 1411 and the auxiliary isolation capacitor 1451 may be flexibly designed based on the requirements of the integrated circuit, typically, but not limited to, their capacitance values are less than 100fF. According to some embodiments, the capacitance values of the first voltage dividing capacitor 1412 and the second voltage dividing capacitor 1452 may mainly include the input parasitic capacitance of the receiver circuit, typically their capacitance values are less than 1pF. The larger the capacitance of each capacitor, the smaller the voltage input to the latch 1402.

In some embodiments, if the capacitance values of the main isolation capacitor 1411, the first voltage dividing capacitor 1412, the auxiliary isolation capacitor 1451, and the second voltage dividing capacitor 1452 are represented by C1, C2, C3, and C4, respectively, the capacitance ratio between the main isolation capacitor 1411 and the first voltage dividing capacitor 1412 may be equal to the capacitance ratio between the auxiliary isolation capacitor 1451 and the second voltage dividing capacitor 1452 (i.e., c1:c2=c3:c4). The capacitance ratio between each capacitor may be associated with the input signal of latch 1402.

In some embodiments, the main isolation capacitor 1411 and the auxiliary isolation capacitor 1451 may have the same capacitance value; the first and second voltage dividing capacitors 1412 and 1452 may have the same capacitance value (i.e., c1=c3; c2=c4; which is advantageous for mass production, reduction of manufacturing costs, and system stability.

In some embodiments, the input signal is filtered before being sent to the isolation module. As shown in fig. 14, the buffer 1404 may include an input configured to receive an input signal from a transmitter, and an output terminal configured to perform filtering on the input signal and output the filtered signal to an isolation module (e.g., the first input buffer 1401 and/or the second input buffer 1405). The buffer 1404 may be configured on the first die. It should be noted that the buffer 1404 is not a mandatory component in the isolation circuit.

In some embodiments, inverter 1406 may be configured to invert an input signal and output the inverted signal. For example, inverter 1406 generates an inverted signal at node B' that is formed as the second signal of the differential pair (the first signal at node B). For example, if the first stage 1410 has received a differential input signal as its input, then the inverter 1406 is not required and a second buffer may be configured in place of the inverter 1406. The inverter 1406 may include an input terminal configured to receive an input signal (i.e., a first differential signal) and an output terminal configured to output an inverted signal (i.e., a third differential signal). According to some embodiments, an input terminal of the inverter 1406 may be coupled to the first isolation module 1401 and an output terminal of the inverter 1406 may be coupled to the second isolation module 1405. In some cases, an input terminal of the inverter 1406 may be coupled to the second isolation module 1405 and an output terminal of the inverter 1406 may be coupled to the first isolation module 1401. In some embodiments, the inverter 1406 may be configured on the first die. According to some embodiments, the inverter 1406 may be configured to generate a third differential signal.

In some embodiments, the latch 1402 stores the isolated signal (e.g., the differential signal at nodes C and C') at a predetermined level (or within a certain range) for a certain time interval and outputs a latch signal. The latch 1402 may include, but is not limited to, a first input terminal configured to receive a first isolation signal, a second input terminal configured to receive a second isolation signal, and an output terminal configured to output a latch signal. In some cases, the latch 1402 may have a small flip voltage to identify digital signals having small amplitude differences, so that even small signal differences may be identified. According to some embodiments, latch 1402 comprises a voltage latch. For example, the latch 1402 may also be referred to as a latch circuit.

In some embodiments, amplifier 1403 may be configured to amplify the latch signal. Amplifier 1403 is coupled to latch/latch circuit 1402. For example, the amplifier 1403 is configured to provide amplification in a predetermined range; in some cases attenuation rather than amplification is required.

Fig. 15 schematically shows a timing diagram of the isolation circuit shown in fig. 14 when there is no Common Mode Transient (CMT) between the first die and the second die. As described above, the first die and the second die are configured on different power supply voltages and are connected to separate ground terminals. According to some embodiments, when there is no CMT between the first die and the second die, the common mode voltage at node C may be the same as the supply voltage of the second die (e.g., VDD 2), and the common mode voltage at node C' may also be the same as the supply voltage of the second die (e.g., VDD 2). There may be no common mode current between the first die and the second die caused by the CMT. The differential mode voltage between nodes C and C' may be relatively low, and thus, the level of the isolation signal output to the latch circuit 1402 may be correspondingly relatively low.

Fig. 16 schematically showsThe timing diagram of the isolation circuit shown in fig. 14 when a CMT is present between the first die and the second die. For example, when CMT occurs between a first die and a second die, common mode current generated by the CMT flows through isolation gates (e.g., first input buffer and/or second input buffer). As shown in fig. 16, the common mode voltages at nodes C and C' may change significantly suddenly during CMT, which may result in signal transmission errors. For example, bit errors tend to occur in the region 1601 shown. For example, when there is no CMT, the signal transmission is not interrupted, as shown in region 1602. Common mode voltage Δv at the input terminals of latch 1402 _cm The variation of (2) may be represented by the following equation:

ΔV _cm ＝I _cm ×R _cm

wherein I is _cm Is a common mode current generated by CMT, R _cm Is the common mode input impedance of the latch 1402.

In effect, the common mode impedance mismatch between the two input terminals of latch 1402 may convert the common mode voltage to a differential mode voltage that results in a signal transmission error. By common mode impedance mismatch Rmis _cm Differential mode voltage V caused _dm This can be expressed by the following equation:

V _dm ＝I _cm ×Rmis _cm

to improve the CMTI of the isolation circuit, the latch should have a low common mode input impedance value R _cm And low common mode impedance mismatch Rmis _cm °

Fig. 17 schematically illustrates a simplified diagram of an isolation circuit according to an embodiment of the disclosure. The diagram is merely an example, which should not unduly limit the scope of the claims. Those of ordinary skill in the art will recognize many variations, alternatives, and modifications. As shown, the isolation circuit includes a buffer 1704, an inverter 1706, a first isolation block 1701, a second isolation block 1705, a common mode block 1707, a latch 1702, and an amplifier 1703. The common mode block 1707 may be coupled in parallel to the latch 1702. In some cases, the latch 1702 may be referred to as a latch circuit.

For example, the first isolation module 1701 may be referred to as a first input buffer. The second isolation module 1705 may be referred to as a second input buffer. The differential input signals are configured at nodes B and B'. The first isolation module 1701 receives a first differential signal at a node B. The output of the first isolation module 1701 is configured at node C. For example, a differential signal from a transmitter is received. The second isolation module 1705 receives a second differential signal at node B'. The output of the second isolation module 1705 is configured at node C'.

As mentioned above, the purpose of the isolation circuit is to accommodate different signal voltage levels present in different electrical components and circuits. The first differential input signal (e.g., at node B) is characterized by a first magnitude and the second differential signal (e.g., at node C) is characterized by a second magnitude. For example, the first magnitude may be greater than the second magnitude. It should be appreciated that the voltage level differences may be accommodated by setting the input buffers 1701 and 1702.

For example, portions 1730 and 1740 are configured on two different dies, each die having its own ground terminal. In some embodiments, the transmitter may be configured on the first die and coupled to the first ground terminal. The first input buffer 1701 may be coupled to a second ground terminal (e.g., GND 2). According to some embodiments, the second input buffer 1705 may be configured to receive a third differential signal from the transmitter and provide a fourth differential signal. For example, the third differential input signal may be characterized by a third magnitude, the fourth differential signal may be characterized by a fourth magnitude, and the third magnitude may be greater than the fourth magnitude. The second input buffer 1705 may be coupled to a second ground terminal GND2.

For example, the common mode block 1707 includes a common mode circuit. The common mode circuit may be coupled to a bias voltage (e.g., V _bias ) And may include a resistor pair. The common mode circuit may be configured to reduce a common mode transient voltage, which may be associated with a voltage difference between GND1 and GND2, respectively, for two different die configurations. The common mode circuit 1707 may be configured on a second die. In some embodiments, the transmitter and common mode circuit 1707 configured on different dies may introduce common mode transient voltages, which may break down Bad valid differential signaling. The common mode circuit 1707 is configured to reduce common mode transient voltages, thereby reducing or eliminating such disruptions and improving signal transmission. The first isolation block 1701, the second isolation block 1705, the latch 1702, the amplifier 1703, the buffer 1704, and the inverter 1706 are similar to the above circuits, and will not be described in detail below.

In some embodiments, the common mode block 1707 may include, but is not limited to, a first input terminal coupled to a first latch input terminal of the latch 1702 and a second latch input terminal coupled to a second input terminal of the latch 1702. The first input terminal of the common mode block 1707 and the second input terminal of the common mode block 1707 may have low impedance values and be properly matched. According to some embodiments, the common mode module 1707 is configured in the signal path to accommodate common mode current flow caused by CMT so that common mode transient voltages can be reduced. When CMT occurs between the first die and the second die, the common mode current induced by CMT will flow through common mode block 1707 and thus the variation of the common mode voltage at nodes C and C' can be reduced; the common mode voltage converted to a differential mode voltage can also be reduced, thereby enhancing the CMTI of the isolation circuit.

Fig. 18 schematically illustrates a diagram of a common mode module according to an embodiment of the disclosure. The diagram is merely an example, which should not unduly limit the scope of the claims. Those of ordinary skill in the art will recognize many variations, alternatives, and modifications. In some embodiments, the common mode module 1807 may include a first input terminal configured to receive a first common mode input signal (i.e., a second differential signal), a second input terminal configured to receive a second common mode input signal (i.e., a fourth differential signal), a first resistor 1871 coupled to the first input terminal of the common mode module 1807, and a second resistor 1872 coupled to the second input terminal of the common mode module 1807. For example, first resistor 1871 and second resistor 1872 may also be referred to as a resistor pair. A first input terminal of the common mode module 1807 may be coupled to a first latch input terminal and a second input terminal of the common mode module 1807 may be coupled to a second latch input terminal.

First resistor 1871 and second resistor 1872 are coupled to a bias voltage (e.g., V _bias ). Bias voltage V _bias May be ground, or a supply voltage for the second die, or a bias voltage having a specified value. In some embodiments, the bias voltage V _bias May be associated with a common mode input voltage of a latch (not shown). For example, bias voltage V of latch _bias And the common-mode input voltage may both be coupled to a supply voltage (e.g., VDD 2) of the second die. When there is no CMT, the common mode voltage at nodes C and C' will be approximately equal to VDD2 and common mode block 1807 is turned off.

According to some embodiments, positive CMT occurs when the voltage difference between the first ground terminal (e.g., GND 1) and the second ground terminal (e.g., GND 2) increases, and common mode current flows from the first die to the second die through common mode module 1807. When the voltage difference between the grounds of the first ground terminal (e.g., GND 1) and the second ground terminal (e.g., GND 2) decreases, negative CMT occurs and common mode current flows from the second die to the first die through common mode module 1807. In some embodiments, first resistor 1871 and second resistor 1872 may have low impedance values such that common mode voltage Δv at nodes C and C' may be reduced _cm Is a variation of (c). The mismatch in the impedance values of first resistor 1871 and second resistor 1872 converts the common mode voltage variation to a differential mode voltage, and proper matching of the impedance values of first resistor 1871 and second resistor 1872 may reduce the converted differential mode voltage, and thus may enhance effective signal transmission.

Fig. 19 schematically illustrates a diagram of a common mode module according to another embodiment of the disclosure. The diagram is merely an example, which should not unduly limit the scope of the claims. Those of ordinary skill in the art will recognize many variations, alternatives, and modifications. As described above, the common mode module 1907 may also be referred to as a common mode circuit. The common mode circuit 1907 may include a crossover circuit. The crossover circuit may include a first switch and a second switch. For example, the crossover circuit may include a P-type MOSFET (also referred to as a "PMOS transistor") configured in the crossover circuit. In some embodiments, the common mode module 1907 may include a first input terminal configured to receive a first common mode input signal (i.e., a second differential signal), a second input terminal configured to receive a second common mode input signal (i.e., a fourth differential signal), a first P-type MOSFET 1981 (i.e., a first switch), a second P-type MOSFET 1982 (i.e., a second switch), a first resistor 1991, and a second resistor 1992. According to some embodiments, the first P-type MOSFET 1981 and the second P-type MOSFET 1982 may be configured as a cross-coupled pair (i.e., a cross-circuit).

In some embodiments, the drain of the first P-type MOSFET 1981 and the gate of the second P-type MOSFET 1982 may be coupled to a first latch input terminal (e.g., node C); the gate of the first P-type MOSFET 1981 and the drain of the second P-type MOSFET 1982 may be coupled to a second latch input terminal (e.g., node C'); the source of the first P-type MOSFET 1981 and the source of the second P-type MOSFET 1982 may be coupled together to a bias voltage V _bias . In some embodiments, the bias voltage V _bias May be ground, or a supply voltage of the second die (e.g., VDD 2), or a bias voltage having a specified value. In some embodiments, the bias voltage V _bias May be associated with a common mode input voltage of the latch.

In some cases, the first terminal of the first resistor 1991 and the first terminal of the second resistor 1992 may be coupled together to a supply voltage of the second die VDD 2. A second terminal of the first resistor 1991 may be coupled to the substrate of the first P-type MOSFET 1981 and a second terminal of the second resistor 1992 may be coupled to the substrate of the second P-type MOSFET 1982. The impedance values of the first resistor 1991 and the second resistor 1992 may be associated with the common mode current generated due to the CMT such that the common mode current may be adjusted by adjusting the impedance values of the resistors. The first resistor 1991 may be configured to reduce the current flowing through the substrate of the first P-type MOSFET 1981 during CMT. The second resistor 1992 can be configured to reduce the current flowing through the substrate of the second P-type MOSFET1982 during CMT.

Fig. 20 schematically illustrates a simplified diagram of an isolation circuit according to another embodiment of the present disclosure. The diagram is merely an example, which should not unduly limit the scope of the claims. Those of ordinary skill in the art will recognize many variations, alternatives, and modifications. As described above, the common mode module 2007 may also be referred to as a common mode circuit 2007. Common mode circuitry 2007 may include crossover circuitry. In some embodiments, the common mode module 2007 may be disposed on a second die (VDD 2, GND 2). In some implementations, the transmitter Tx 2001 may be configured on the first die. The transmitter Tx may be coupled to a first isolation module 2061 and a second isolation module 2062, respectively. In some cases, the first isolation module 2061 may be referred to as a first input buffer and the second isolation module 2062 may be referred to as a second input buffer.

For example, common mode circuit 2007 may be coupled to a supply voltage (e.g., VDD 2). In some cases, common mode circuit 2007 may be coupled to a second ground terminal (e.g., GND 2). For example, the common mode circuit 2007 may include a first switch and a second switch configured in a crossover configuration (i.e., a crossover circuit). The first switch may include a first P-type MOSFET 2081 and the second switch may include a second P-type MOSFET 2082. When there is no CMT, the voltages at nodes C and C' are relatively low, and the first switch (e.g., first P-type MOSFET 2091) and the second switch (e.g., second P-type MOSFET 2092) may be turned off. When the voltage difference between the first ground terminal (e.g., GND 1) and the second ground terminal (e.g., GND 2) decreases, a negative CMT 2004 occurs between the first die and the second die, and the common mode current generated by the CMT flows in the first direction 2003, i.e., from nodes C and C' to the first die through the first isolation module 2061 and the second isolation module 2062. Thus, the voltages at nodes C and C' may be lower than the bias voltage V _bias The first switch (e.g., the first P-type MOSFET 2091) and the second switch (e.g., the second P-type MOSFET 2092) may be turned on.

According to some embodiments, the common mode current may be associated with a common mode input impedance and a differential mode input impedance of the common mode module 2007. As the common mode current increases, the common mode input impedance decreases and the differential mode input impedance correspondingly increases. Thus, when CMT occurs, the common mode voltage caused by CMT may decrease and the differential mode voltage may increase, thereby enhancing the CMTI of the isolation circuit and amplifying the effective differential input signal of the latch 2002.

Common mode input impedance R of common mode block 2007 _com This can be expressed by the following equation:

wherein g _mp Is the transconductance of the cross-coupled MOSFETs (i.e., the first P-type MOSFET 2091 and the second P-type MOSFET 2092). The differential-mode input impedance of the common-mode module 2007 can be represented by the following equation:

in some cases, transconductance g _mp May be proportional to the common mode current generated by the CMT. As shown in the above equation, the larger the transconductance, the smaller the common-mode input impedance and the larger the differential-mode input impedance. Due to the impedance characteristics of the common mode module 2007, when negative CMT occurs between the first die and the second die, common mode noise may decrease and the magnitude of the effective differential input signal of the latch 2002 may increase. Thus, the common mode module 2007 may be configured to enhance the CMTI of the isolation circuits and increase the effective differential input signal of the latch 2002.

Fig. 21 schematically shows a timing diagram of the isolation circuit shown in fig. 20 when negative CMT occurs. For example, when a negative CMT occurs between a first die and a second die, common mode current generated by the CMT flows from the second die to the first die through isolation gates (e.g., first input buffer and/or second input buffer). As shown in fig. 21, the common mode voltage at nodes C and C 'may be lower than VDD2 at regions 2101 and 2102 during CMT, common mode module 2007 (i.e., the first switch and/or the second switch) may be on, and the differential mode voltage between nodes C and C' may increase during CMT, so the effective differential input signal of the latch may increase at region 2103, as shown.

Fig. 22 schematically illustrates a simplified diagram of a common mode module 2207 according to another embodiment of the disclosure. As described above, the common mode module 2207 may also be referred to as a common mode circuit. The common mode circuit 2207 may include a crossover circuit. The crossover circuit may include a first switch and a second switch. For example, the crossover circuit may include an N-type MOSFET (also referred to as an "NMOS transistor") configured in the crossover circuit. In some embodiments, the common mode module 2207 includes a first input terminal configured to receive a first common mode input signal (i.e., a second differential signal), a second input terminal configured to receive a second common mode input signal (i.e., a fourth differential signal), a first N-type MOSFET 2281 (i.e., a first switch), a second N-type MOSFET2282 (i.e., a second switch), a first resistor 2291, and a second resistor 2292.

The first resistor 2291 and the second resistor 2292 may also be referred to as a resistor pair. The first switch (i.e., first N-type MOSFET 2281) may be coupled to the second differential signal and the second switch (i.e., second N-type MOSFET 2282) may be coupled to the fourth differential signal.

According to some embodiments, the first N-type MOSFET 2281 and the second N-type MOSFET2282 may be configured as a cross-coupled pair (i.e., a cross-circuit). The drain of the first N-type MOSFET 2281 and the gate of the second N-type MOSFET2282 may be coupled to a first latch input terminal; the gate of the first N-type MOSFET 2281 and the drain of the second N-type MOSFET2282 may be coupled to a second latch input terminal; the source of the first N-type MOSFET 2281 and the source of the second N-type MOSFET2282 may be coupled together to a bias voltage V _bias . In some embodiments, the bias voltage V _bias May be ground, or a supply voltage for the second die, or a bias voltage having a specified value.

In some embodiments, the bias voltage V _bias May be associated with a common mode input voltage of the latch. In some cases, the first terminal of the first resistor 2291 and the first terminal of the second resistor 2292 may be coupled together to a second ground terminal (e.g., GND 2). A second terminal of the first resistor 2291 may be coupled to the substrate of the first N-type MOSFET2281 and a second terminal of the second resistor 2292 may be coupled to the substrate of the second N-type MOSFET 2282. The impedance values of the first resistor 2291 and the second resistor 2292 may be equal to those due to CThe common mode currents generated by MT are correlated so that the common mode currents can be adjusted by adjusting the impedance values of the resistors (e.g., 2291, 2292). The first resistor 2291 may be configured to reduce the current flowing through the substrate of the first N-type MOSFET2281 during CMT. The second resistor 2292 may be configured to reduce the current flowing through the substrate of the second P-type MOSFET 2282 during CMT.

In some embodiments, when the voltage difference between the first ground terminal (e.g., GND 1) and the second ground terminal (e.g., GND 2) increases, positive CMT occurs between the first die and the second die, and common mode current generated by the CMT flows from the first die to nodes C and C' through the first input buffer and/or the second input buffer. Thus, the voltages at nodes C and C' may be higher than the bias voltage V _bias The first switch (e.g., first N-type MOSFET 2291) and the second switch (e.g., second N-type MOSFET 2292) may be turned on. According to some embodiments, the common mode current may be associated with a common mode input impedance and a differential mode input impedance of the common mode module 2207. As the common mode current increases, the common mode input impedance decreases and the differential mode input impedance correspondingly increases. Thus, when CMT occurs, the common mode voltage caused by CMT may decrease and the differential mode voltage may increase, thereby enhancing the CMTI of the isolation circuit and amplifying the effective differential input signal of the latch. That is, the common mode module 2207 may be configured to enhance the CMTI of the isolation circuits and increase the effective differential input signal of the latches.

Fig. 23 schematically illustrates a diagram of a common mode module according to another embodiment of the disclosure. The diagram is merely an example, which should not unduly limit the scope of the claims. Those of ordinary skill in the art will recognize many variations, alternatives, and modifications. As described above, the common mode module 2307 may also be referred to as a common mode circuit. The common mode circuit 2307 may include a first cross circuit 2308 and a second cross circuit 2309. For example, the first crossbar 2308 may include P-type MOSFETs (also referred to as "PMOS transistors") configured in the crossbar. For example, the second crossover circuit 2309 may include an N-type MOSFET (also referred to as an "NMOS transistor") configured in the crossover circuit. According to some embodiments, the first cross-over circuit 2308 may be coupled to a supply voltage (e.g., VDD 2) and the second cross-over circuit 2309 may be coupled to a second ground terminal (e.g., GND 2). In some embodiments, the common mode module 2307 may include a first input terminal configured to receive a first common mode input signal (i.e., a second differential signal), a second input terminal configured to receive a second common mode input signal (i.e., a fourth differential signal), a first crossover circuit 2308 (also referred to as a "first common mode leg"), and a second crossover circuit 2309 (also referred to as a "second common mode leg"). The first common mode leg 2308 may include a first P-type MOSFET 2311, a second P-type MOSFET 2312, a first resistor 2301, and a second resistor 2302. The second common mode leg 2309 may include a first N-type MOSFET 2321, a second N-type MOSFET 2322, a third resistor 2331, and a fourth resistor 2332. The first common mode leg 2308 and the second common mode leg 2309 may be connected in parallel.

The impedance characteristics of the first cross circuit 2308 are similar to those of the common mode module 2007 shown in fig. 20, and the impedance characteristics of the second cross circuit 2309 are similar to those of the common mode module 2207 shown in fig. 22. In some embodiments, when the voltage difference between the first ground terminal GND1 and the second ground terminal GND2 decreases, a negative CMT occurs between the first die and the second die, and the common mode current generated by the CMT flows from nodes C and C' to the first die through the first isolation module (i.e., the first input buffer) and/or the second isolation module (i.e., the second input buffer). Thus, the voltages at nodes C and C' may be lower than the bias voltage V _bias The first common mode leg 2308 may be on, i.e., the first P-type MOSFET 2311 and the second P-type MOSFET 2312 may be on, while the second common mode leg 2309 is off at the same time.

The common mode current generated due to the negative CMT may be associated with the common mode input impedance and the differential mode input impedance of the first common mode leg 2308. As the common mode current increases, the common mode input impedance decreases and the differential mode input impedance correspondingly increases. Thus, when negative CMT occurs, the common mode voltage caused by CMT may decrease and the differential mode voltage may increase, thereby enhancing the CMTI of the isolation circuit and amplifying the effective differential input signal of the latch. The common-mode input impedance and the differential-mode input impedance of the first common-mode branch 2308 may be associated with the impedance values of each P-type MOSFET (e.g., 2311, 2312) and each resistor (e.g., 2301, 2302) of the first common-mode branch 2308. The first common mode leg 2308 may be configured to enhance the CMTI of the isolation circuit and increase the effective differential input signal of the latch during negative CMT.

When the voltage difference between the first ground terminal GND1 and the second ground terminal GND2 increases, a positive CMT occurs between the first die and the second die, and a common mode current generated by the CMT flows from the first die to the nodes C and C' through the first isolation module (i.e., the first input buffer) and the second isolation module (i.e., the second input buffer). Thus, the voltages at nodes C and C' may be higher than the bias voltage V _bias The second common mode leg 2309 may be on while the first common mode leg 2308 is off. The common mode current generated due to the positive CMT may be associated with the common mode input impedance and the differential mode input impedance of the second common mode leg 2309. As the common mode current increases, the common mode input impedance decreases and the differential mode input impedance correspondingly increases. Thus, when positive CMT occurs, the common mode voltage caused by CMT may decrease and the differential mode voltage may increase, thereby enhancing the CMTI of the isolation circuit and amplifying the effective differential input signal of the latch.

The common-mode input impedance and the differential-mode input impedance of the second common-mode leg 2309 may be associated with the impedance value of each N-type MOSFET (e.g., 2321, 2322) and each resistor (e.g., 2331, 2332) of the second common-mode leg 2309. The second common mode leg 2309 may be configured to enhance the CMTI of the isolation circuit and increase the effective differential input signal of the latch during positive CMT. The structure and operation of the common mode module 2307 prevents the isolation circuit from being disturbed by common mode transients regardless of the direction of the common mode current.

To increase flexibility in circuit design and enable flexible adjustment of the impedance value of the common mode circuit 2307, it should be appreciated that the first common mode leg 2308 may also include a first diode (not shown) configured to be connected in parallel with the first P-type MOSFET 2311 and the second P-type MOSFET2312, and/or the second common mode leg 2309 may also include a second diode (not shown) configured to be connected in parallel with the first N-type MOSFET 2321 and the second N-type MOSFET 2322.

Fig. 24 schematically illustrates a diagram of a common mode module according to another embodiment of the disclosure. The diagram is merely an example, which should not unduly limit the scope of the claims. Those of ordinary skill in the art will recognize many variations, alternatives, and modifications. As described above, the common mode module 2407 may also be referred to as a common mode circuit. The common mode circuit 2407 may include a crossover circuit. The crossover circuit may include a first switch and a second switch. For example, the crossover circuit may include BJT transistors configured in the crossover circuit. In some embodiments, the common mode module 2407 may include a first input terminal configured to receive a first common mode input signal (i.e., a second differential signal), a second input terminal configured to receive a second common mode input signal (i.e., a fourth differential signal), a first PNP transistor 2471 (i.e., a first switch), and a second PNP transistor 2472 (i.e., a second switch). According to some embodiments, the first PNP transistor 2471 and the second PNP transistor 2472 can be configured as a cross-coupled pair (i.e., a cross-circuit).

The collector terminal of the first PNP transistor 2471 and the base terminal of the second PNP transistor 2472 can be coupled to the first latch input terminal; the base terminal of the first PNP transistor 2471 and the collector terminal of the second PNP transistor 2472 can be coupled to the second latch input terminal; the emitter terminal of the first PNP transistor 2471 and the emitter terminal of the second PNP transistor 2472 can be coupled together to a bias voltage (e.g., V _bias ). In some embodiments, the bias voltage V _bias May be ground, or a supply voltage for the second die, or a bias voltage having a specified value. In some embodiments, the bias voltage V _bias May be associated with a common mode input voltage of the latch.

The impedance characteristics of the common mode module 2407 are similar to those of the common mode module 2007 shown in fig. 20. In some embodiments, the common mode module 2407 may be disposed on the second die (VDD 2, GND 2). When there is no CMT, the voltages at nodes C and C' are relatively low, first PNP transistor 2471 and second PNP transistor 2472 may be turned off. When the voltage difference between the first ground terminal (e.g., GND 1) and the second ground terminal (e.g., GND 2) decreases, a negative CMT occurs between the first die and the second die, and the common mode current generated by the CMT flows from nodes C and C' to the first die through the first isolation module (i.e., the first input buffer) and the second isolation module (i.e., the second input buffer). Thus, the voltages at nodes C and C' may be lower than the bias voltage V _bias The first PNP transistor 2471 and the second PNP transistor 2472 can be turned on.

According to some embodiments, the common mode current may be associated with a common mode input impedance and a differential mode input impedance of the common mode module 2407. As the common mode current increases, the common mode input impedance decreases and the differential mode input impedance correspondingly increases. Thus, when negative CMT occurs, the common mode voltage caused by CMT may decrease and the differential mode voltage may increase, thereby enhancing the CMTI of the isolation circuit and amplifying the effective differential input signal of the latch.

Common mode input impedance R of common mode module 2407 _com This can be expressed by the following equation:

wherein gm is _pnp Is the transconductance of the cross-coupled PNP transistors (i.e., first PNP transistor 2471 and second PNP transistor 2472). The differential-mode input impedance of common-mode module 2407 may be represented by the following equation:

in some cases, transconductance g _mp May be proportional to the common mode current generated by the CMT. Transconductance g when the common mode current increases _mp And correspondingly increases. As shown in the above equation, the larger the transconductance, the smaller the common-mode input impedance and the larger the differential-mode input impedance. Due to the impedance characteristics of common mode module 2407, common mode noise may be reduced when negative CMT occurs between the first die and the second die And the magnitude of the effective differential input signal of the latch may be increased. Thus, the common mode module 2407 may be configured to enhance the CMTI of the isolation circuits and increase the effective differential input signal of the latches.

Fig. 25 schematically illustrates a diagram of a common mode module according to another embodiment of the disclosure. The diagram is merely an example, which should not unduly limit the scope of the claims. Those of ordinary skill in the art will recognize many variations, alternatives, and modifications. As described above, the common mode module 2507 may also be referred to as a common mode circuit. Common mode circuit 2507 may include a crossover circuit. The crossover circuit may include a first switch and a second switch. For example, the crossover circuit may include BJT transistors configured in the crossover circuit. In some embodiments, the common mode module 2507 may include a first input terminal configured to receive a first common mode input signal (i.e., a second differential signal), a second input terminal configured to receive a second common mode input signal (i.e., a fourth differential signal), a first NPN transistor 2571 (i.e., a first switch), and a second NPN transistor 2572 (i.e., a second switch).

According to some embodiments, the first NPN transistor 2571 and the second NPN transistor 2572 may be configured as a cross-coupled pair (i.e., a cross-circuit). The collector terminal of the first NPN transistor 2571 and the base terminal of the second NPN transistor 2572 can be coupled to the first latch input terminal; the base terminal of the first NPN transistor 2571 and the collector terminal of the second NPN transistor 2572 can be coupled to the second latch input terminal; the emitter terminal of the first NPN transistor 2571 and the emitter terminal of the second NPN transistor 2572 may be coupled together to a bias voltage (e.g., V _bias ). In some embodiments, the bias voltage V _bias May be ground, or a supply voltage for the second die, or a bias voltage having a specified value. In some embodiments, the bias voltage V _bias May be associated with a common mode input voltage of the latch.

In some embodiments, when the voltage difference between the first ground terminal GND1 and the second ground terminal GND2 increases, a positive CMT occurs between the first die and the second die, and the common mode current generated by the CMT passes through the first dieAn isolation module (i.e., a first input buffer) and/or a second isolation module (i.e., a second input buffer) flows from the first die to nodes C and C'. Thus, the voltages at nodes C and C' may be higher than the bias voltage V _bias The first NPN transistor 2571 and the second NPN transistor 2572 can be turned on. According to some embodiments, the common mode current may be associated with a common mode input impedance and a differential mode input impedance of common mode module 2507. As the common mode current increases, the common mode input impedance decreases and the differential mode input impedance correspondingly increases. Thus, when positive CMT occurs, the common mode voltage caused by CMT may decrease and the differential mode voltage may increase, thereby enhancing the CMTI of the isolation circuit and amplifying the effective differential input signal of the latch.

The impedance characteristics of the common mode module 2507 are similar to those of the common mode module 2207 shown in fig. 22. When positive CMT occurs between the first die and the second die, common mode noise may decrease and the magnitude of the effective differential input signal of the latch may increase. Thus, the common mode module 2507 may be configured to enhance the CMTI of the isolation circuit and increase the effective differential input signal of the latch.

Fig. 26 schematically illustrates a diagram of a common mode module according to an embodiment of the disclosure. The diagram is merely an example, which should not unduly limit the scope of the claims. Those of ordinary skill in the art will recognize many variations, alternatives, and modifications. As described above, the common mode module 2607 may also be referred to as a common mode circuit. The common mode circuit 2607 may include a first cross circuit 2608 and a second cross circuit 2609. For example, the first crossbar 2608 may include BJT transistors configured in the crossbar. For example, the second crossbar circuit 2609 may include BJT transistors configured in the crossbar circuit. According to some embodiments, the first crossover circuit 2608 may be coupled to a supply voltage (e.g., VDD 2) and the second crossover circuit 2609 may be coupled to a second ground terminal (e.g., GND 2). In some embodiments, the common mode module 2607 may include a first input terminal configured to receive a first common mode input signal (i.e., a second differential signal), a second input terminal configured to receive a second common mode input signal (i.e., a fourth differential signal), a first crossover circuit 2608 (also referred to as a "first common mode leg"), and a second crossover circuit 2609 (also referred to as a "second common mode leg"). The first common mode leg 2608 may include a first PNP transistor 2681 and a second PNP transistor 2682. The second common mode leg 2609 may include a first NPN transistor 2691 and a second NPN transistor 2692. The first common mode leg 2608 and the second common mode leg 2609 may be connected in parallel.

The impedance characteristics of the first cross circuit 2608 are similar to those of the common mode module 2407 shown in fig. 24, and the impedance characteristics of the second cross circuit 2609 are similar to those of the common mode module 2507 shown in fig. 25. In some embodiments, when the voltage difference between the first ground terminal (e.g., GND 1) and the second ground terminal (e.g., GND 2) decreases, a negative CMT occurs between the first die and the second die, and the common mode current generated by the CMT flows from nodes C and C' to the first die through the first isolation module (i.e., the first input buffer) and the second isolation module (i.e., the second input buffer). Thus, the voltages at nodes C and C' may be lower than the bias voltage V _bias The first common mode leg 2608 may be on while the second common mode leg 2609 is off.

The common mode current generated due to the negative CMT may be associated with the common mode input impedance and the differential mode input impedance of the first common mode leg 2608. As the common mode current increases, the common mode input impedance decreases and the differential mode input impedance correspondingly increases. The common-mode input impedance and the differential-mode input impedance of the first common-mode branch may be associated with an impedance value of each PNP transistor (e.g., 2681, 2682) of the first common-mode branch 2608. The first common mode leg 2608 may be configured to enhance the CMTI of the isolation circuit and increase the effective differential input signal of the latch during negative CMT.

When the voltage difference between the first ground terminal GND1 and the second ground terminal GND2 increases, a positive CMT occurs between the first die and the second die, and a common mode current generated by the CMT flows from the first die to the nodes C and C' through the first isolation module (i.e., the first input buffer) and the second isolation module (i.e., the second input buffer). Thus, the voltages at nodes C and C' may be higher than the bias voltage V _bias First, theThe two common mode legs 2609 may be on while the first common mode leg 2608 is off. The common mode current generated due to the positive CMT may be associated with the common mode input impedance and the differential mode input impedance of the second common mode leg 2609. As the common mode current increases, the common mode input impedance decreases and the differential mode input impedance correspondingly increases. Thus, when CMT occurs, the common mode voltage caused by CMT may decrease and the differential mode voltage may increase, thereby enhancing the CMTI of the isolation circuit and amplifying the effective differential input signal of the latch.

The common-mode input impedance and the differential-mode input impedance of the second common-mode leg may be associated with an impedance value of each NPN transistor (e.g., 2691, 2692) of the second common-mode leg 2609. The second common mode leg 2609 may be configured to enhance the CMTI of the isolation circuit and increase the effective differential input signal of the latch during negative CMT. The structure and operation of the common mode module 2607 prevents the isolation circuit from being disturbed by common mode transients regardless of the direction of the common mode current.

To increase flexibility in circuit design and enable flexible adjustment of impedance values of common mode circuit 2607, it should be appreciated that first common mode leg 2608 may further include a first diode (not shown) configured to be connected in parallel with first PNP transistor 2681 and second PNP transistor 2682, and/or second common mode leg 2609 may further include a second diode (not shown) configured to be connected in parallel with first NPN transistor 2691 and second NPN transistor 2692.

Fig. 27 schematically illustrates a flow chart of a method for providing isolation between two dies according to an embodiment of the disclosure. The diagram is merely an example, which should not unduly limit the scope of the claims. Those of ordinary skill in the art will recognize many variations, alternatives, and modifications. For example, one or more steps may be added, removed, replaced, repeated, rearranged, and/or overlapped without limiting the scope of the claims. A method for providing isolation between two dies may include:

s31, receiving an incoming signal;

s32, generating a differential signal based on the received incoming signal;

s33, providing isolation between the first die and the second die, and generating an isolation signal based on the differential signal, wherein the amplitude of the isolation signal is smaller than the amplitude of the input signal;

S34, processing the isolated signal by a common mode module to reduce common mode noise and amplify the effective differential isolated signal, wherein the processed isolated signal is amplified when CMT occurs;

s35, storing the isolation signal processed by the common mode module at a certain level for a certain time interval and outputting a latch signal;

s36, amplifying the latch signal and outputting the amplified signal.

Fig. 28 schematically illustrates a flow chart of a method for providing isolation between two dies according to another embodiment of the present disclosure. The diagram is merely an example, which should not unduly limit the scope of the claims. Those of ordinary skill in the art will recognize many variations, alternatives, and modifications. For example, one or more steps may be added, removed, replaced, repeated, rearranged, and/or overlapped without limiting the scope of the claims. In some embodiments, the method for providing isolation between two dies may further include a filtering step. As shown in fig. 15, the method for providing isolation between two dies may further include S41, S42, S43, S44, S45, S46, S47. In S42, the received incoming signal may be filtered before the differential signal is generated. Other steps of S41, S43, S44, S45, S46, S47 may be similar to the corresponding steps in fig. 27, and will not be described in detail below. The methods of fig. 27 and 28 may be implemented in any system that includes isolation circuitry according to embodiments of the present disclosure. For more details of this method reference is made to the description of the isolation circuit and will not be described in detail below.

While the above is a complete description of the specific embodiments, various modifications, alternative constructions, and equivalents may be used. Accordingly, the foregoing description and drawings should not be deemed to be a limitation on the scope of the invention, as defined by the appended claims.

Claims

1. A digital isolator device comprising:

a first input buffer configured to receive a first differential signal from a transmitter and provide a second differential signal, the first differential input signal characterized by a first magnitude, the second differential signal characterized by a second magnitude, the first magnitude greater than the second magnitude, the transmitter coupled to a first ground terminal, the first input buffer coupled to a second ground terminal;

a second input buffer configured to receive a third differential signal from the transmitter and provide a fourth differential signal, the second input buffer coupled to the second ground terminal;

a common mode circuit coupled to the second differential signal and the fourth differential signal, the common mode circuit coupled to a bias voltage and comprising a resistor pair, the common mode circuit configured to reduce a common mode transient voltage associated with a voltage difference between the first ground terminal and the second ground terminal; and

A latch circuit configured to store the second differential signal and the fourth differential signal for a time interval.

2. The digital isolator device according to claim 1, wherein the transmitter is configured on a first die and the common mode circuit is configured on a second die.

3. The digital isolator device according to claim 1, further comprising an amplifier coupled to the latch circuit.

4. The digital isolator device according to claim 1, wherein said common mode circuit further comprises a crossover circuit.

5. The digital isolator device according to claim 4, wherein the crossover circuit includes a first switch and a second switch, the first switch coupled to the second differential signal, the second switch coupled to the fourth differential signal.

6. The digital isolator device according to claim 5, wherein:

the first switch includes a first drain, a first source, and a first gate, the first source coupled to the bias voltage, the first gate coupled to the second differential signal, the first drain coupled to the fourth differential signal; and is also provided with

The second switch includes a second drain, a second source, and a second gate, the second source coupled to the bias voltage, the second gate coupled to the fourth differential signal, the second drain coupled to the third differential signal.

7. The digital isolator device according to claim 5, wherein said crossover circuit is coupled to a supply voltage.

8. The digital isolator device according to claim 5, wherein said crossover circuit is coupled to said second ground terminal.

9. The digital isolator device according to claim 1, wherein the common mode circuit further comprises a first crossover circuit coupled to a supply voltage and a second crossover circuit coupled to the second ground terminal.

10. The digital isolator device according to claim 9, wherein said first crossover circuit includes a first pair of switches configured in parallel and a second pair of switches configured in parallel.

11. The digital isolator device according to claim 1, wherein the common mode circuit comprises PMOS transistors configured in a crossover circuit.

12. The digital isolator device according to claim 1, wherein the common mode circuit comprises BJT transistors configured in a crossover circuit.

13. The digital isolator device according to claim 1, wherein:

the first input buffer includes a first capacitor directly coupled to the first differential signal and a second capacitor directly coupled to the second ground terminal; and is also provided with

The second input buffer includes a third capacitor directly coupled to the third differential signal and a fourth capacitor directly coupled to the second ground terminal.

14. The digital isolator device according to claim 1, further comprising an inverter configured to generate the third differential signal.

15. A digital isolator device comprising:

a latch module configured to store a first isolation signal and a second isolation signal for a time interval and output a latch signal, the latch module comprising:

a first latch input terminal configured to receive a first latch input signal; and

a second latch input terminal configured to receive a second latch input signal;

a common mode module configured to receive a common mode current generated due to a common mode transient between a first die and a second die, the common mode module comprising:

a first input terminal coupled to the first latch input terminal and configured to receive a first common mode input signal;

A second input terminal coupled to the second latch input terminal and configured to receive a second common mode input signal;

a first common mode leg coupled to the first input terminal and characterized by a first impedance value; and

a second common mode leg coupled to the second input terminal and characterized by a second impedance value;

wherein the latch module and the common mode module are connected in parallel;

wherein the common mode current flowing through the common mode module is associated with a common mode voltage and a differential mode voltage of the latch module.

16. The digital isolator device according to claim 15, wherein:

the common mode current is associated with the first impedance value of the first common mode leg, the first impedance value being associated with the first latch input signal; and is also provided with

The common mode current is associated with a second impedance value of the second common mode leg, the second impedance value being associated with the second latch input signal of the latch module.

17. The digital isolator device according to claim 15, wherein the common mode module is coupled to a bias voltage that is associated with a common mode voltage of the latch module.

18. The digital isolator device according to claim 15, wherein:

when the input voltage of the latch module is lower than the bias voltage, the first common mode branch is conducted; and is also provided with

The second common mode leg is turned on when the input voltage of the latch module is higher than the bias voltage.